Commit Graph

170973 Commits

Author SHA1 Message Date
NAKAMURA Takumi 4cf1a3be82 llvm/test/Transforms/LoopStrengthReduce/ARM64/lsr-*.ll: Add explicit triple arm64-unknown for targeting pecoff.
llvm-svn: 205125
2014-03-30 05:01:04 +00:00
NAKAMURA Takumi 09717bd1c4 X86Subtarget.h: isTargetWindows() should tell whether he is targeting msvc.
FYI, !isWindowsGNUEnvironment() is insufficient. It missed cygwin.

FIXME: The name "isTargetWindows" should be fixed.
llvm-svn: 205124
2014-03-30 04:35:00 +00:00
Lang Hames c339840666 [MC] Remove an unused (and broken) variant of the setupForSymbolicDisassembly
method in MCDisassembler.

llvm-svn: 205123
2014-03-30 04:27:33 +00:00
Lang Hames 652b0a4f3b [PBQP] Move invalid graph nodeId/edgeId methods into base class.
llvm-svn: 205122
2014-03-30 03:47:00 +00:00
Rafael Espindola 5e66a7e699 Add a missing break.
Patch by Tobias Güntner.

I tried to write a test, but the only difference is the Changed value that
gets returned. It can be tested with "opt -debug-pass=Executions -functionattrs,
but that doesn't seem worth it.

llvm-svn: 205121
2014-03-30 03:26:17 +00:00
Saleem Abdulrasool ceec2cba64 Support: normalize the default triple on Unix
This will fix cross-compiling buildbots (e.g. cygwin).  This is in the same vein
as SVN r205070.  Apply this to fix the cross-compiling scenario, even though the
preferred solution is to update the build system to normalize the embedded
triple rather than perform this at runtime every time.  This is meant to tide us
over until that approach is fleshed out and applied.

llvm-svn: 205120
2014-03-30 03:22:37 +00:00
Rafael Espindola 986b14c507 Remove dead declarations.
Patch by Tobias Güntner.

llvm-svn: 205119
2014-03-30 02:33:01 +00:00
Benjamin Kramer 4d951abf1f Remove outdated comment.
llvm-svn: 205117
2014-03-29 20:16:23 +00:00
Dmitri Gribenko 1fd72104ad Fix a few -Wdocumentation warnings
llvm-svn: 205116
2014-03-29 19:40:32 +00:00
Jason Molenda f8310d40c8 Include string.h for memset() prototype. Thanks Dmitri.
llvm-svn: 205115
2014-03-29 19:29:04 +00:00
Benjamin Kramer 3ad660a515 Detemplatize LOHDirective.
The ARM64 backend uses it only as a container to keep an MCLOHType and
Arguments around so give it its own little copy. The other functionality
isn't used and we had a crazy method specialization hack in place to
keep it working. Unfortunately that was incompatible with MSVC.

Also range-ify a couple of loops while at it.

llvm-svn: 205114
2014-03-29 19:21:20 +00:00
Jason Molenda a332978b2a lldb arm64 import.
These changes were written by Greg Clayton, Jim Ingham, Jason Molenda.

It builds cleanly against TOT llvm with xcodebuild.  I updated the
cmake files by visual inspection but did not try a build.  I haven't
built these sources on any non-Mac platforms - I don't think this
patch adds any code that requires darwin, but please let me know if
I missed something.

In debugserver, MachProcess.cpp and MachTask.cpp were renamed to
MachProcess.mm and MachTask.mm as they picked up some new Objective-C
code needed to launch processes when running on iOS.

llvm-svn: 205113
2014-03-29 18:54:20 +00:00
Benjamin Kramer 61e595be4d ARM64: Remove unused helper function, make others static.
llvm-svn: 205112
2014-03-29 18:00:49 +00:00
Tim Northover fe7a445bf7 Install: add arm_neon.h header back
I'd gone too far pruning aarch64_simd.h this time and took out one
instance of arm_neon.h. This should restore us to the status quo.

llvm-svn: 205111
2014-03-29 17:35:34 +00:00
Benjamin Kramer 48e7e85d29 tblgen: Twinify PrintFatalError.
No functionality change.

llvm-svn: 205110
2014-03-29 17:17:15 +00:00
Tim Northover 4e55afed7e TableGen: don't save a StringRef to a local std::string.
This caused a failure in some Windows builds.

llvm-svn: 205109
2014-03-29 16:59:27 +00:00
Benjamin Kramer fd719b9551 Avoid storing Twines.
While there nested ifs into a helper function. No functionality change.

llvm-svn: 205108
2014-03-29 16:54:29 +00:00
Benjamin Kramer 543c74303b Avoid a local Twine variable.
Harmless in this case but potentially dangerous if it gets extended some day.

llvm-svn: 205107
2014-03-29 16:54:24 +00:00
Hal Finkel 777c9dd90a [PowerPC] Handle v2i64 comparisons
v2i64 is a legal type under VSX, however we don't have native vector
comparisons. We can handle eq/ne by casting it to an Altivec type, but
everything else must be expanded.

llvm-svn: 205106
2014-03-29 16:04:40 +00:00
Tim Northover adbd34e045 ARM64: format register strings without creating a local Twine.
It was causing horrible failures on some build-bots.

llvm-svn: 205105
2014-03-29 15:35:57 +00:00
Tim Northover 97606edd75 ARM64: Fix GCC warning in CGBuiltin.cpp
llvm-svn: 205104
2014-03-29 15:26:07 +00:00
Tim Northover dca92dbc82 Remove stray references to aarch64_simd.h
They were causing the autotools builds to fail.

llvm-svn: 205103
2014-03-29 15:21:06 +00:00
Logan Chien 8faefa2d31 llvm-mc: Fix build breakage caused by r205050.
When LLVM is not built with zlib, nocompression.s will test
for the error message.  But this test case will cause breakage
because the exit code is non-zero.  This commit fix this issue
by adding "not" to the command.

llvm-svn: 205102
2014-03-29 15:10:22 +00:00
Tim Northover 618ca29317 CodeGen: Allow different RTTI emission strategies
Some ABIs and C++ libraries may make different trade-offs in how RTTI
is emitted (currently with respect to visibility and so on). This
implements one scheme, as used by ARM64.

llvm-svn: 205101
2014-03-29 15:09:55 +00:00
Tim Northover a2ee433c8d ARM64: initial clang support commit.
This adds Clang support for the ARM64 backend. There are definitely
still some rough edges, so please bring up any issues you see with
this patch.

As with the LLVM commit though, we think it'll be more useful for
merging with AArch64 from within the tree.

llvm-svn: 205100
2014-03-29 15:09:45 +00:00
David Majnemer af3698066a CodeGen: Don't crash when replacing functions
The peculiarities of C99 create scenario where an LLVM IR function
declaration may need to be replaced with a definition baring a different
type because the prototype and definition are not required to agree.

However, we were not properly deferring this when it occurred.

This fixes PR19280.

llvm-svn: 205099
2014-03-29 14:19:55 +00:00
Tim Northover 238b508aaf ARM64: parametrise IVar offset type (long on ARM64, int elsewhere).
This is part of the ARM64 patch, but can only be tested properly when
the full codegen gets committed.

llvm-svn: 205098
2014-03-29 13:42:40 +00:00
Tim Northover e77cc39aff ObjC: allow targets to decide when to use stret for blocks.
This was originally part of the ARM64 patch, but seems semantically
separate.

llvm-svn: 205097
2014-03-29 13:28:05 +00:00
Hal Finkel e8fba98735 [PowerPC] VSX instruction latency corrections
The vector divide and sqrt instructions have high latencies, and the scalar
comparisons are like all of the others. On the P7, permutations take an extra
cycle over purely-simple vector ops.

llvm-svn: 205096
2014-03-29 13:20:31 +00:00
Tim Northover 336f189b61 Driver: implement addClangWarningOptions
This function allows certain platforms to enable or disable diagnostics
by default.

llvm-svn: 205095
2014-03-29 13:16:12 +00:00
Stepan Dyatkovskiy df657cc1d5 Recommitted fix for PR18931, with extended tests set.
Issue subject: Crash using integrated assembler with immediate arithmetic

Fix description:
Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage,
since it is impossible to resolve labels on this stage. In the end of stage we still have
expression (MCExpr).
Then, when we want to encode it, we expect it to be an immediate, but it still an expression.
Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage.

llvm-svn: 205094
2014-03-29 13:12:40 +00:00
Tim Northover 2125374ecf ARM64: use 64-bit constant even on 32-bit machines
Another existing bot failure so no tests.

llvm-svn: 205093
2014-03-29 11:51:49 +00:00
Tim Northover 2011df293d ARM64: change format specifier to work on 32-bit targets
Existing tests were failing.

llvm-svn: 205092
2014-03-29 11:47:07 +00:00
Chandler Carruth 7b7a67c5c8 [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it is
no assert at all. ;] Some of these should probably be switched to
llvm_unreachable, but I didn't want to perturb the behavior in this
patch.

Found by -Wstring-conversion, which I'll try to turn on in CMake builds
at least as it is finding useful things.

llvm-svn: 205091
2014-03-29 11:07:40 +00:00
Tim Northover 00ed9964c6 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

llvm-svn: 205090
2014-03-29 10:18:08 +00:00
Tim Northover 3e38d290c8 TableGen: avoid dereferencing nullptr variable
ARM64 ended up reaching odder parts of TableGen alias generation than
current backends and caused a segfault.

llvm-svn: 205089
2014-03-29 09:03:22 +00:00
Tim Northover 753eca0f78 CodeGen: add sensible defaults for the ISD::FROUND operation
Some exotic types didn't know how to handle FROUND, which ARM64 uses.

llvm-svn: 205088
2014-03-29 09:03:18 +00:00
Tim Northover d1c6f51730 MC-exceptions: add support for compact-unwind without .eh_frame
ARM64 has compact-unwind information, but doesn't necessarily want to
emit .eh_frame directives as well. This teaches MC about such a
situation so that it will skip .eh_frame info when compact unwind has
been successfully produced.

For functions incompatible with compact unwind, the normal information
is still written.

llvm-svn: 205087
2014-03-29 09:03:13 +00:00
Tim Northover cea0abb60a CodeGenPrep: wrangle IR to exploit AArch64 tbz/tbnz inst.
Given IR like:
    %bit = and %val, #imm-with-1-bit-set
    %tst = icmp %bit, 0
    br i1 %tst, label %true, label %false

some targets can emit just a single instruction (tbz/tbnz in the
AArch64 case). However, with ISel acting at the basic-block level, all
three instructions need to be together for this to be possible.

This adds another transformation to CodeGenPrep to expose these
opportunities, if targets opt in via the hook.

llvm-svn: 205086
2014-03-29 08:22:29 +00:00
Tim Northover 0999cbd0b9 MC: add a RefKind field to MCValue
This is principally to allow neater mapping of fixups to relocations
in ARM64 ELF. Without this, there isn't enough information available
to GetRelocType, leading to many more fixup_arm64_... enumerators.

llvm-svn: 205085
2014-03-29 08:22:20 +00:00
Tim Northover 53d3251851 MachO: Add linker-optimisation hint framework to MC.
Another part of the ARM64 backend (so tests will be following soon).
This is currently used by the linker to relax adrp/ldr pairs into nops
where possible, though could well be more broadly applicable.

llvm-svn: 205084
2014-03-29 07:34:53 +00:00
Tim Northover 5627670e84 MachO: actually set linker-private prefix at MC level.
This was accidentally omitted from r205081.

llvm-svn: 205083
2014-03-29 07:33:24 +00:00
Jason Molenda d5dd36a020 Link against the zlib solib, required to build against TOT llvm.
llvm-svn: 205082
2014-03-29 07:11:52 +00:00
Tim Northover c3988b4aa3 MachO: allow each section to have a linker-private symbol
The upcoming ARM64 backend doesn't have section-relative relocations,
so we give each section its own symbol to provide this functionality.
Of course, it doesn't need to appear in the final executable, so
linker-private is the best kind for this purpose.

llvm-svn: 205081
2014-03-29 07:05:06 +00:00
Tim Northover 9086f061f0 Make GetCPISymbol a virtual method.
ARM64 for iOS is going to want to emit these symbols in a
linker-private style for efficiency, but other targets probably don't
want that behaviour.

llvm-svn: 205080
2014-03-29 07:04:59 +00:00
Tim Northover 4516de3412 Intrinsics: add LLVMHalfElementsVectorType constraint
This is like the LLVMMatchType, except the verifier checks that the
second argument is a vector with the same base type and half the
number of elements.

This will be used by the ARM64 backend.

llvm-svn: 205079
2014-03-29 07:04:54 +00:00
Rafael Espindola e2bab04b85 Forgot to replace a %t1 in the previous commit.
llvm-svn: 205078
2014-03-29 06:45:26 +00:00
Rafael Espindola 90eeff28c6 Check in binaries to avoid dependency on broken llvm-mc behavior.
On these tests llvm-mc will convert got relocations with a symbol to section
relocations. This is invalid, since the relocation doesn't reference the symbol
itself, so its offset in a section in irrelevant.

Given the object files, these are still valid lld tests, so just run the
tests directly on the binaries.

Found by running check-lld after fixing the relocation handling in llvm-mc.

llvm-svn: 205077
2014-03-29 06:26:51 +00:00
Rafael Espindola 5904e12bfa Completely rewrite ELFObjectWriter::RecordRelocation.
I started trying to fix a small issue, but this code has seen a small fix too
many.

The old code was fairly convoluted. Some of the issues it had:

* It failed to check if a symbol difference was in the some section when
  converting a relocation to pcrel.
* It failed to check if the relocation was already pcrel.
* The pcrel value computation was wrong in some cases (relocation-pc.s)
* It was missing quiet a few cases where it should not convert symbol
  relocations to section relocations, leaving the backends to patch it up.
* It would not propagate the fact that it had changed a relocation to pcrel,
  requiring a quiet nasty work around in ARM.
* It was missing comments.

llvm-svn: 205076
2014-03-29 06:26:49 +00:00
Hal Finkel 19be506a5e [PowerPC] Add subregister classes for f64 VSX values
We had stored both f64 values and v2f64, etc. values in the VSX registers. This
worked, but was suboptimal because we would always spill 16-byte values even
through we almost always had scalar 8-byte values. This resulted in an
increase in stack-size use, extra memory bandwidth, etc. To fix this, I've
added 64-bit subregisters of the Altivec registers, and combined those with the
existing scalar floating-point registers to form a class of VSX scalar
floating-point registers. The ABI code has also been enhanced to use this
register class and some other necessary improvements have been made.

llvm-svn: 205075
2014-03-29 05:29:01 +00:00