llvm-project

Commit Graph

Author	SHA1	Message	Date
Dan Gohman	c8054d90fb	Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81293	2009-09-09 00:09:15 +00:00
Dan Gohman	a5b9645c4b	Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897	2009-06-04 22:49:04 +00:00
Evan Cheng	3c12fc4342	On some targets, non-move instructions can become move instructions because of coalescing. e.g. vr2 = OR vr0, vr1 => vr2 = OR vr1, vr1 // after coalescing vr0 with vr1 Update the value# of the destination register with the copy instruction if that happens. llvm-svn: 56165	2008-09-12 18:13:14 +00:00

Author

SHA1

Message

Date

Dan Gohman

c8054d90fb

Eliminate more uses of llvm-as and llvm-dis.

llvm-svn: 81293

2009-09-09 00:09:15 +00:00

Dan Gohman

a5b9645c4b

Split the Add, Sub, and Mul instruction opcodes into separate

integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897

2009-06-04 22:49:04 +00:00

Evan Cheng

3c12fc4342

On some targets, non-move instructions can become move instructions because of coalescing. e.g.

vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1   // after coalescing vr0 with vr1

Update the value# of the destination register with the copy instruction if that happens.

llvm-svn: 56165

2008-09-12 18:13:14 +00:00

3 Commits