Commit Graph

388437 Commits

Author SHA1 Message Date
Roman Lebedev 9acc589e5a
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VPANDN tests 2021-05-14 20:22:59 +03:00
Roman Lebedev a3617138c2
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VPANDN tests 2021-05-14 20:22:59 +03:00
Roman Lebedev 3f235a0b84
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PANDN tests 2021-05-14 20:22:59 +03:00
Roman Lebedev 1d73c2b8cf
[X86] AMD Zen 3: same-reg AVX YMM VPXOR is a zero-cycle(!) dep-breaking zero-idiom
As confirmed by exegesis measurements, and ref docs.
2021-05-14 20:22:59 +03:00
Roman Lebedev 31669b5073
[X86] AMD Zen 3: same-reg AVX XMM VPXOR is a zero-cycle(!) dep-breaking zero-idiom
As confirmed by exegesis measurements, and ref docs.
2021-05-14 20:22:58 +03:00
Roman Lebedev 498bf365f4
[X86] AMD Zen 3: same-reg SSE XMM PXOR is a 1-cycle(!) dep-breaking zero-idiom
As confirmed by the exegesis measurements, and ref docs.
2021-05-14 20:22:58 +03:00
Roman Lebedev 3009f8a383
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VPXOR tests 2021-05-14 20:22:58 +03:00
Roman Lebedev d58d020b6c
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VPXOR tests 2021-05-14 20:22:58 +03:00
Roman Lebedev 0f7a595095
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PXOR tests 2021-05-14 20:22:58 +03:00
Benjamin Kramer d4d80a2903 Bump googletest to 1.10.0 2021-05-14 19:16:31 +02:00
Philip Reames e488bf815f Revert "Do actual DCE in LoopUnroll"
This reverts commit 9d1a61e695.

I'd missed some review feedback, and had missed updating an aarch64 test.  Reverting while I fix both.
2021-05-14 10:15:30 -07:00
Philip Reames 9d1a61e695 Do actual DCE in LoopUnroll
LoopUnroll does a limited DCE pass after unrolling, but if you have a chain of dead instructions, it only deletes the last one. Improve the code to recursively delete all trivially dead instructions.

Differential Revision: https://reviews.llvm.org/D102511
2021-05-14 10:05:25 -07:00
Matt Morehouse b7d1ab75cf [HWASan] Add aliasing flag and enable HWASan to use it.
-fsanitize-hwaddress-experimental-aliasing is intended to distinguish
aliasing mode from LAM mode on x86_64.  check-hwasan is configured
to use aliasing mode while check-hwasan-lam is configured to use LAM
mode.

The current patch doesn't actually do anything differently in the two
modes.  A subsequent patch will actually build the separate runtimes
and use them in each mode.

Currently LAM mode tests must be run in an emulator that
has LAM support.  To ensure LAM mode isn't broken by future patches, I
will next set up a QEMU buildbot to run the HWASan tests in LAM.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102288
2021-05-14 09:47:20 -07:00
Anastasia Stulova 769cc335e6 [OpenCL] Simplify use of C11 atomic types.
Remove requirements on extension pragma in atomic types
because it has not respected the spec wrt disabling types
and hasn't been useful either. With this change, the
developers can use atomic types from the extensions if they
are supported without enabling the pragma just like the builtin
functions

This patch does not break backward compatibility since the
extension pragma is still supported and it makes the behavior of
the compiler less strict by accepting code without needless and
inconsistent pragma statements.

Differential Revision: https://reviews.llvm.org/D100976
2021-05-14 17:43:00 +01:00
Fangrui Song 4adf7a7604 [ELF] Add -Bno-symbolic
This option will be available in GNU ld 2.27 (https://sourceware.org/bugzilla/show_bug.cgi?id=27834).
This option can cancel previously specified -Bsymbolic and
-Bsymbolic-functions.  This is useful for excluding some links when the
default uses -Bsymbolic-functions.

Reviewed By: jhenderson, peter.smith

Differential Revision: https://reviews.llvm.org/D102383
2021-05-14 09:40:32 -07:00
Fangrui Song da9b6d0656 [ELF][test] Improve -Bsymbolic & -Bsymbolic-functions test
Previously there was no test checking that -Bsymbolic-functions only applies to STT_FUNC symbols.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D102461
2021-05-14 09:33:43 -07:00
Philip Reames 6594bac06c Autogen a test for ease of update 2021-05-14 09:33:17 -07:00
Florian Hahn c62f984814
[LV] Add a few more complex first-order recurrence tests. 2021-05-14 17:27:17 +01:00
Bradley Smith 12a74137b3 [AArch64][SVE] Combine cntp intrinsics with add/sub to produce incp/decp
Depends on D101062

Differential Revision: https://reviews.llvm.org/D102077
2021-05-14 17:16:06 +01:00
Benoit Jacob e0a88db545 Fix some typos.
Fix some typos

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D102503
2021-05-14 21:34:09 +05:30
Simon Pilgrim b95a103808 [X86][SSE] Pull out combineToHorizontalAddSub helper from inside (F)ADD/SUB combines. NFCI.
The intention is to be able to run this from additional locations (such as shuffle combining) in the future.
2021-05-14 16:52:55 +01:00
Mark de Wever a85b1320b6 [libc++] Improve make_string test support.
Adds MAKE_CSTRING and makes the operators of `MultiStringType` `constexpr`.

The code is copied from D96664 so it can be used in D80895.

Differential Revision: https://reviews.llvm.org/D102414
2021-05-14 17:42:17 +02:00
Benjamin Kramer 4dd546131a Bump googletest to 1.8.1
We've accumulated a scary amount of local patches to this directory. I
tried to merge them all, but if your favorite change is missing please
reapply it manually (and send it upstream).
2021-05-14 17:20:06 +02:00
Bradley Smith 90ffcb1245 [AArch64][SVE] Add unpredicated vector BIC ISD node
Addition of this node allows us to better utilize the different forms of
the SVE BIC instructions, including using the alias to an AND (immediate).

Differential Revision: https://reviews.llvm.org/D101831
2021-05-14 16:12:13 +01:00
Philip Reames 3f1c218318 [rs4gc] Strip memory related attributes consistently
I noticed that rs4gc is not stripping a number of memory aliasing related attributes. We do strip some from call sites, but don't strip the same ones from declarations or parameters.

Why do we need to strip these? Two answers:

    Safepoints conceptually read and write to the entire garbage collected heap in the physical model. We need this to preserve ordering of all loads and stores with respect to possible relocation.
    We can infer other attributes from these. For instance, readnone can imply both nofree and nosync. Both of which don't hold after physical rewriting.

Note: This exposed a latent issue which was fixed a couple weeks back in 01801d5274.

Differential Revision: https://reviews.llvm.org/D99802
2021-05-14 07:54:56 -07:00
Kadir Cetinkaya ed339111bf
[clangd] Always default to raw pch format
Clang would emit a fatal error when it encounters an unregistered PCH
format. This change ensures clangd will always use raw format no matter what
user specifies.

As side effects:

- serializing an AST in an unknown format might throw off build
systems. I suppose this would only be an issue when build system and clangd are
racing for same PCM modules, hopefully this should be rare and both clangd or
the build system should recover on the next run.

- whenever clang reads a serialized AST it seems to be checking for file
signature and emitting non-fatal errors. so this should be fine again.

The only other valid module format in clang is `obj` but it is part of codegen,
i don't think it is worth the dependency. Hence chosing to not register it, at
least yet.

Differential Revision: https://reviews.llvm.org/D102418
2021-05-14 16:34:57 +02:00
David Spickett 810d4a6ff6 [utils] Don't print username in arcanist clang format message
I didn't realise this message was also posted to the phabricator review.

Just say "the user's local path". "local" is the important part,
the username is not important.
2021-05-14 14:33:00 +00:00
David Green ce76093c3c [ARM] Expand predecessor search to multiple blocks when reverting WhileLoopStarts
We were previously only searching a single preheader for call
instructions when reverting WhileLoopStarts to DoLoopStarts. This
extends that to multiple blocks that can come up when, for example a
loop is expanded from a memcpy. It also expends the instructions from
just Call's to also include other LoopStarts, to catch other low
overhead loops in the preheader.

Differential Revision: https://reviews.llvm.org/D102269
2021-05-14 15:08:14 +01:00
David Green 11b34e78c1 [ARM] Define CPSR on MEMCPY pseudos
These pseudos are converted post-isel into t2WhileLoopStart and
t2LoopEnd/LoopDec instructions, which themselves are defined to clobber
CPSR. Doing the same with the MEMCPY nodes will make sure they are
scheduled correctly to not end up with incorrect uses.
2021-05-14 15:06:59 +01:00
Hsiangkai Wang b41e1306b8 [RISCV] Add the DebugLoc parameter to getVLENFactoredAmount().
The MachineBasicBlock::iterator is continuously changing during
generating the frame handling instructions. We should use the DebugLoc
from the caller, instead of getting it from the changing iterator.

If the prologue instructions located in a basic block without any other
instructions after these prologue instructions, the iterator will be
updated to the boundary of the basic block and it is invalid to use the
iterator to access DebugLoc. This patch also fixes the crash when
accessing DebugLoc using the iterator.

Differential Revision: https://reviews.llvm.org/D102386
2021-05-14 21:31:06 +08:00
David Candler 3d59f9d224 [ARM][AArch64] Correct __ARM_FEATURE_CRYPTO macro and crypto feature
This patch contains a couple of minor corrections to my previous
crypto patch:

Since both AArch32 and AArch64 are now correctly setting the aes and
sha2 features individually, it is not necessary to continue to check
the crypto feature when defining feature macros.

In the AArch32 driver, the feature vector is only modified when the
crypto feature is actually in the vector. If crypto is not present,
there is no need to split it and explicitly define crypto/sha2/aes.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D102406
2021-05-14 14:19:46 +01:00
Dmitry Preobrazhensky 434b278cde [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- added description of GFX90A;
- minor bugfixing and improvements.
2021-05-14 16:13:30 +03:00
Nemanja Ivanovic 7cd2833311 [PowerPC] Add vec_vupkhpx and vec_vupklpx for XL compatibility
These are old names for these functions that XL still supports.
2021-05-14 08:02:00 -05:00
Sanjay Patel 9dfd7f9b67 [SDAG] reduce code duplication for extend_vec_inreg combines; NFC
These are identical so far, and I was looking at adding a fold
for a pattern with scalar_to_vector which would also nd up duplicated.
2021-05-14 08:29:57 -04:00
Nathan Sidwell 0566f97961 [clang][NFC] remove unused return value
In working on p0388 (ary[N] -> ary[] conversion), I discovered neither
use of UnwrapSimilarArrayTypes used the return value. So let's nuke
it.

Differential Revision: https://reviews.llvm.org/D102480
2021-05-14 05:25:47 -07:00
Djordje Todorovic 01c90bbd4f [Transforms][Debugify] Fix "Missing line" false alarm on PHI nodes
This is a fix for https://bugs.llvm.org/show_bug.cgi?id=49959

The "Missing line" false alarm was introduced in D75242.

Patch by Yilong Guo<yilong.guo@intel.com>

Differential Revision: https://reviews.llvm.org/D100446
2021-05-14 14:06:13 +02:00
Jay Foad 6ec66f681c [TableGen] Remove unneeded forward defs. NFC. 2021-05-14 12:36:20 +01:00
Roman Lebedev 4af4afe014
[X86] AMD Zen 3: same-reg AVX YMM VANDNPD is a zero-cycle(!) dep-breaking zero-idiom
As confirmed by exegesis measurements, and ref docs.
2021-05-14 14:06:24 +03:00
Roman Lebedev 17f99a8a41
[X86] AMD Zen 3: same-reg AVX XMM VANDNPD is a zero-cycle(!) dep-breaking zero-idiom
As confirmed by exegesis measurements, and ref docs.
2021-05-14 14:06:24 +03:00
Roman Lebedev 38ceb46fb0
[X86] AMD Zen 3: same-reg SSE XMM ANDNPD is a 1-cycle(!) dep-breaking zero-idiom
As confirmed by exegesis measurements, and ref docs.
2021-05-14 14:06:24 +03:00
Roman Lebedev 3221e06e9b
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VANDNPD tests 2021-05-14 14:06:24 +03:00
Roman Lebedev 0b7e52e725
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VANDNPD tests 2021-05-14 14:06:24 +03:00
Roman Lebedev 055fa84cd8
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM ANDNPD tests 2021-05-14 14:06:24 +03:00
Roman Lebedev d8a595b81c
[X86] AMD Zen 3: same-reg AVX YMM VANDNPS is a zero-cycle(!) dep-breaking zero-idiom
As confirmed by exegesis measurements, and ref docs.
2021-05-14 14:06:24 +03:00
Roman Lebedev fd4cbc822b
[X86] AMD Zen 3: same-reg AVX XMM VANDNPS is a zero-cycle(!) dep-breaking zero-idiom
As confirmed by exegesis measurements, and ref docs.
2021-05-14 14:06:23 +03:00
Roman Lebedev f38dcbecb6
[X86] AMD Zen 3: same-reg SSE XMM ANDNPS is a 1-cycle(!) dep-breaking zero-idiom
Same as SSE XMM XORPS/XORPD, it is not zero-cycle, even though it breaks the deps.
As confirmed by the exegesis measurements, and ref docs.
2021-05-14 14:06:23 +03:00
Roman Lebedev c79c7bb980
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VANDNPS tests 2021-05-14 14:06:23 +03:00
Roman Lebedev a57006d627
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VANDNPS tests 2021-05-14 14:06:23 +03:00
Roman Lebedev a657808948
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM ANDNPS tests 2021-05-14 14:06:23 +03:00
Sander de Smalen f82966d19a [LoopVectorizationLegality] NFC: Mark some interfaces as 'const'
This patch marks blockNeedsPredication, isConsecutivePtr, isMaskRequired
and getSymbolicStrides as 'const'.
2021-05-14 11:53:54 +01:00