Commit Graph

2828 Commits

Author SHA1 Message Date
Eli Friedman f6fbfd3f83 Last batch of test conversions to new atomic instructions.
llvm-svn: 140585
2011-09-27 00:17:29 +00:00
Eli Friedman a486cb972f Convert a bunch more tests over to the new atomic instructions.
llvm-svn: 140582
2011-09-26 23:15:09 +00:00
Jakob Stoklund Olesen 55cf2ed148 Only run MF.verify() with EXPENSIVE_CHECKS=1.
llvm-svn: 140441
2011-09-24 01:11:19 +00:00
Jakob Stoklund Olesen 3bb99bc957 Verify that terminators follow non-terminators.
This exposes a -segmented-stacks bug.

llvm-svn: 140429
2011-09-23 22:45:39 +00:00
Eli Friedman 8a15a5aa93 PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that.
llvm-svn: 140428
2011-09-23 22:41:57 +00:00
Eli Friedman 64a4bf1788 PR10989: Don't print .hidden on Windows.
llvm-svn: 140356
2011-09-23 00:13:02 +00:00
Eli Friedman 87c844cdf8 PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.)
llvm-svn: 140355
2011-09-22 23:41:28 +00:00
Duncan Sands 0e4fcb8e3b Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from
floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.

llvm-svn: 140332
2011-09-22 20:15:48 +00:00
Devang Patel 5e6b65cf0d Do not unnecessarily use AT_specification DIE because it does not add any value.
Few weeks ago, llvm completely inverted the debug info graph. Earlier each debug info node used to keep track of its compile unit, now compile unit keeps track of important nodes. One impact of this change is that the global variable's do not have any context, which should be checked before deciding to use AT_specification DIE.

llvm-svn: 140282
2011-09-21 23:41:11 +00:00
Nadav Rotem 253a7391ee add another testcase for pr10902
llvm-svn: 140257
2011-09-21 17:13:40 +00:00
Nadav Rotem bc9ba30158 [VECTOR-SELECT] Address one of the bugs in pr10902.
Vector SetCC result types need to be type-legalized.
This code worked before because scalar result types are known to be legal.

llvm-svn: 140249
2011-09-21 14:34:38 +00:00
Bruno Cardoso Lopes 6cb23f6e7f Add a DAGCombine for subvector extracts to remove useless chains of
subvector inserts and extracts. Initial patch by Rackover, Zvi with
some tweak done by me.

llvm-svn: 140204
2011-09-20 23:19:33 +00:00
Bruno Cardoso Lopes 8058234b32 Revert r140097, working on a better approach
llvm-svn: 140203
2011-09-20 23:19:29 +00:00
NAKAMURA Takumi 011be52871 test/CodeGen/X86/avx-minmax.ll: Unbreak Win32.
On Windows x64, 128-bit arguments are not passed by reg but by indirect. eg.

maxpd:
        vmovapd (%rcx), %xmm0
        vmaxpd  (%rdx), %xmm0, %xmm0

FIXME: I don't care YMM on x64 for now.
llvm-svn: 140143
2011-09-20 14:11:35 +00:00
Craig Topper 68c92d86da Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd.
llvm-svn: 140140
2011-09-20 07:38:59 +00:00
Bruno Cardoso Lopes 0828ab04bf Attempt to fix -mtriple=i686-{cygwin|mingw|win32} regressions. Nakamura,
if this doesn't work, please provide more details.

llvm-svn: 140107
2011-09-20 00:08:12 +00:00
Bruno Cardoso Lopes 51792dcc4d Based on the small opt Zvi's patch was trying to achieve, eliminate
128-bit undef subvector insertion into a 256-bit vector

llvm-svn: 140097
2011-09-19 23:36:50 +00:00
Bruno Cardoso Lopes d4a3d452d4 Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix
PR10955 and PR10948.

llvm-svn: 140069
2011-09-19 21:29:24 +00:00
Nadav Rotem 261a10a007 setOperationAction should be done on the return value of the type, not the operands.
llvm-svn: 140001
2011-09-18 14:57:03 +00:00
Nadav Rotem 7ae11279e9 When promoting integer vectors we often create ext-loads. This patch adds a
dag-combine optimization to implement the ext-load efficiently (using shuffles).

For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.

llvm-svn: 139995
2011-09-18 10:39:32 +00:00
Benjamin Kramer 98e5736295 Apply Duncan's test fix from r139986 to the avx version of that test too.
llvm-svn: 139992
2011-09-18 00:41:38 +00:00
Duncan Sands f2b8c854dd Synthesize x86 max/min instructions also for vectors (i.e. produce
maxps and maxpd).  This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it.  Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.

llvm-svn: 139986
2011-09-17 16:49:39 +00:00
Andrew Trick 31004375fc Test case trial and error. Not sure the proper way to check MBB names.
llvm-svn: 139900
2011-09-16 03:57:19 +00:00
Andrew Trick b57d9c38a2 Reduced a stronger test case for coalescer bug PR10920.
llvm-svn: 139898
2011-09-16 03:46:49 +00:00
Jakob Stoklund Olesen 53e2e48de7 VirtRegMap is counting spill slots, not register spills.
Fix the stats counters to reflect that.

llvm-svn: 139819
2011-09-15 18:31:13 +00:00
Bruno Cardoso Lopes fa1ca3070b Change all checks regarding the presence of any SSE level to always
take into consideration the presence of AVX. This change, together with
the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully)
emit the same code as SSE for 128-bit vector ops. I don't
have a testcase for this, but AVX now beats SSE in performance for
128-bit ops in the majority of programas in the llvm testsuite

llvm-svn: 139817
2011-09-15 18:27:36 +00:00
Andrew Trick 76a86d3d4c [regcoalescing] bug fix for RegistersDefinedFromSameValue.
An improper SlotIndex->VNInfo lookup was leading to unsafe copy removal.
Fixes PR10920 401.bzip2 miscompile with no IV rewrite.

llvm-svn: 139765
2011-09-15 01:09:33 +00:00
Nadav Rotem d748dbacb0 Add integer promotion support for vselect
llvm-svn: 139692
2011-09-14 14:42:15 +00:00
Bruno Cardoso Lopes 333a59eced Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "movss".
llvm-svn: 139686
2011-09-14 02:36:14 +00:00
Devang Patel 9cd29103aa Remove unnecessary old test.
llvm-svn: 139674
2011-09-14 00:28:54 +00:00
Eli Friedman f1518216fd Error out on CodeGen of unaligned load/store. Fix test so it isn't accidentally testing that case.
llvm-svn: 139641
2011-09-13 20:50:54 +00:00
Nadav Rotem 1af0c538e0 update checked pattern
llvm-svn: 139631
2011-09-13 19:59:18 +00:00
Nadav Rotem 52202fbf2d Add vselect target support for targets that do not support blend but do support
xor/and/or (For example SSE2).

llvm-svn: 139623
2011-09-13 19:17:42 +00:00
Bruno Cardoso Lopes bf6e1e2717 Change testcase commandline to be more strict and silence buildbots
llvm-svn: 139554
2011-09-12 22:59:26 +00:00
Bruno Cardoso Lopes ff8d8a830e Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
destination types are equal!

llvm-svn: 139553
2011-09-12 22:59:23 +00:00
Bruno Cardoso Lopes 973d2921e8 Revert the wrong part of r139528, and fix testcases.
llvm-svn: 139541
2011-09-12 21:24:07 +00:00
Bruno Cardoso Lopes be7a086f58 Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
However with this fix it does now.

Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.

llvm-svn: 139528
2011-09-12 19:30:40 +00:00
Eli Friedman 501f541b45 Really un-XFAIL the testcase, like I said I would in r139458.
llvm-svn: 139459
2011-09-10 02:02:27 +00:00
Richard Trieu d9917bef6c Fixed an assert from:
assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.

llvm-svn: 139454
2011-09-10 01:26:21 +00:00
Nadav Rotem de838daefd Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
llvm-svn: 139400
2011-09-09 20:29:17 +00:00
Bruno Cardoso Lopes 46b9cde019 Add a AVX version of a simple i64 -> f64 bitcast. This could be
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

llvm-svn: 139320
2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes 51920a6191 Reapply testcase from r139309!
llvm-svn: 139318
2011-09-08 21:05:43 +00:00
Bruno Cardoso Lopes f483c081b6 Remove this crashing test, until I figure out what's going wrong here
llvm-svn: 139309
2011-09-08 18:32:36 +00:00
Bruno Cardoso Lopes fb113a0051 Add AVX versions of blend vector operations and fix some issues noticed
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

llvm-svn: 139305
2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes ea8d803bb0 Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

llvm-svn: 139304
2011-09-08 18:05:02 +00:00
Nadav Rotem 354b7585de add a testcase for the previous patch
llvm-svn: 139287
2011-09-08 08:31:31 +00:00
Eli Friedman 02f2f89a98 Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
This isn't exactly ideal, but it is good enough for the moment.

llvm-svn: 139245
2011-09-07 18:48:32 +00:00
Duncan Sands 1257042b70 Another forgotten trampoline testcase.
llvm-svn: 139230
2011-09-07 10:05:14 +00:00
Devang Patel 9de7a7db26 While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor.
llvm-svn: 139208
2011-09-07 00:07:58 +00:00
Jakob Stoklund Olesen 1f72dd40c7 Pseudo CMOV instructions don't clobber EFLAGS.
The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057
2011-09-02 23:52:55 +00:00