e3e36f80f5
Unbreak CMake build.
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llvm-svn: 140655
2011-09-27 23:29:59 +00:00
f9b71a2e01
Implement TII::get/setExecutionDomain() for ARM.
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llvm-svn: 140653
2011-09-27 22:57:21 +00:00
b48c994cc0
Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.
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I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass. They are essentially doing the same
thing.
llvm-svn: 140652
2011-09-27 22:57:18 +00:00
c63af1b7b6
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
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Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
llvm-svn: 140647
2011-09-27 22:18:54 +00:00
354ff9e348
This is the start of the new SjLj EH preparation pass, which will replace the
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current IR-level pass.
The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).
Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.
llvm-svn: 140646
2011-09-27 22:14:12 +00:00
a5d18f2d7e
Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
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of the instruction definitions using Pat<>.
llvm-svn: 140644
2011-09-27 22:01:01 +00:00
7a6e8f2c5d
Remove an invalid assert that is really just asserting when the scheduler emits
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a suboptimal schedule.
llvm-svn: 140643
2011-09-27 21:59:16 +00:00
6a2eb5c1c8
test/CMakeLists.txt: Depend on llvm-objdump. "make check" is expected to resolve test-dependent targets on CMake build.
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llvm-svn: 140641
2011-09-27 21:54:50 +00:00
af136f71ec
Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().
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Naming conventions consistency. No functional change.
llvm-svn: 140636
2011-09-27 20:59:33 +00:00
547b6c5ecd
Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit.
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If someone prefers %tmp42 to %42, run instnamer.
llvm-svn: 140634
2011-09-27 20:39:19 +00:00
b762df5840
Remove incorrect passage.
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llvm-svn: 140631
2011-09-27 20:16:57 +00:00
bf415251df
These symbols appear to be visible by SearchForAddressOfSymbol and no longer
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require special case handling.
rdar://10117377
llvm-svn: 140629
2011-09-27 20:01:41 +00:00
2bc774ac1a
Add binary archive support to llvm-nm.
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llvm-svn: 140627
2011-09-27 19:37:18 +00:00
d3b7b12618
Object: Add archive support.
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llvm-svn: 140626
2011-09-27 19:36:55 +00:00
68ba81346e
Check that catch clauses have pointer type.
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llvm-svn: 140625
2011-09-27 19:34:22 +00:00
4f7054e56e
PTX: Fix case where printed alignment could be 0
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llvm-svn: 140624
2011-09-27 19:25:49 +00:00
554a012eb5
Unbreak tests.
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llvm-svn: 140622
2011-09-27 19:06:37 +00:00
d9f23c4f6b
Add FCA to the lexicon.
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llvm-svn: 140619
2011-09-27 18:44:01 +00:00
e074593498
PTX: Use external symbols to keep track of params and locals. This also fixes
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a couple of outstanding issues with frame objects occuring as instruction
operands.
llvm-svn: 140616
2011-09-27 18:12:55 +00:00
1c7597693c
Use existing function.
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llvm-svn: 140615
2011-09-27 17:55:08 +00:00
e41b1d59f0
Fix function MipsRegisterInfo::getRegisterNumbering.
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Return numbers of 64-bit registers.
llvm-svn: 140609
2011-09-27 17:15:27 +00:00
ff5d0965b0
Do not add the pass that restores $gp if target is Mips64.
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llvm-svn: 140607
2011-09-27 16:58:43 +00:00
86de1a666d
Have the verifier check that all landingpad operands are constants.
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llvm-svn: 140606
2011-09-27 16:43:19 +00:00
38b3b83362
Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC.
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Add a new method: getAnyExtOrTrunc and use it to replace the manual check.
llvm-svn: 140603
2011-09-27 11:16:47 +00:00
1b857d2762
Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8,
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while the decision is to bit-pack small values.
llvm-svn: 140601
2011-09-27 10:48:29 +00:00
614c8e5146
Remove some not-really-correct wording.
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llvm-svn: 140600
2011-09-27 10:37:28 +00:00
bb050745e7
Mark MipsPseudo isPseudo.
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llvm-svn: 140598
2011-09-27 04:57:54 +00:00
9f01f89386
PTX: Add support for sitofp in backend
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llvm-svn: 140593
2011-09-27 01:04:47 +00:00
90f90da156
Split the landing pad basic block with the correct function. Also merge the
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split landingpad instructions into a PHI node.
PR11016
llvm-svn: 140592
2011-09-27 00:59:31 +00:00
581243919d
Disable LSR retry by default.
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Disabling aggressive LSR saves compilation time, and with the new
indvars behavior usually improves performance.
llvm-svn: 140590
2011-09-27 00:44:14 +00:00
f6fbfd3f83
Last batch of test conversions to new atomic instructions.
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llvm-svn: 140585
2011-09-27 00:17:29 +00:00
8868faec63
LSR, one of the new Cost::isLoser() checks did not get merged in the previous checkin.
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llvm-svn: 140583
2011-09-26 23:35:25 +00:00
a486cb972f
Convert a bunch more tests over to the new atomic instructions.
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llvm-svn: 140582
2011-09-26 23:15:09 +00:00
b1a9f65487
Remove extraneous commit garbage.
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llvm-svn: 140581
2011-09-26 23:14:02 +00:00
784729d408
LSR cost metric minor fix and verification.
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The minor bug heuristic was noticed by inspection. I added the
isLoser/isValid helpers because they will become more
important with subsequent checkins.
llvm-svn: 140580
2011-09-26 23:11:04 +00:00
287d6ef088
Fix an incorrect decoder test.
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llvm-svn: 140579
2011-09-26 23:08:34 +00:00
02bb7573fb
Remove old hack for compiling with gcc-4.0.
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llvm-svn: 140573
2011-09-26 22:30:57 +00:00
d20cd25c69
Remove incorrect testcases.
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llvm-svn: 140572
2011-09-26 22:13:55 +00:00
a6a9c20c23
Set register class of a register according to value of HasMips64.
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llvm-svn: 140570
2011-09-26 21:55:17 +00:00
7b502920ef
Define variable HasMips64 in MipsTargetLowering.
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llvm-svn: 140569
2011-09-26 21:47:02 +00:00
e5ce709022
In single float mode, double precision FP arguments are passed in integer
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registers, so there is no need to check here.
llvm-svn: 140568
2011-09-26 21:37:50 +00:00
ab7b99ab9c
Convert more tests to new atomic instructions.
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llvm-svn: 140567
2011-09-26 21:36:10 +00:00
6fb0c1e474
Convert more tests over to the new atomic instructions.
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I did not convert Atomics-32.ll and Atomics-64.ll by hand; the diff is autoupgrade output.
The wmb test is gone because there isn't any way to express wmb with the new atomic instructions; if someone really needs a non-asm way to write a wmb on Alpha, a platform-specific intrisic could be added.
llvm-svn: 140566
2011-09-26 21:30:17 +00:00
878a67397d
Fix grammar.
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llvm-svn: 140564
2011-09-26 21:10:31 +00:00
dec0ee3237
Remove dead table entry.
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llvm-svn: 140563
2011-09-26 21:08:28 +00:00
58c80f886c
Some minor (and more involved) cleanups. No real context changes.
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llvm-svn: 140561
2011-09-26 21:06:33 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
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llvm-svn: 140560
2011-09-26 21:06:22 +00:00
c064f2c33e
Convert more tests over to the new atomic instructions.
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llvm-svn: 140559
2011-09-26 20:27:49 +00:00
bda9e7af58
Upgrade a couple more tests to the new atomic instructions.
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llvm-svn: 140558
2011-09-26 20:15:56 +00:00
5c91891cf3
Enhance alias analysis for atomic instructions a bit. Upgrade a couple alias-analysis tests to the new atomic instructions.
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llvm-svn: 140557
2011-09-26 20:15:28 +00:00
Ted Kremenek