Commit Graph

255961 Commits

Author SHA1 Message Date
Rui Ueyama 9a651672d0 Clarify benchmark conditions.
llvm-svn: 296383
2017-02-27 21:07:50 +00:00
Matt Arsenault c9f2517e96 AMDGPU: Add some of the new gfx9 VOP3 instructions
llvm-svn: 296382
2017-02-27 21:04:41 +00:00
Simon Pilgrim 5c4efcdddf [X86][SSE] Attempt to extract vector elements through target shuffles
DAGCombiner already supports peeking thorough shuffles to improve vector element extraction, but legalization often leaves us in situations where we need to extract vector elements after shuffles have already been lowered.

This patch adds support for VECTOR_EXTRACT_ELEMENT/PEXTRW/PEXTRB instructions to attempt to handle target shuffles as well. I've covered some basic scenarios including handling shuffle mask scaling and the implicit zero-extension of PEXTRW/PEXTRB, there is more that could be done here (that I've mentioned in TODOs) but I haven't found many cases where its worth it.

Differential Revision: https://reviews.llvm.org/D30176

llvm-svn: 296381
2017-02-27 21:01:57 +00:00
Matt Arsenault 7596f13d15 AMDGPU: Support inlineasm for packed instructions
Add packed types as legal so they may be used with inlineasm.
Keep all operations expanded for now.

llvm-svn: 296379
2017-02-27 20:52:10 +00:00
Rui Ueyama 1720ef1343 Add terminator to .eh_frame sections
Patch by Mark Kettenis.

Currenlty ld.lld does not add a terminator (a CIE with its length field
set to zero) to the .eh_frame sections it generates.  While the relevant
standards (the AMD64 SysV ABI and the Linux LSB) are not explicit about
this, such a terminator is expected by some unwinder implementations and
seems to be always emitted by ld.bfd. In addition to that, the Linux LSB

  https://refspecs.linuxfoundation.org/LSB_5.0.0/LSB-Core-generic/LSB-Core-generic/ehframechpt.html#EHFRAME

explicitly says that

  The .eh_frame section shall contain 1 or more Call Frame Information
  (CFI) records.

Currently, if the .eh_frame sections of the input files only contain
terminators, ld.lld emits a zero=sized .eh_frame section
which clearly doesn't meet that requirement.

The diff makes sure a terminator gets added to each .eh_frame section
and adjusts all the relevant tests to account for that.  An additional
test isn't needed as these adjustments mean that the existence of the
terminator is tested for by several tests already.

Differential Revision: https://reviews.llvm.org/D30335

llvm-svn: 296378
2017-02-27 20:44:59 +00:00
Rui Ueyama 3ead2e73ee De-template ResolvedReloc as it doesn't actually depends on ELFT.
Pointed out by Bob Haarman.

llvm-svn: 296377
2017-02-27 20:32:34 +00:00
Alexey Bataev a79c41cf51 [SLP] Use different flags in tests for reduction ops and extra args.
llvm-svn: 296376
2017-02-27 20:22:44 +00:00
Matt Arsenault 2ed2193218 AMDGPU: Don't fold immediate if clamp/omod are set
Doesn't fix any practical problems because clamp/omod
are currently folded after peephole optimizer.

llvm-svn: 296375
2017-02-27 20:21:31 +00:00
Vedant Kumar 5a97265351 [ubsan] Factor out logic to emit a range check. NFC.
This is a readability improvement, but it will also help prep an
upcoming patch to detect UB loads from bitfields.

llvm-svn: 296374
2017-02-27 19:46:19 +00:00
Bob Haarman aaf5191364 enable -flto=thin in clang-cl
Summary: This enables LTO to be used with the clang-cl frontend.

Reviewers: rnk, hans

Reviewed By: hans

Subscribers: pcc, cfe-commits, mehdi_amini, Prazek

Differential Revision: https://reviews.llvm.org/D30239

llvm-svn: 296373
2017-02-27 19:40:19 +00:00
Matt Arsenault 3cb390498e AMDGPU: Fold omod into instructions
llvm-svn: 296372
2017-02-27 19:35:42 +00:00
Taewook Oh a49eb8578a [TailDuplicator] Maintain DebugLoc for branch instructions
Summary: Existing implementation of duplicateSimpleBB function drops DebugLoc metadata of branch instructions during the transformation. This patch addresses this issue by making newly created branch instructions to keep the metadata of replaced branch instructions.

Reviewers: qcolombet, craig.topper, aprantl, MatzeB, sanjoy, dblaikie

Reviewed By: dblaikie

Subscribers: dblaikie, llvm-commits

Differential Revision: https://reviews.llvm.org/D30026

llvm-svn: 296371
2017-02-27 19:30:01 +00:00
Matt Arsenault e2d1d3a940 AMDGPU: Add f16 to shader calling conventions
Mostly useful for writing tests for f16 features.

llvm-svn: 296370
2017-02-27 19:24:47 +00:00
Alexey Bataev 0aadc6ef13 [SLP] Modify test to check IR flags propagation for extra args.
llvm-svn: 296369
2017-02-27 19:16:09 +00:00
Matt Arsenault 9be7b0d485 AMDGPU: Add VOP3P instruction format
Add a few non-VOP3P but instructions related to packed.

Includes hack with dummy operands for the benefit of the assembler

llvm-svn: 296368
2017-02-27 18:49:11 +00:00
Amaury Sechet 10c7fb4187 Refactor xaluo.ll and xmulo.ll tests. NFC
llvm-svn: 296367
2017-02-27 18:32:54 +00:00
Sanjay Patel 40975e05eb [InlineFunction] add nonnull assumptions based on argument attributes
This was suggested in D27855: have the inliner add assumptions, so we don't 
lose nonnull info provided by argument attributes.

This still doesn't solve PR28430 (dyn_cast), but this gets us closer.

https://reviews.llvm.org/D29999

llvm-svn: 296366
2017-02-27 18:13:48 +00:00
Krzysztof Parzyszek e9be35596e [Hexagon] Defs and clobbers can overlap
llvm-svn: 296365
2017-02-27 18:03:35 +00:00
Xin Tong 16b85a6601 Fix a bug when unswitching on partial LIV for SwitchInst
Summary: Fix a bug when unswitching on partial LIV for SwitchInst.

Reviewers: hfinkel, efriedma, sanjoy

Reviewed By: sanjoy

Subscribers: david2050, mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D29107

llvm-svn: 296363
2017-02-27 18:00:13 +00:00
Rong Xu 08d0840273 Fix comments. NFC.
Change "Thin-LTO" to "ThinLTO" in the comments for consistency.

llvm-svn: 296362
2017-02-27 17:59:01 +00:00
Michael Kruse 6469380daa [Cmake] Optionally use a system isl version.
This patch adds an option to build against a version of libisl already
installed on the system. The installation is autodetected using the
pkg-config file shipped with isl.

The detection of the library is in the FindISL.cmake module that creates
an imported target.

Contributed-by: Philip Pfaffe <philip.pfaffe@gmail.com>

Differential Revision: https://reviews.llvm.org/D30043

llvm-svn: 296361
2017-02-27 17:54:25 +00:00
Kamil Rytarowski 47e7d7fe85 Support NetBSD Thread ID in lldb-server tests
Summary:
Native Thread ID is retrieved with _lwp_self() on NetBSD.

The returned value is of type int32_t, but for consistency with other Operating Systems cast it to uint64_t.

Sponsored by <The NetBSD Foundation>

Reviewers: joerg, labath, clayborg, emaste

Reviewed By: labath, clayborg

Subscribers: #lldb

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D30374

llvm-svn: 296360
2017-02-27 17:52:48 +00:00
Arnaud A. de Grandmaison 5309887746 Fix the project name in the license file.
llvm-svn: 296359
2017-02-27 17:47:58 +00:00
Arnaud A. de Grandmaison 5978330c3a Add libcxxabi's LICENSE.TXT to libunwind.
When libunwind was spinned off libcxxabi, most file were copied from
libcxxabi to libunwind.  However, libc++abi's toplevel LICENSE.TXT was
forgotten in the copying. It's considered a good practice to have the
license file at the root of the project, and making linunwind a separate
project was not supposed to change its licensing. Besides, several
header files refer to the LICENSE.TXT, so copy the one from libc++abi.

llvm-svn: 296358
2017-02-27 17:33:20 +00:00
Steven Wu 0255799b8a Fix LLVM module build
Add WasmRelocs/WebAssembly.def to textual include header.

llvm-svn: 296356
2017-02-27 16:56:37 +00:00
Craig Topper 7502119ce8 [X86] Use APInt instead of SmallBitVector tracking undef elements from getTargetConstantBitsFromNode and getConstVector.
Summary:
SmallBitVector uses a malloc for more than 58 bits on a 64-bit target and more than 27 bits on a 32-bit target. Some of the vector types we deal with here use more than those number of elements and therefore cause a malloc.

APInt on the other hand supports up to 64 bits without a malloc. That's the maximum number of bits we need here so we can avoid a malloc for all cases by using APInt.

Reviewers: RKSimon

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30392

llvm-svn: 296355
2017-02-27 16:15:32 +00:00
Craig Topper 3917ca2af4 [X86] Use APInt instead of SmallBitVector for tracking Zeroable elements in shuffle lowering
Summary:
SmallBitVector uses a malloc for more than 58 bits on a 64-bit target and more than 27 bits on a 32-bit target. Some of the vector types we deal with here use more than those number of elements and therefore cause a malloc.

APInt on the other hand supports up to 64 bits without a malloc. That's the maximum number of bits we need here so we can avoid a malloc for all cases by using APInt.

Reviewers: RKSimon

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30390

llvm-svn: 296354
2017-02-27 16:15:30 +00:00
Craig Topper e1be95c3d0 [X86] Fix SmallVector sizes in constant pool shuffle decoding to avoid heap allocation
Some of the vectors are under sized to avoid heap allocation. In one case the vector was oversized.

Differential Revision: https://reviews.llvm.org/D30387

llvm-svn: 296353
2017-02-27 16:15:27 +00:00
Craig Topper 53e5a38da9 [X86] Use APInt instead of SmallBitVector for tracking undef elements in constant pool shuffle decoding
Summary:
SmallBitVector uses a malloc for more than 58 bits on a 64-bit target and more than 27 bits on a 32-bit target. Some of the vector types we deal with here use more than those number of elements and therefore cause a malloc.

APInt on the other hand supports up to 64 bits without a malloc. That's the maximum number of bits we need here so we can avoid a malloc for all cases by using APInt. This will incur a minor increase in stack usage due to APInt storing the bit count separately from the data bits unlike SmallBitVector, but that should be ok.

Reviewers: RKSimon

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30386

llvm-svn: 296352
2017-02-27 16:15:25 +00:00
Asiri Rathnayake 68050fd694 Fix LIBCXX_HAS_EXTERNAL_THREAD_API builds. NFC.
Add the missing check in the __config header.

llvm-svn: 296351
2017-02-27 16:10:57 +00:00
Amaury Sechet 00bf6f52dc Remove an empty line in icmp-illegal.ll . NFC
llvm-svn: 296350
2017-02-27 16:09:44 +00:00
Alexey Bataev cb78d09d14 [SLP] A test for a fix of PR32038.
llvm-svn: 296349
2017-02-27 16:07:10 +00:00
Michael Kruse c4f61d2346 [DeLICM] Add nomap regressions tests. NFC.
These verify that some scalars are not mapped because it would be
incorrect to do so.

For these check we verify that no transformation has been executed from
output of the pass's '-analyze'. Adding optimization remarks is not useful
as it would result in too many messages, even repeated ones. I avoided
checking the '-debug-only=polly-delicm' output which is an antipattern.

llvm-svn: 296348
2017-02-27 15:53:18 +00:00
Michael Kruse b295c37a15 [DeLICM] Statistics for use in regression tests.
Print some measurements of the DeLICM transformation at -analyze to be
used in regression tests.

llvm-svn: 296347
2017-02-27 15:53:13 +00:00
Asiri Rathnayake 01eb47800b Fix typo in error message. NFC.
llvm-svn: 296346
2017-02-27 15:49:51 +00:00
Artur Pilipenko 0860bfc676 Loop predication expand both sides of the widened condition
This is a fix for a loop predication bug which resulted in malformed IR generation.

Loop invariant side of the widened condition is not guaranteed to be available in the preheader as is, so we need to expand it as well. See added unsigned_loop_0_to_n_hoist_length test for example.

Reviewed By: sanjoy, mkazantsev

Differential Revision: https://reviews.llvm.org/D30099

llvm-svn: 296345
2017-02-27 15:44:49 +00:00
Asiri Rathnayake 0b59cf64a0 Attempt to fix arm-native libcxxabi tests for the no-exceptions variant
These tests embed calls to exceptions-related symbols from the abi library,
which are absent in the no-exceptions variant. The tests need to be marked
as unsupported for the no-exceptions configuration.

llvm-svn: 296344
2017-02-27 15:31:34 +00:00
Sjoerd Meijer 32ecac7ac8 AArch64InstPrinter: rewrite of printSysAlias
This is a cleanup/rewrite of the printSysAlias function. This was not using the
tablegen instruction descriptions, but was "manually" decoding the
instructions. This has been replaced with calls to lookup_XYZ_ByEncoding
tablegen calls.

This revealed several problems. First, instruction IVAU had the wrong encoding.
This was cancelled out by the parser that incorrectly matched the wrong
encoding. Second, instruction CVAP was missing from the SystemOperands tablegen
descriptions, so this has been added. And third, the required target features
were not captured in the tablegen descriptions, so support for this has also
been added.

Differential Revision: https://reviews.llvm.org/D30329

llvm-svn: 296343
2017-02-27 14:45:34 +00:00
John Brawn c97b714ffb [ARM] LSL is an alias of MOV
Currently we handle this correctly in arm, but in thumb we don't which leads to
an unpredictable instruction being emitted for LSL  in an IT block and SP not
being permitted in some cases when it should be.

For the thumb2 LSL we can handle this by making LSL  an alias of MOV in the
.td file, but for thumb1 we need to handle it in checkTargetMatchPredicate to
get the IT handling right. We also need to adjust the handling of
MOV rd, rn, LSL  to avoid generating the 16-bit encoding in an IT block. We
should also adjust it to allow SP in the same way that it is allowed in
MOV rd, rn, but I haven't done that here because it looks like it would take
quite a lot of work to get right.

Additionally correct the selection of the 16-bit shift instructions in
processInstruction, where it was checking if the two registers were equal when
it should have been checking if they were low. It appears that previously this
code was never executed and the 16-bit encoding was selected by default, but
the other changes I've done here have somehow made it start being used.

Differential Revision: https://reviews.llvm.org/D30294

llvm-svn: 296342
2017-02-27 14:40:51 +00:00
Krasimir Georgiev 7cb267af75 [clang-format] Add a NamespaceEndCommentsFixer
Summary:
This patch adds a NamespaceEndCommentsFixer TokenAnalyzer for clang-format,
which fixes end namespace comments.
It currently supports inserting and updating existing wrong comments.

Example source:
```
namespace A {
int i;
}

namespace B {
int j;
} // namespace A
```

after formatting:
```
namespace A {
int i;
} // namespace A

namespace B {
int j;
} // namespace B
```

Reviewers: klimek, djasper

Reviewed By: djasper

Subscribers: klimek, mgorny

Differential Revision: https://reviews.llvm.org/D30269

llvm-svn: 296341
2017-02-27 13:28:36 +00:00
Rafael Espindola cf8396e4aa Add a test we already get right.
It would have found a problem in a patch I am writing.

llvm-svn: 296339
2017-02-27 13:21:18 +00:00
Asiri Rathnayake 749c557d81 Fix cmake dependency for the external-thread-library variant. NFC.
llvm-svn: 296338
2017-02-27 13:19:25 +00:00
Haojian Wu 4a92050ce2 [clang-move] Extend clang-move to support moving global variable.
Summary: Also support dumping global variables.

Reviewers: ioeric

Reviewed By: ioeric

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D30337

llvm-svn: 296337
2017-02-27 13:19:13 +00:00
Artur Pilipenko f7196c8d9e [DAGCombine] Fix for a load combine bug with non-zero offset patterns on BE targets
This pattern is essentially a i16 load from p+1 address:

  %p1.i16 = bitcast i8* %p to i16*
  %p2.i8 = getelementptr i8, i8* %p, i64 2
  %v1 = load i16, i16* %p1.i16
  %v2.i8 = load i8, i8* %p2.i8
  %v2 = zext i8 %v2.i8 to i16
  %v1.shl = shl i16 %v1, 8
  %res = or i16 %v1.shl, %v2

Current implementation would identify %v1 load as the first byte load and would mistakenly emit a i16 load from %p1.i16 address. This patch adds a check that the first byte is loaded from a non-zero offset of the first load address. This way this address can be used as the base address for the combined value. Otherwise just give up combining.

llvm-svn: 296336
2017-02-27 13:04:23 +00:00
Pavel Labath 4b2b6bfb97 Merge Linux and FreeBSD arm register contexts
Summary:
These two register contexts were identical, so this shouldn't cause any
regressions, but I'd appreciate it if you can check that this at least compiles.

Reviewers: emaste, sas

Subscribers: aemerson, rengolin, lldb-commits, mgorny

Differential Revision: https://reviews.llvm.org/D27126

llvm-svn: 296335
2017-02-27 13:00:50 +00:00
Pavel Labath c9fbd9a3be Fix MinidumpParserTest on 32-bit arches
load_size should be 64-bit unconditionally to match the underlying API.
This makes sure the MAX value correctly signals to auto-detect the file
size when mmap()ing.

llvm-svn: 296334
2017-02-27 12:21:20 +00:00
Pavel Labath 3474ebc4c5 Remove the callback-based log channel registration mechanism
All the existing channels have beens switched to the new mechanism and
this code is now unused.

llvm-svn: 296333
2017-02-27 12:21:16 +00:00
Artur Pilipenko c43b20a43b [DAGCombine] NFC. MatchLoadCombine extract MemoryByteOffset lambda helper
This refactoring will simplify the upcoming change to fix the bug in folding patterns with non-zero offsets on BE targets.

llvm-svn: 296332
2017-02-27 11:42:54 +00:00
Artur Pilipenko f2c26e0bf2 [DAGCombine] NFC. MatchLoadCombine remember the first byte provider, not the load node
This refactoring will simplify the upcoming change to fix a bug in folding patterns with non-zero offsets on BE targets.

llvm-svn: 296331
2017-02-27 11:40:14 +00:00
Martin Probst 20371c30ef clang-format: [JS] whitespace after async in arrow functions.
Summary:
Async arrow functions should be marked with a whitespace after the async keyword, before the parameter list:
    x = async () => foo();

Before:
    x = async() => foo();

This makes it easier to tell apart an async arrow function from a call to a function called async.

Reviewers: bkramer

Subscribers: cfe-commits, klimek

Differential Revision: https://reviews.llvm.org/D30399

llvm-svn: 296330
2017-02-27 11:15:53 +00:00