Commit Graph

7258 Commits

Author SHA1 Message Date
Evan Cheng 9a3b2b09ad Mac OS X X86-64 low 4G address not available.
llvm-svn: 40702
2007-08-01 23:46:10 +00:00
Evan Cheng 763cdfd371 Mac OS X X86-64 low 4G address not available.
llvm-svn: 40701
2007-08-01 23:45:51 +00:00
Evan Cheng 58c3c30921 Some out operands were incorrectly specified as input operands.
llvm-svn: 40697
2007-08-01 23:07:38 +00:00
Evan Cheng da549ece5c Missing Requires.
llvm-svn: 40691
2007-08-01 21:42:24 +00:00
Evan Cheng 6f2ce6b842 Be more precise.
llvm-svn: 40689
2007-08-01 20:22:37 +00:00
Dan Gohman d541c831c3 Change a .size directive to use a tab instead of a space, for consistency.
llvm-svn: 40672
2007-08-01 14:42:30 +00:00
Evan Cheng aa39b39eec Indexed loads each has 2 outputs.
llvm-svn: 40658
2007-08-01 00:12:08 +00:00
Dan Gohman 54ec4bfa5f Change the x86 assembly output to use tab characters to separate the
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.

llvm-svn: 40648
2007-07-31 20:11:57 +00:00
Evan Cheng 12c6be84ff Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )
llvm-svn: 40628
2007-07-31 08:04:03 +00:00
Evan Cheng 242a87734a This isn't safe when there are uses of load's chain result.
llvm-svn: 40617
2007-07-31 06:21:44 +00:00
Dan Gohman 204dece054 Use tabs more consistently in assembler pseudo-ops.
llvm-svn: 40594
2007-07-30 15:08:02 +00:00
Dan Gohman 55360dacd4 Fix the comment for getClosestTargetForJIT to reflect the fact that
it does not have a Module parameter.

llvm-svn: 40590
2007-07-30 14:58:59 +00:00
Dan Gohman e379f08b19 More explicit keywords.
llvm-svn: 40589
2007-07-30 14:51:59 +00:00
Evan Cheng 581d2795dc Vector fneg must be expanded into fsub -0.0, X.
llvm-svn: 40586
2007-07-30 07:51:22 +00:00
Christopher Lamb 5fecb80efa Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource.
llvm-svn: 40578
2007-07-29 01:24:57 +00:00
Christopher Lamb ac3a364c51 Add register info needed to use subreg sets on X86.
llvm-svn: 40572
2007-07-28 19:03:30 +00:00
Duncan Sands ce38853cc6 Trampoline codegen support for X86-32.
llvm-svn: 40566
2007-07-27 20:02:49 +00:00
Dan Gohman 4788552deb Re-apply 40504, but with a fix for the segfault it caused in oggenc:
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.

llvm-svn: 40555
2007-07-27 17:16:43 +00:00
Duncan Sands 644f917358 Support for trampolines, except for X86 codegen which is
still under discussion.

llvm-svn: 40549
2007-07-27 12:58:54 +00:00
Evan Cheng 931de40afa Reverting 40504 for now. It's breaking oggenc.
llvm-svn: 40547
2007-07-27 01:37:47 +00:00
Evan Cheng d204d08b97 Make sure epilogue esp adjustment is placed before any terminator and pop instructions.
llvm-svn: 40538
2007-07-26 17:45:41 +00:00
Evan Cheng 936d17aa1b Don't pollute the meaning of isUnpredicatedTerminator.
llvm-svn: 40537
2007-07-26 17:32:14 +00:00
Evan Cheng ca6e041903 Minor bug.
llvm-svn: 40535
2007-07-26 17:02:45 +00:00
Dan Gohman c9edd977ea In the .loc directive, print the fields as "debug" fields, so they
don't get decorated as if for immediate fields for instructions.

llvm-svn: 40529
2007-07-26 15:24:15 +00:00
Dan Gohman cecd4b3793 Fix a whitespace difference between CMPSSrr and CMPSDrr.
llvm-svn: 40528
2007-07-26 15:11:50 +00:00
Christopher Lamb cde0ee5221 Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
llvm-svn: 40518
2007-07-26 07:48:21 +00:00
Evan Cheng ce5185b181 Same goes for constantpool, etc.
llvm-svn: 40517
2007-07-26 07:35:15 +00:00
Christopher Lamb a8fc0e527b Add selection DAG nodes for subreg insert/extract. PR1350
llvm-svn: 40516
2007-07-26 07:34:40 +00:00
Dan Gohman 8455bd3fae Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the
x86 target, replacing them with the new alignment attributes on memory
references.

llvm-svn: 40504
2007-07-26 00:31:09 +00:00
Evan Cheng 630c1f75b8 Mac OS X x86-64 lower 4G address is not available.
llvm-svn: 40502
2007-07-25 23:41:36 +00:00
Evan Cheng 952aa6988b Mac OS X should use 0x90 to fill in gaps to satisfy function alignment requirements.
llvm-svn: 40501
2007-07-25 23:36:05 +00:00
Evan Cheng 5c6a31e9a0 Functions with LinkOnce and weak linkage still need to be aligned. Doh.
llvm-svn: 40499
2007-07-25 22:28:16 +00:00
Dan Gohman cf0a5349de Don't ignore the return value of AsmPrinter::doInitialization and
AsmPrinter::doFinalization.

llvm-svn: 40487
2007-07-25 19:33:14 +00:00
Nick Lewycky 5805c46e8f Fix debug info and globals filled with zeros.
llvm-svn: 40483
2007-07-25 03:48:45 +00:00
Anton Korobeynikov 64b64ae591 Minor cleanup:
- Split EH and debug infiormation
 - Make DwarfWriter more verbose in some cases

llvm-svn: 40481
2007-07-25 00:06:28 +00:00
Dan Gohman f0bb12848f Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask.
llvm-svn: 40480
2007-07-24 23:00:27 +00:00
Dan Gohman f906c7286f Use movaps to load a v4f32 build_vector of all-constant values into a
register instead of loading each element individually.

llvm-svn: 40478
2007-07-24 22:55:08 +00:00
Anton Korobeynikov 0c46451d2b Heal EH handling stuff by emitting correct offsets to callee-saved registers.
Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :)

llvm-svn: 40472
2007-07-24 21:07:39 +00:00
Dan Gohman b6a8ae20c7 Fix some uses of dyn_cast to be uses of cast.
llvm-svn: 40443
2007-07-23 20:24:29 +00:00
Dan Gohman 17f68f95d8 Delete the svn:executable property on these files, which aren't executable.
llvm-svn: 40441
2007-07-23 19:26:08 +00:00
Bill Wendling 3d88e9940a Add missing SSE builtins:
__builtin_ia32_cvtss2si64
    __builtin_ia32_cvttss2si64
    __builtin_ia32_cvtsi642ss
    __builtin_ia32_cvtsd2si64
    __builtin_ia32_cvttsd2si64
    __builtin_ia32_cvtsi642sd

llvm-svn: 40411
2007-07-23 03:07:27 +00:00
Evan Cheng ac1591be42 No more noResults.
llvm-svn: 40132
2007-07-21 00:34:19 +00:00
Evan Cheng 9d5df0a5f6 Added -print-emitted-asm to print out JIT generated asm to cerr.
llvm-svn: 40123
2007-07-20 21:56:13 +00:00
Evan Cheng 8fefeffb37 Because we promote SSE logical ops and loads to v2i64, we often end up generate
code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.

llvm-svn: 40076
2007-07-20 00:27:43 +00:00
Evan Cheng 9081ab8127 Oops. These stores actually produce results.
llvm-svn: 40074
2007-07-20 00:20:46 +00:00
Evan Cheng 64738536b3 Fix custom lowering of SSE FXOR.
llvm-svn: 40071
2007-07-19 23:36:01 +00:00
Evan Cheng 7ca3555bfa Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)).
llvm-svn: 40070
2007-07-19 23:34:10 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Evan Cheng 22b0c344db Only adjust esp around calls in presence of alloca.
llvm-svn: 40030
2007-07-19 00:42:58 +00:00
Evan Cheng 7b5b06805a Only adjust esp around calls in presence of alloca.
llvm-svn: 40028
2007-07-19 00:42:05 +00:00