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24046 Commits

Author SHA1 Message Date
Rafael Espindola b770f897ee Fix section relocation for SECTIONREL32 with immediate offset. 
Patch by Kai Nacke. This matches the gnu as output.

llvm-svn: 180568
 2013-04-25 19:27:05 +00:00
Akira Hatanaka f0aa6c9101 [mips] Add definitions of micromips load and store instructions. 
Patch by Zoran Jovanovic.

llvm-svn: 180241
 2013-04-25 01:21:25 +00:00
Akira Hatanaka cd9b74a599 [mips] Add definitions of micromips shift instructions. 
Patch by Zoran Jovanovic.

llvm-svn: 180238
 2013-04-25 01:11:15 +00:00
Tom Stellard 87047f69ad R600: Initialize BooleanVectorContents 
Fixes test/CodeGen/R600/setcc.ll

llvm-svn: 180231
 2013-04-24 23:56:18 +00:00
Tom Stellard 34e4068d05 R600: Use SHT_PROGBITS for the .AMDGPU.config section 
The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

llvm-svn: 180230
 2013-04-24 23:56:14 +00:00
Jyotsna Verma af2359b98c Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. 
llvm-svn: 180145
 2013-04-23 21:17:40 +00:00
Jyotsna Verma f00aab98a0 Hexagon: Define relations for GP-relative instructions. 
No functionality change.

llvm-svn: 180144
 2013-04-23 21:05:55 +00:00
Stephen Lin 8118e0b588 Add more tests for r179925 to verify correct handling of signext/zeroext; strengthen condition check to require actual MVT::i32 virtual register types, just in case (no actual functionality change) 
llvm-svn: 180138
 2013-04-23 19:42:25 +00:00
Stephen Lin 4eedb29b05 Lowercase "is" boolean variable prefix for consistency within function, no functionality change. 
llvm-svn: 180136
 2013-04-23 19:30:12 +00:00
Jyotsna Verma 89c84821ea Hexagon: Remove assembler mapped instruction definitions. 
llvm-svn: 180133
 2013-04-23 19:15:55 +00:00
Bill Schmidt a76bf5a6d0 Change commentary for PowerPC Boolean vector contents. 
No functional change intended.

llvm-svn: 180131
 2013-04-23 18:49:44 +00:00
Akira Hatanaka e9d0b318b1 [mips] Compare splat value with element size instead of calling isUIntN. 
No intended changes in functionality.

llvm-svn: 180130
 2013-04-23 18:09:42 +00:00
Owen Anderson 2d4cca35c3 DAGCombine should not aggressively fold SEXT(VSETCC(...)) into a wider VSETCC without first checking the target's vector boolean contents. 
This exposed an issue with PowerPC AltiVec where it appears it was setting the wrong vector boolean contents.  The included change
fixes the PowerPC tests, and was OK'd by Hal.

llvm-svn: 180129
 2013-04-23 18:09:28 +00:00
Vincent Lejeune 117f075f6e R600: Use .AMDGPU.config section to emit stacksize 
llvm-svn: 180124
 2013-04-23 17:34:12 +00:00
Vincent Lejeune b6bfe85a07 R600: Add CF_END 
llvm-svn: 180123
 2013-04-23 17:34:00 +00:00
Jyotsna Verma a696239bec Hexagon: Remove duplicate instructions to handle global/immediate values 
for absolute/absolute-set addressing modes.

llvm-svn: 180120
 2013-04-23 17:11:46 +00:00
Tim Northover 2ac2d4c59d AArch64: remove unnecessary check that RS is valid 
AArch64 always demands a register-scavenger, so the pointer should never be
NULL. However, in the spirit of paranoia, we'll assert it before use just in
case.

llvm-svn: 180080
 2013-04-23 06:55:15 +00:00
Matt Arsenault 034ca0fe41 Remove unused DwarfSectionOffsetDirective string 
The value isn't actually used, and setting it emits a COFF specific
directive.

llvm-svn: 180064
 2013-04-22 22:49:11 +00:00
Eric Christopher 04d4e9312c Move C++ code out of the C headers and into either C++ headers 
or the C++ files themselves. This enables people to use
just a C compiler to interoperate with LLVM.

llvm-svn: 180063
 2013-04-22 22:47:22 +00:00
Chad Rosier 65dd0399c6 [ms-inline asm] Removed this unnecessary check. In the current implementation, 
Disp will always be one of MCSymbolRefExpr or MCConstantExpr, and never NULL.

llvm-svn: 180059
 2013-04-22 22:38:35 +00:00
Chad Rosier 732b837a41 [ms-inline asm] Add the OpDecl to the InlineAsmIdentifierInfo struct and in turn 
the MCParsedAsmOperand.
Part of rdar://13663589

llvm-svn: 180054
 2013-04-22 22:04:25 +00:00
Chad Rosier eeb0034918 Fix unused variable warning. 
llvm-svn: 180044
 2013-04-22 20:42:32 +00:00
Akira Hatanaka d8fb032cff 80 columns. 
llvm-svn: 180040
 2013-04-22 20:13:37 +00:00
Akira Hatanaka 0d6964cf4a [mips] In performDSPShiftCombine, check that all elements in the vector are 
shifted by the same amount and the shift amount is smaller than the element
size.

llvm-svn: 180039
 2013-04-22 19:58:23 +00:00
Chad Rosier cb78f0d05e [ms-inline asm] Remove the identifier parsing logic from the AsmParser. This is 
now taken care of by the frontend, which allows us to parse arbitrary C/C++
variables.
Part of rdar://13663589

llvm-svn: 180037
 2013-04-22 19:42:15 +00:00
Chad Rosier f6675c3d3e [ms-inline asm] Refactor/clean up the SemaLookup interface. No functional 
change indended.
Part of rdar://13663589

llvm-svn: 180028
 2013-04-22 17:01:46 +00:00
Eric Christopher cc2cfe426d No really, don't store anything to this since it's unconditionally 
set below.

llvm-svn: 180015
 2013-04-22 14:11:25 +00:00
Eric Christopher 6647fb2c60 Remove variable store that is never read. 
llvm-svn: 180014
 2013-04-22 13:51:44 +00:00
Stepan Dyatkovskiy f80f9513ce Fix for 5.5 Parameter Passing --> Stage C: 
-- C.4 and C.5 statements, when NSAA is not equal to SP.
 -- C.1.cp statement for VA functions. Note: There are no VFP CPRCs in a
    variadic procedure.

Before this patch "NSAA != 0" means "don't use GPRs anymore ". But there are
some exceptions in AAPCS.
1. For non VA function: allocate all VFP regs for CPRC. When all VFPs are allocated
   CPRCs would be sent to stack, while non CPRCs may be still allocated in GRPs.
2. Check that for VA functions all params uses GPRs and then stack.
   No exceptions, no CPRCs here.

llvm-svn: 180011
 2013-04-22 13:06:52 +00:00
Jim Grosbach 563983c8a3 Legalize vector truncates by parts rather than just splitting. 
Rather than just splitting the input type and hoping for the best, apply
a bit more cleverness. Just splitting the types until the source is
legal often leads to an illegal result time, which is then widened and a
scalarization step is introduced which leads to truly horrible code
generation. With the loop vectorizer, these sorts of operations are much
more common, and so it's worth extra effort to do them well.

Add a legalization hook for the operands of a TRUNCATE node, which will
be encountered after the result type has been legalized, but if the
operand type is still illegal. If simple splitting of both types
ends up with the result type of each half still being legal, just
do that (v16i16 -> v16i8 on ARM, for example). If, however, that would
result in an illegal result type (v8i32 -> v8i8 on ARM, for example),
we can get more clever with power-two vectors. Specifically,
split the input type, but also widen the result element size, then
concatenate the halves and truncate again.  For example on ARM,
To perform a "%res = v8i8 trunc v8i32 %in" we transform to:
  %inlo = v4i32 extract_subvector %in, 0
  %inhi = v4i32 extract_subvector %in, 4
  %lo16 = v4i16 trunc v4i32 %inlo
  %hi16 = v4i16 trunc v4i32 %inhi
  %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
  %res = v8i8 trunc v8i16 %in16

This allows instruction selection to generate three VMOVN instructions
instead of a sequences of moves, stores and loads.

Update the ARMTargetTransformInfo to take this improved legalization
into account.

Consider the simplified IR:

define <16 x i8> @test1(<16 x i32>* %ap) {
  %a = load <16 x i32>* %ap
  %tmp = trunc <16 x i32> %a to <16 x i8>
  ret <16 x i8> %tmp
}

define <8 x i8> @test2(<8 x i32>* %ap) {
  %a = load <8 x i32>* %ap
  %tmp = trunc <8 x i32> %a to <8 x i8>
  ret <8 x i8> %tmp
}

Previously, we would generate the truly hideous:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #20
	bic	sp, sp, #7
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d24, d25}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	vld1.64	{d18, d19}, [r2:128]
	add	r1, r0, #16
	vmovn.i32	d22, q8
	vld1.64	{d16, d17}, [r1:128]
	vmovn.i32	d20, q9
	vmovn.i32	d18, q12
	vmov.u16	r0, d22[3]
	strb	r0, [sp, #15]
	vmov.u16	r0, d22[2]
	strb	r0, [sp, #14]
	vmov.u16	r0, d22[1]
	strb	r0, [sp, #13]
	vmov.u16	r0, d22[0]
	vmovn.i32	d16, q8
	strb	r0, [sp, #12]
	vmov.u16	r0, d20[3]
	strb	r0, [sp, #11]
	vmov.u16	r0, d20[2]
	strb	r0, [sp, #10]
	vmov.u16	r0, d20[1]
	strb	r0, [sp, #9]
	vmov.u16	r0, d20[0]
	strb	r0, [sp, #8]
	vmov.u16	r0, d18[3]
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	vldmia	sp, {d16, d17}
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	mov	sp, r7
	pop	{r7}
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #12
	bic	sp, sp, #7
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d20, d21}, [r0:128]
	vmovn.i32	d18, q8
	vmov.u16	r0, d18[3]
	vmovn.i32	d16, q10
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	ldm	sp, {r0, r1}
	mov	sp, r7
	pop	{r7}
	bx	lr

Now, however, we generate the much more straightforward:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d20, d21}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	add	r1, r0, #16
	vld1.64	{d18, d19}, [r2:128]
	vld1.64	{d22, d23}, [r1:128]
	vmovn.i32	d17, q8
	vmovn.i32	d16, q9
	vmovn.i32	d18, q10
	vmovn.i32	d19, q11
	vmovn.i16	d17, q8
	vmovn.i16	d16, q9
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d18, d19}, [r0:128]
	vmovn.i32	d16, q8
	vmovn.i32	d17, q9
	vmovn.i16	d16, q8
	vmov	r0, r1, d16
	bx	lr

llvm-svn: 179989
 2013-04-21 23:47:41 +00:00
Jakob Stoklund Olesen 84ebe25db7 Passing arguments to varags functions under the SPARC v9 ABI. 
Arguments after the fixed arguments never use the floating point
registers.

llvm-svn: 179987
 2013-04-21 21:36:49 +00:00
Jakob Stoklund Olesen 65d3287282 Fix the SETHIimm pattern for 64-bit code. 
Don't ignore the high 32 bits of the immediate.

llvm-svn: 179985
 2013-04-21 21:18:03 +00:00
Tim Northover 798697d662 ARM: Use ldrd/strd to spill 64-bit pairs when available. 
This allows common sp-offsets to be part of the instruction and is
probably faster on modern CPUs too.

llvm-svn: 179977
 2013-04-21 11:57:07 +00:00
Jakob Stoklund Olesen a41f91ea8e Compile varargs functions for SPARCv9. 
With a little help from the frontend, it looks like the standard va_*
intrinsics can do the job.

Also clean up an old bitcast hack in LowerVAARG that dealt with
unaligned double loads. Load SDNodes can specify an alignment now.

Still missing: Calling varargs functions with float arguments.

llvm-svn: 179961
 2013-04-20 22:49:16 +00:00
Tim Northover d9d4211fe2 ARM: don't add FrameIndex offset for LDMIA (has no immediate) 
Previously, when spilling 64-bit paired registers, an LDMIA with both
a FrameIndex and an offset was produced. This kind of instruction
shouldn't exist, and the extra operand was being confused with the
predicate, causing aborts later on.

This removes the invalid 0-offset from the instruction being
produced.

llvm-svn: 179956
 2013-04-20 19:31:00 +00:00
Tim Northover 56862bd6b2 AArch64: remove useless comment 
llvm-svn: 179952
 2013-04-20 15:57:41 +00:00
Tim Northover 16aba17024 Remove unused ShouldFoldAtomicFences flag. 
I think it's almost impossible to fold atomic fences profitably under
LLVM/C++11 semantics. As a result, this is now unused and just
cluttering up the target interface.

llvm-svn: 179940
 2013-04-20 12:32:43 +00:00
Tim Northover a2b533906a Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE. 
llvm-svn: 179939
 2013-04-20 12:32:17 +00:00
Hal Finkel 0f64e21bb9 Move PPC getSwappedPredicate for reuse 
The getSwappedPredicate function can be used in other places (such as in
improvements to the PPCCTRLoops pass). Instead of trapping it as a static
function in PPCInstrInfo, move it into PPCPredicates with other
predicate-related things.

No functionality change intended.

llvm-svn: 179926
 2013-04-20 05:16:26 +00:00
Stephen Lin b8bd232a3d Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter). 
llvm-svn: 179925
 2013-04-20 05:14:40 +00:00
Stephen Lin d36fd2cfe2 Test commit 
llvm-svn: 179913
 2013-04-20 00:47:48 +00:00
Akira Hatanaka 1ebb2a1c56 [mips] Instruction selection patterns for DSP-ASE vector shifts. 
llvm-svn: 179906
 2013-04-19 23:21:32 +00:00
Eli Bendersky 90dd3e7dfd Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'm 
trying to move as much FastISel logic as possible out of the main path in
SelectionDAGISel - intermixing them just adds confusion.

llvm-svn: 179902
 2013-04-19 22:29:18 +00:00
Michael Liao b53d8963ce ArrayRefize getMachineNode(). No functionality change. 
llvm-svn: 179901
 2013-04-19 22:22:57 +00:00
Hal Finkel e632239d7b Fix PPC optimizeCompareInstr swapped-sub argument handling 
When matching a compare with a subtract where the arguments of the compare are
swapped w.r.t. the arguments of the subtract, we need to negate the predicates
(or CR bit indices) of the users. This, however, is not the same as inverting
the predicate (negating LT -> GT, but inverting LT -> GE, for example). The ARM
backend seems to do this correctly, but when I adapted the code for the PPC
backend, I introduced an error in this logic.

Comparison optimization is now enabled again by default.

llvm-svn: 179899
 2013-04-19 22:08:38 +00:00
Anton Korobeynikov 9c0df1695d Do not mangle in MS-way the globals with magic \001 in the name. 
Based on the patch by David Nadlinger!

llvm-svn: 179889
 2013-04-19 21:20:56 +00:00
Chad Rosier e8f9bfdb71 [ms-inline asm] Make code layout more canonical with iniline asm handled last. 
llvm-svn: 179875
 2013-04-19 19:29:50 +00:00
Akira Hatanaka be6a818fd4 [mips] First patch which adds support for micromips. 
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.

Patch by Zoran Jovanovic.

llvm-svn: 179873
 2013-04-19 19:03:11 +00:00
Akira Hatanaka c68fd9f4f1 [mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and change 
operand type to uimm16.

Patch by Vladimir Medic.

llvm-svn: 179872
 2013-04-19 18:47:40 +00:00
Chad Rosier 95ce889691 [ms-inline asm] Refactor the parsing of identifiers. No functional change 
indended.
Part of rdar://13663589

llvm-svn: 179871
 2013-04-19 18:39:50 +00:00