772cf466da
Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.
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They should always be zero-extended, not sign extended. Added test case.
llvm-svn: 178275
2013-03-28 19:22:28 +00:00
f686be4674
Patch by Gordon Keiser!
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If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.
This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a
postindexed load, where the offset 0xc is applied to SP after the load occurs.
llvm-svn: 178017
2013-03-26 13:58:53 +00:00
e3d323052f
Remove edis - the enhanced disassembler. Fixes PR14654.
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llvm-svn: 170578
2012-12-19 19:55:47 +00:00
ed0881b2a6
Use the new script to sort the includes of every file under lib.
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Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
llvm-svn: 169131
2012-12-03 16:50:05 +00:00
136d6746c5
Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst
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which would then cause an assert when printed. rdar://11437956
llvm-svn: 168960
2012-11-29 23:47:11 +00:00
6fd9624843
Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target
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is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement.
llvm-svn: 166982
2012-10-29 23:27:20 +00:00
b23926d395
Fix a bug where a 32-bit address with the high bit does not get symbolicated
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because the value is incorrectly being signed extended when passed to
SymbolLookUp().
llvm-svn: 166234
2012-10-18 21:49:18 +00:00
0c97e76492
Fix the handling of edge cases in ARM shifted operands.
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This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.
Patch by Chris Lidbury.
llvm-svn: 164455
2012-09-22 11:18:12 +00:00
00e071ad52
Diagnose invalid alignments on duplicating VLDn instructions.
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Patch by Chris Lidbury.
llvm-svn: 163323
2012-09-06 15:27:12 +00:00
fb3cdd83b0
Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions.
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Patch by Chris Lidbury.
llvm-svn: 163321
2012-09-06 15:17:49 +00:00
228e6d4cf3
Fix integer undefined behavior due to signed left shift overflow in LLVM.
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Reviewed offline by chandlerc.
llvm-svn: 162623
2012-08-24 23:29:28 +00:00
f6add7e667
Remove unnecessary include of ARMGenInstrInfo.inc.
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llvm-svn: 162086
2012-08-17 06:21:09 +00:00
ecaef49f59
Switch the fixed-length disassembler to be table-driven.
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Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.
As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:
Time to compile at -O2 (averaged w/ hot caches):
Previous: 35.5s
New: 8.9s
TEXT size:
Previous: 447,251
New: 297,661
Builds in 25% of the time previously required and generates code 66% of
the size.
Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.
llvm-svn: 161888
2012-08-14 19:06:05 +00:00
6a43bf7d74
Fix #13035 , a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.
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llvm-svn: 161162
2012-08-02 08:29:50 +00:00
288e1af8c8
Fix #13138 , a bug around ARM instruction DSB encoding and decoding issue.
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llvm-svn: 161161
2012-08-02 08:21:27 +00:00
35521e2310
Fix a typo (the the => the)
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llvm-svn: 160621
2012-07-23 08:51:15 +00:00
1dc44dcedd
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
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llvm-svn: 159989
2012-07-10 12:51:09 +00:00
aeed158f75
Revert r159938 (and r159945) to appease the buildbots.
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llvm-svn: 159960
2012-07-09 20:43:34 +00:00
5beef2d242
Oops - correct broken disassembly for VMOV
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llvm-svn: 159945
2012-07-09 18:20:02 +00:00
c9e1c94fae
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)
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llvm-svn: 159938
2012-07-09 16:41:33 +00:00
f1ef87ddbb
Correct decoder for T1 conditional B encoding
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llvm-svn: 158055
2012-06-06 09:12:53 +00:00
70c1aa0bb5
ARMDisassembler.cpp: Fix utf8 char in comments.
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llvm-svn: 157292
2012-05-22 21:47:02 +00:00
cabbae653e
Tweak to the fix in r156212, as with the change in removing the shift the
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SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .
llvm-svn: 156213
2012-05-04 22:09:52 +00:00
8ce1ada1be
Fix a bug in the ARM disassembler for wide branch conditional instructions
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where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046
llvm-svn: 156212
2012-05-04 22:02:27 +00:00
914223010c
Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
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for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.
Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!
llvm-svn: 156118
2012-05-03 22:41:56 +00:00
9560af848c
Fixed disassembler for vstm/vldm ARM VFP instructions.
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llvm-svn: 156077
2012-05-03 16:38:40 +00:00
9d8f6f3d9d
ARM: Tweak tADDrSP definition for consistent operand order.
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Make the operand order of the instruction match that of the asm syntax.
llvm-svn: 155747
2012-04-27 23:51:33 +00:00
f435b09eaf
Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.
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llvm-svn: 155700
2012-04-27 08:42:59 +00:00
e9600009e9
Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector
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llvm-svn: 155439
2012-04-24 11:13:20 +00:00
ca45af9a75
Added support for disassembling unpredictable swp/swpb ARM instructions.
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llvm-svn: 155004
2012-04-18 14:18:57 +00:00
41f1fcd80e
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
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llvm-svn: 155001
2012-04-18 13:12:50 +00:00
29ae538647
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
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instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .
llvm-svn: 154884
2012-04-17 00:49:27 +00:00
40d4e47003
Fix a few more places in the ARM disassembler so that branches get
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symbolic operands added when using the C disassembler API.
llvm-svn: 154628
2012-04-12 23:13:34 +00:00
72f18bbcff
Fixed a case of ARM disassembly getting an assert on a bad encoding
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of a VST instruction.
llvm-svn: 154544
2012-04-11 22:40:17 +00:00
d2980cd041
Fix ARM disassembly of VLD instructions with writebacks. And add test a case
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for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .
llvm-svn: 154459
2012-04-11 00:25:40 +00:00
7a3973d3e0
ARMDisassembler: drop bogus dependency on ARMCodeGen
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And indirectly, a dependency on most of the core LLVM optimization
libraries.
llvm-svn: 153957
2012-04-03 15:48:14 +00:00
f6e7e12f75
Remove unnecessary llvm:: qualifications
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llvm-svn: 153500
2012-03-27 07:21:54 +00:00
4afd7d2316
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
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llvm-svn: 153252
2012-03-22 14:14:49 +00:00
d213f2111a
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
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llvm-svn: 153251
2012-03-22 13:24:43 +00:00
7e7d5eefb2
Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
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case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .
llvm-svn: 153218
2012-03-21 20:54:32 +00:00
32a49333ec
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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llvm-svn: 153089
2012-03-20 15:54:56 +00:00
ca658c2264
Use uint16_t to store registers and opcode in static tables in the target specific backends.
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llvm-svn: 152537
2012-03-11 07:16:55 +00:00
eed9992b26
Tidy up. Remove dead code that slipped into previous commit.
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llvm-svn: 152184
2012-03-07 00:52:39 +00:00
ed428bc1ce
ARM more NEON VLD/VST composite physical register refactoring.
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Register pair, all lanes subscripting.
llvm-svn: 152157
2012-03-06 23:10:38 +00:00
13a292cc74
ARM refactor more NEON VLD/VST instructions to use composite physregs
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Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
llvm-svn: 152150
2012-03-06 22:01:44 +00:00
520eb3ba8a
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
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llvm-svn: 152127
2012-03-06 18:33:12 +00:00
e5307f9019
ARM Refactor VLD/VST spaced pair instructions.
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Use the new composite physical registers.
llvm-svn: 152063
2012-03-05 21:43:40 +00:00
c988e0c521
ARM refactor away a bunch of VLD/VST pseudo instructions.
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With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
llvm-svn: 152045
2012-03-05 19:33:30 +00:00
56b662ce0f
Make MemoryObject accessor members const again
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llvm-svn: 151687
2012-02-29 01:09:06 +00:00
1489b523c3
Fix the symbolic operand added for the C disassmbler API for the ARM bl
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thumb instruction. The PC adjustment is +4 in Thumb mode and +8 in ARM mode.
llvm-svn: 151530
2012-02-27 18:15:15 +00:00
Gordon Keiser