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347 Commits

Author SHA1 Message Date
Evan Cheng 2c450d35ae Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate. 
llvm-svn: 74692
 2009-07-02 06:38:40 +00:00
Bob Wilson deb35afd23 Add a new addressing mode for NEON load/store instructions. 
llvm-svn: 74658
 2009-07-01 23:16:05 +00:00
David Goodwin 27303cde82 Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table. 
llvm-svn: 74543
 2009-06-30 18:04:13 +00:00
Evan Cheng 57726817aa A few more load instructions. 
llvm-svn: 74500
 2009-06-30 02:15:48 +00:00
Evan Cheng b23b50d54d Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
 2009-06-29 07:51:04 +00:00
Evan Cheng eab9ca7ea6 Renaming for consistency. 
llvm-svn: 74368
 2009-06-27 02:26:13 +00:00
Evan Cheng d76f0be844 Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag. 
llvm-svn: 74158
 2009-06-25 02:08:06 +00:00
Evan Cheng bec1dba896 Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available. 
llvm-svn: 73985
 2009-06-23 19:38:13 +00:00
Evan Cheng 431cf567de Initial Thumb2 support. Majority of the work is done by David Goodwin. There are 
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.

I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.

Test cases will be contributed later after I re-organize what's in svn first.

llvm-svn: 73965
 2009-06-23 17:48:47 +00:00
Bob Wilson 2e076c4e02 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919
 2009-06-22 23:27:02 +00:00
Evan Cheng fabdcce677 Handle the rest of pseudo instructions. 
llvm-svn: 59275
 2008-11-13 23:36:57 +00:00
Evan Cheng 2666f59322 Fix pre- and post-indexed load / store encoding bugs. 
llvm-svn: 59230
 2008-11-13 07:34:59 +00:00
Evan Cheng af644b50b4 Consolidate formats; fix FCMPED etc. encodings. 
llvm-svn: 59107
 2008-11-12 07:18:38 +00:00
Evan Cheng 4b6c7efbde Fix VFP conversion instruction encodings. 
llvm-svn: 59104
 2008-11-12 06:41:41 +00:00
Evan Cheng 97ccab888a Fix FMDRR encoding. 
llvm-svn: 59088
 2008-11-11 22:46:12 +00:00
Evan Cheng 8cbbcb1f2f Encode VFP load / store instructions. 
llvm-svn: 59084
 2008-11-11 21:48:44 +00:00
Evan Cheng 38c9a14a88 Encode VFP conversion instructions. 
llvm-svn: 59074
 2008-11-11 19:40:26 +00:00
Evan Cheng ac2af2fdb2 Encode VFP arithmetic instructions. 
llvm-svn: 59016
 2008-11-11 02:11:05 +00:00
Evan Cheng 7095cd2af2 Jump table JIT support. Work in progress. 
llvm-svn: 58836
 2008-11-07 09:06:08 +00:00
Evan Cheng 98dc53e926 Encode misc arithmetic instructions. 
llvm-svn: 58828
 2008-11-07 01:41:35 +00:00
Evan Cheng 49d665218c Encode extend instructions; more clean up. 
llvm-svn: 58818
 2008-11-06 22:15:19 +00:00
Evan Cheng aa03cd3336 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm. 
- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808
 2008-11-06 17:48:05 +00:00
Evan Cheng 47b546d75f Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
llvm-svn: 58800
 2008-11-06 08:47:38 +00:00
Evan Cheng 36ae40342f Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>. 
llvm-svn: 58793
 2008-11-06 03:35:07 +00:00
Evan Cheng 2686c8fb34 Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls. 
llvm-svn: 58789
 2008-11-06 01:21:28 +00:00
Evan Cheng fd2adbfa28 Encode pic load / store instructions; fix some encoding bugs. 
llvm-svn: 58780
 2008-11-05 23:22:34 +00:00
Evan Cheng 81889d010c Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions. 
llvm-svn: 58764
 2008-11-05 18:35:52 +00:00
Evan Cheng 453844c352 LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR. 
llvm-svn: 58707
 2008-11-04 17:57:07 +00:00
Jim Grosbach 4d0549e3be Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there. 
llvm-svn: 58626
 2008-11-03 18:38:31 +00:00
Jim Grosbach b7c01f5f48 Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right) 
llvm-svn: 57524
 2008-10-14 20:36:24 +00:00
Evan Cheng 7848cfcd77 Fix addrmode1 instruction encodings; fix bx_ret encoding. 
llvm-svn: 56277
 2008-09-17 07:53:38 +00:00
Evan Cheng 937569afe3 Specify instruction encoding using range list to avoid endianess issues. 
llvm-svn: 56276
 2008-09-17 07:16:21 +00:00
Evan Cheng 12134701ec Revert 56176. All those instruction formats are still needed. 
llvm-svn: 56180
 2008-09-13 01:35:33 +00:00
Evan Cheng c5c74f36fd Eliminate unnecessary instruction formats. 
llvm-svn: 56176
 2008-09-12 23:15:39 +00:00
Evan Cheng d1424c4eca Addrmode 1 S bit can be dynamically set. Look for CPSR def. 
llvm-svn: 56172
 2008-09-12 22:45:55 +00:00
Evan Cheng fa558788e7 Control flow instruction encodings. 
llvm-svn: 55601
 2008-09-01 08:25:56 +00:00
Evan Cheng c288cc0572 ldm / stm instruction encodings. 
llvm-svn: 55599
 2008-09-01 07:48:18 +00:00
Evan Cheng c37532b24a AXI2 and AXI3 instruction encodings. 
llvm-svn: 55598
 2008-09-01 07:34:13 +00:00
Evan Cheng a282723499 Reorganize instruction formats again; AXI1 encoding. 
llvm-svn: 55597
 2008-09-01 07:19:00 +00:00
Evan Cheng 169eccc24e addrmode3 instruction encodings. 
llvm-svn: 55596
 2008-09-01 07:00:14 +00:00
Evan Cheng 624844b4dd Reorganize some instruction format definitions. No functionality change. 
llvm-svn: 55594
 2008-09-01 01:51:14 +00:00
Evan Cheng cccca875b1 Rest of addrmode2 instruction encodings. 
llvm-svn: 55593
 2008-09-01 01:27:33 +00:00
Evan Cheng 01fd3f129a Addr2 word / byte load encodings. 
llvm-svn: 55591
 2008-08-31 19:02:21 +00:00
Evan Cheng 5b6c931e1f Addr1 instructions opcodes are encoded in bits 21-24; encode S bit. 
llvm-svn: 55590
 2008-08-31 18:32:16 +00:00
Evan Cheng c139c221dd addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode. 
llvm-svn: 55531
 2008-08-29 07:40:52 +00:00
Evan Cheng ee98fa9db2 More refactoring. 
llvm-svn: 55528
 2008-08-29 06:41:12 +00:00
Evan Cheng 2d37f19ef2 Refactor ARM instruction format definitions into a separate file. No functionality changes. 
llvm-svn: 55518
 2008-08-28 23:39:26 +00:00