3b1459b810
Narrow right shifts need to encode their immediates differently from a normal
...
shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
llvm-svn: 126723
2011-03-01 01:00:59 +00:00
97e6428014
Change VFPNeonA8 definition to make the code easier to read.
...
llvm-svn: 126298
2011-02-23 02:35:33 +00:00
04ad35b53f
VFP single precision arith instructions can go down to NEON pipeline, but on Cortex-A8 only.
...
llvm-svn: 126238
2011-02-22 19:53:14 +00:00
9cd43977c3
Add assembly parsing support for "msr" and also fix its encoding. Also add
...
testcases for the disassembler to make sure it still works for "msr".
llvm-svn: 125948
2011-02-18 19:45:59 +00:00
4a8c43fe6d
Some single precision VFP instructions may be executed on NEON pipeline, but not double precision ones.
...
llvm-svn: 125624
2011-02-16 00:35:02 +00:00
90d1dfe4c6
Fix encoding and add parsing support for the arm/thumb CPS instruction:
...
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
llvm-svn: 125489
2011-02-14 13:09:44 +00:00
861e49ce3b
AsmMatcher custom operand parser failure enhancements.
...
Teach the AsmMatcher handling to distinguish between an error custom-parsing
an operand and a failure to match. The former should propogate the error
upwards, while the latter should continue attempting to parse with
alternative matchers.
Update the ARM asm parser accordingly.
llvm-svn: 125426
2011-02-12 01:34:40 +00:00
36dd43fda6
Add support for parsing dmb/dsb instructions
...
llvm-svn: 125055
2011-02-07 22:09:15 +00:00
4d4b490fb7
Add mcr*2 and mr*c2 support to thumb2 targets
...
llvm-svn: 123919
2011-01-20 16:58:48 +00:00
cf99dc7eb9
Add mcr* and mr*c support to thumb targets
...
llvm-svn: 123917
2011-01-20 16:35:57 +00:00
ec86bac8b3
Add a FIXME.
...
llvm-svn: 123769
2011-01-18 19:59:19 +00:00
d42257ceef
The new t2LEApcrel* pseudo instructions need the size specified.
...
rdar://8768390
llvm-svn: 121876
2010-12-15 18:48:45 +00:00
b538a22762
Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends.
...
llvm-svn: 121585
2010-12-10 22:32:08 +00:00
95bd6b7b62
Tidy up.
...
llvm-svn: 121522
2010-12-10 20:51:35 +00:00
c4669edf2c
Trailing whitespace.
...
llvm-svn: 121521
2010-12-10 20:47:29 +00:00
cf096a431a
Fix Thumb2 encoding of the S bit.
...
llvm-svn: 121182
2010-12-07 20:50:15 +00:00
0bfb4d5043
The ARM AsmMatcher needs to know that the CCOut operand is a register value,
...
not an immediate. It stores either ARM::CPSR or reg0.
llvm-svn: 121018
2010-12-06 18:21:12 +00:00
87240d4b9c
Add a post encoder method to the VFP instructions to convert them to the Thumb2
...
encoding if we're in that mode.
llvm-svn: 120608
2010-12-01 21:54:50 +00:00
943fb60b1f
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
...
llvm-svn: 120589
2010-12-01 19:18:46 +00:00
cbb08ca08c
General cleanups of comments.
...
llvm-svn: 120536
2010-12-01 02:42:55 +00:00
c25545a1a7
s/T1pIEncode/T1pILdStEncode/g
...
s/T1pIEncodeImm/T1pILdStEncodeImm/g
llvm-svn: 120524
2010-12-01 01:38:08 +00:00
7c646b924b
Renaming variables to coincide with documentation. No functionality change.
...
llvm-svn: 120522
2010-12-01 01:32:02 +00:00
05632cb5cc
Rename operands to match ARM documentation. No functionality change.
...
llvm-svn: 120500
2010-11-30 23:54:45 +00:00
5c51fcda81
Inline classes that were used in only one place.
...
llvm-svn: 120488
2010-11-30 23:16:25 +00:00
a9e3df7aa0
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
...
t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
llvm-svn: 120482
2010-11-30 22:57:21 +00:00
cd5e30f6c6
Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.
...
rdar://8685712
llvm-svn: 120438
2010-11-30 18:30:19 +00:00
e22c7322b8
Correct Thumb2 encodings for a much wider range of loads and stores.
...
llvm-svn: 120364
2010-11-30 00:14:31 +00:00
0c51bb4b25
Parameterize ARMPseudoInst size property.
...
llvm-svn: 120353
2010-11-29 23:48:41 +00:00
58bc36a3a9
ARM Pseudo-ize tBR_JTr.
...
llvm-svn: 120310
2010-11-29 19:32:47 +00:00
150b1ad7f8
Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.
...
llvm-svn: 120303
2010-11-29 18:37:44 +00:00
5876e41c9f
trailing whitespace
...
llvm-svn: 119863
2010-11-19 22:42:55 +00:00
09d7bfd886
Add ARM encoding information for STRD.
...
llvm-svn: 119852
2010-11-19 22:14:31 +00:00
6e9aace4f3
Factor out operand encoding bits for ARM addressing mode 2 store instructions.
...
llvm-svn: 119846
2010-11-19 21:35:06 +00:00
09f6823eb6
Delete another dead class.
...
llvm-svn: 119844
2010-11-19 21:16:08 +00:00
e093e5f0dc
whitespace tweak.
...
llvm-svn: 119843
2010-11-19 21:14:37 +00:00
d6e5c9f2fe
Refactor PICSTR* instructions to really be pseudos. Nuke dead classes.
...
llvm-svn: 119841
2010-11-19 21:14:02 +00:00
4a22eba616
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes.
...
llvm-svn: 119840
2010-11-19 21:07:51 +00:00
003c6e700b
Add ARM binary encoding information for the rest of the indexed loads.
...
llvm-svn: 119821
2010-11-19 19:41:26 +00:00
c6ac246671
Remove dead code.
...
llvm-svn: 119815
2010-11-19 18:18:37 +00:00
76aed40813
ARM LDRD binary encoding.
...
llvm-svn: 119812
2010-11-19 18:16:46 +00:00
1b91ae18ed
Add ARM encoding information for LDRH post-increment.
...
llvm-svn: 119743
2010-11-18 21:43:37 +00:00
3625098459
Fill out the set of Thumb2 multiplication operator encodings.
...
llvm-svn: 119733
2010-11-18 20:32:18 +00:00
51fdc47a11
ARMPseudoInst instructions should default to being considered a single 4-byte
...
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274
llvm-svn: 119713
2010-11-18 18:01:40 +00:00
a74c7ccd59
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
...
the operand to the pattern.
llvm-svn: 119607
2010-11-18 01:38:26 +00:00
19be1fbca1
Add FIXME.
...
llvm-svn: 119603
2010-11-18 01:20:48 +00:00
cfb66204b7
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not
...
just pretend to be.
llvm-svn: 119602
2010-11-18 01:15:56 +00:00
8e7f8df4a2
Refactor a few ARM load instructions to better parameterize things and re-use
...
common encoding information.
llvm-svn: 119598
2010-11-18 00:46:58 +00:00
8839775df6
More ARM encoding bits. LDRH now encodes properly.
...
llvm-svn: 119529
2010-11-17 18:11:11 +00:00
345b48fcbd
Add binary emission stuff for VLDM/VSTM. This reuses the
...
"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.
llvm-svn: 119435
2010-11-17 00:45:23 +00:00
3bd60eff26
- Remove dead patterns.
...
- Add encodings to the *LDMIA_RET instrs. Probably not needed...
llvm-svn: 119323
2010-11-16 02:08:45 +00:00
38b469effd
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
...
llvm-svn: 119180
2010-11-15 20:47:07 +00:00
63274cbc5d
add fields to the .td files unconditionally, simplifying tblgen a bit.
...
Switch the ARM backend to use 'let' instead of 'set' with this change.
llvm-svn: 119120
2010-11-15 05:19:05 +00:00
e69afc6bb7
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
...
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
llvm-svn: 118995
2010-11-13 09:09:38 +00:00
2f790749e8
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
...
flag for the LDRT/STRT family instructions as a side effect.
llvm-svn: 118955
2010-11-13 00:35:48 +00:00
31a7234a47
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
...
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
llvm-svn: 118925
2010-11-12 21:28:15 +00:00
2d59ee34f1
Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
...
llvm-svn: 118922
2010-11-12 20:32:20 +00:00
6bb1ae9d45
Kill more unused stuff.
...
llvm-svn: 118921
2010-11-12 19:27:45 +00:00
984ff7d17e
Remove unused class.
...
llvm-svn: 118919
2010-11-12 19:24:53 +00:00
0deb9c20c0
Encoding for ARM LDRSB instructions.
...
llvm-svn: 118905
2010-11-12 17:52:59 +00:00
ce2250fba4
Fill out support for Thumb2 encodings of NEON instructions.
...
llvm-svn: 118854
2010-11-11 23:12:55 +00:00
99a8cb4875
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
...
llvm-svn: 118843
2010-11-11 21:36:43 +00:00
7ffe3b35ac
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
...
More tests to come.
llvm-svn: 118819
2010-11-11 19:07:48 +00:00
68685e644f
Encoding for ARM LDRSH_POST.
...
llvm-svn: 118794
2010-11-11 16:55:29 +00:00
f18b951e18
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
...
llvm-svn: 118767
2010-11-11 01:55:59 +00:00
607efcbc3e
ARM STRH encoding information.
...
llvm-svn: 118757
2010-11-11 01:09:40 +00:00
c4dd2349c7
Move LDM predicate operand encoding into base clase. Add STM missing STM
...
encoding bits.
llvm-svn: 118738
2010-11-10 23:44:32 +00:00
cc4a491557
ARM LDM encoding for the mode (ia, ib, da, db) operand.
...
llvm-svn: 118736
2010-11-10 23:38:36 +00:00
58ef598cd1
Fix ARM encoding of non-return LDM instructions.
...
llvm-svn: 118732
2010-11-10 23:18:49 +00:00
e39a9fcc0e
Fix ARM encoding of LDM+Return instruction.
...
llvm-svn: 118730
2010-11-10 23:12:48 +00:00
c002463ac4
Add encoding for VSTR.
...
llvm-svn: 118220
2010-11-04 00:59:42 +00:00
0ebd1fd594
Revert r118097 to fix buildbots.
...
llvm-svn: 118121
2010-11-02 23:47:29 +00:00
7c30390277
Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.
...
llvm-svn: 118097
2010-11-02 22:41:42 +00:00
9f20daf3b4
Factor out a common encoding class for loads and stores with a lane parameter.
...
llvm-svn: 118055
2010-11-02 20:47:39 +00:00
ad40234eff
Add correct NEON encodings for the "multiple single elements" form of vld.
...
llvm-svn: 117984
2010-11-02 00:05:05 +00:00
418bd53008
Move the machine operand MC encoding patterns to the parent classes.
...
llvm-svn: 117956
2010-11-01 21:17:06 +00:00
fddf36d254
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
...
codegen using the patterns; the latter gates the assembler recognizing the
instruction.
llvm-svn: 117931
2010-11-01 17:08:58 +00:00
2623343625
Move instruction encoding bits into the parent class and remove the temporary
...
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.
llvm-svn: 117906
2010-11-01 06:00:39 +00:00
7ff334687d
fix the !eq operator in tblgen to return a bit instead of an int.
...
Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
llvm-svn: 117862
2010-10-31 19:22:57 +00:00
74ef9e184e
Encode the register list operands for ARM mode LDM/STM instructions.
...
llvm-svn: 117753
2010-10-30 00:37:59 +00:00
3b7e05bb97
ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
...
llvm-svn: 117702
2010-10-29 20:21:36 +00:00
4e57b52394
ARM mode LDREX*/STREX* binary encodings.
...
llvm-svn: 117695
2010-10-29 19:58:57 +00:00
338de3ee56
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
...
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
ed9652f959
Provide correct encodings for the get_lane and set_lane variants of vmov.
...
llvm-svn: 117495
2010-10-27 21:28:09 +00:00
40d24a4abf
Provide correct NEON encodings for vdup.
...
llvm-svn: 117475
2010-10-27 19:25:54 +00:00
1e4d9a17c2
First part of refactoring ARM addrmode2 (load/store) instructions to be more
...
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
3665fee8de
Provide correct NEON encodings for vshl, register and immediate forms.
...
llvm-svn: 117394
2010-10-26 20:56:57 +00:00
284cb361d1
Add NEON encodings for vmov and vmvn of immediates.
...
llvm-svn: 117374
2010-10-26 17:40:54 +00:00
b45591979b
NEON vmov's are in Neon domain.
...
llvm-svn: 117347
2010-10-26 02:03:05 +00:00
2477446ee5
Add correct instruction encodings for vbic, vorn, and vmvn.
...
llvm-svn: 117282
2010-10-25 18:43:52 +00:00
dff239c5f9
Provide correct NEON encodings for vand, veor, and vorr.
...
llvm-svn: 117279
2010-10-25 18:28:30 +00:00
2c9ae05c67
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
...
llvm-svn: 117165
2010-10-22 22:12:16 +00:00
6956a60563
More ARM multiply instuction binary encodings.
...
llvm-svn: 117121
2010-10-22 18:35:16 +00:00
f98df0849f
Parameterize a bit of ARM encoding information, simplifying some instruction
...
definitions.
llvm-svn: 117114
2010-10-22 17:42:06 +00:00
22261600a8
More ARM multiply instruction encoding information.
...
llvm-svn: 117108
2010-10-22 17:16:17 +00:00
9e44cf2bb2
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
...
half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
llvm-svn: 117056
2010-10-21 20:21:49 +00:00
59351844e1
ARM instructions that are both predicated and set the condition codes
...
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
llvm-svn: 116563
2010-10-15 03:23:44 +00:00
b9386558a7
trailing whitespace
...
llvm-svn: 116450
2010-10-13 23:12:26 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
d9d31dafda
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
...
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
llvm-svn: 116360
2010-10-12 23:00:24 +00:00
98c29d732d
Split out the "size" field from the encoding. The newer documentation has it as
...
a separate bit in the coding.
llvm-svn: 116347
2010-10-12 22:03:19 +00:00
576640f0e3
Encoding for ARM-mode VADD.F32 instruction.
...
llvm-svn: 116338
2010-10-12 21:22:40 +00:00
5476a274c8
More binary encoding stuff, taking advantage of the new "by name" operand
...
matching in tblgen to do the predicate operand.
llvm-svn: 116213
2010-10-11 18:51:51 +00:00
233b3a2f95
Add a 'pattern' arg to the ARM PseudoNeonI class.
...
llvm-svn: 115831
2010-10-06 20:36:55 +00:00
04c342ea20
replace stuff like:
...
let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
llvm-svn: 115720
2010-10-06 00:05:18 +00:00
e929899a3f
Increase the number of bits used internally by the ARM target to represent the
...
addressing mode from four to five.
llvm-svn: 115645
2010-10-05 18:14:55 +00:00
6b853c3ce3
Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
...
register allocation to VLDMD and VSTMD respectively. This avoids using the
dregpair operand modifier.
llvm-svn: 114047
2010-09-16 00:31:02 +00:00
c597fd3b4a
Convert some VTBL and VTBX instructions to use pseudo instructions prior to
...
register allocation. Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!
llvm-svn: 113818
2010-09-13 23:55:10 +00:00
abcbe2474d
VFP/NEON load/store multiple instructions are addrmode4, not 5.
...
llvm-svn: 113322
2010-09-08 00:25:50 +00:00
b70dc8777e
- Cleanup some whitespaces.
...
- Convert {0,1} and friends into 0b01, which is identical and more consistent.
llvm-svn: 112593
2010-08-31 07:50:46 +00:00
87bb14c566
Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which
...
is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this
out! :-)
llvm-svn: 112538
2010-08-30 22:05:23 +00:00
f8dfa461fa
Create Thumb2sI_cpsr and T2sI_cpsr. These new classes indicate that CPSR is the
...
optional modified register (instead of reg0). Along with r112461 it will make
sure that the optional define of CPSR is marked as "def" and will thus mark the
instructions using these classes (t2ANDS*) as setting the 's' flag.
llvm-svn: 112462
2010-08-30 01:47:35 +00:00
9392b0e960
Start converting NEON load/stores to use pseudo instructions, beginning here
...
with the VST4 instructions. Until after register allocation, we want to
represent sets of adjacent registers by a single super-register. These
VST4 pseudo instructions have a single QQ or QQQQ source register operand.
They get expanded to the real VST4 instructions with 4 separate D register
operands. Once this conversion is complete, we'll be able to remove the
NEONPreAllocPass and avoid some fragile and hacky code elsewhere.
llvm-svn: 112108
2010-08-25 23:27:42 +00:00
d8042b7bd7
MC/ARM: Add an ARMOperand class for condition codes.
...
llvm-svn: 110788
2010-08-11 06:36:53 +00:00
9664984be8
Add a separate ARM instruction format for Saturate instructions.
...
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!! Two of them were already out of sync. I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.) Add support for encoding these instructions.
llvm-svn: 110754
2010-08-11 00:01:18 +00:00
ff66cd43c4
ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608
...
llvm-svn: 109125
2010-07-22 17:28:34 +00:00
b4d39841e4
Renumber NEON instruction formats to be consecutive.
...
llvm-svn: 106927
2010-06-26 00:05:09 +00:00
cc386fb125
Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to
...
"N..." instead of "NEON..." for consistency with the other NEON format names.
llvm-svn: 106921
2010-06-25 23:56:05 +00:00
d66f66a5cf
Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.
...
Renumber MiscFrm to 25.
llvm-svn: 106916
2010-06-25 23:45:37 +00:00
722bff2c7d
Clean up some extra whitespace.
...
llvm-svn: 104544
2010-05-24 20:08:34 +00:00
b93331f3be
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
...
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
llvm-svn: 100384
2010-04-05 03:10:20 +00:00
c86256fa5d
Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions.
...
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd). The table is specified via
a list of vectors, which can be:
{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}
llvm-svn: 99789
2010-03-29 01:14:22 +00:00
cf603fb1c5
Add a format argument to the N3V and N3VX classes, removing the N3Vf class.
...
llvm-svn: 99704
2010-03-27 03:56:52 +00:00
6094cdab9f
Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set
...
it as the format for the appropriate N3V*SL*<> classes. These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.
Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):
vmlal.s32 q3, d2, d10[0]
llvm-svn: 99690
2010-03-27 01:03:13 +00:00
0b57de3c4c
Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}
...
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.
Modify VEXTd and VEXTq classes to use the format.
llvm-svn: 99659
2010-03-26 22:28:56 +00:00
2cf04957c2
Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
...
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm. The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from. N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.
Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.
llvm-svn: 99655
2010-03-26 21:26:28 +00:00
8fc94d6362
Add N3RegFrm to represent "NEON 3 vector register format" instructions.
...
Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).
llvm-svn: 99628
2010-03-26 18:32:20 +00:00
5d4e917d9f
Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily
...
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field. The Vd, Vm fields are interpreted
the same between the two, though.
See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.
llvm-svn: 99590
2010-03-26 01:07:59 +00:00
a3617ec88a
Removed instruction class NI from ARMInstrFormats.td.
...
It doesn't seem to be used anywhere.
llvm-svn: 99566
2010-03-25 23:11:56 +00:00
91d2774416
Add NVDupLnFrm and change NVDupLane class to use that format.
...
llvm-svn: 99557
2010-03-25 21:49:12 +00:00
d82f9002e4
Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to
...
expect a Format arg. N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.
llvm-svn: 99548
2010-03-25 20:39:04 +00:00
45ab3f3ccf
Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,
...
instead of the current N2V. Format of NVDupLane instances are set to NEONFrm
currently.
llvm-svn: 99518
2010-03-25 17:01:27 +00:00
34de7768bf
Make the use of the vmla and vmls VFP instructions controllable via cmd line.
...
Preliminary testing shows significant performance wins by not using these
instructions.
llvm-svn: 99436
2010-03-24 22:31:46 +00:00
e99953ce9c
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
...
NVCVTFrm will later be used to describe "vcvt with fractional bits".
llvm-svn: 99415
2010-03-24 19:47:14 +00:00
9b1f60adec
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
...
respectively, and add some more comment.
llvm-svn: 99373
2010-03-24 00:57:50 +00:00
6a64320da8
Renamed NVdImmFrm to N1RegModImmFrm.
...
llvm-svn: 99344
2010-03-23 23:09:14 +00:00
8a687233e3
Fix typo in the comment for N3VX class.
...
llvm-svn: 99328
2010-03-23 21:35:03 +00:00
5dbf39285d
Add New NEON Format NVdVmVCVTFrm.
...
Converted some of the NEON vcvt instructions to this format.
llvm-svn: 99326
2010-03-23 21:25:38 +00:00
020023a3fa
Add New NEON Format NVdVmImmFrm.
...
llvm-svn: 99322
2010-03-23 20:40:44 +00:00
59f75bba24
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
...
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
llvm-svn: 99309
2010-03-23 18:54:46 +00:00
3968c6a252
Fix bad indentation, 80-column violations, and trailing whitespace.
...
llvm-svn: 99295
2010-03-23 17:23:59 +00:00
ac5024bbeb
Add New NEON Format NVdImmFrm.
...
Ref: A7.4.6 One register and a modified immediate value.
llvm-svn: 99288
2010-03-23 16:43:47 +00:00
f833fad813
Add NLdStFrm Format.
...
llvm-svn: 99014
2010-03-20 00:17:00 +00:00
e4191e719b
Revert this change, since it was causing ARM performance regressions.
...
--- Reverse-merging r98889 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMInstrFormats.td
llvm-svn: 99010
2010-03-19 22:51:32 +00:00
0dab68f3d0
Renumber LdStExFrm from 28 to 11 and shift the existing format values to make
...
room for it. This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.
llvm-svn: 98967
2010-03-19 17:39:00 +00:00
a4d86b63c7
Update comment to refer to the right filename.
...
llvm-svn: 98902
2010-03-18 23:57:57 +00:00
f11aa9e7b4
Get rid of target-specific fp <-> int nodes when still I'm here.
...
llvm-svn: 98889
2010-03-18 22:35:45 +00:00
fb2ceede8f
fix some buggy ops concatentation
...
llvm-svn: 98869
2010-03-18 21:06:54 +00:00
274a0d3794
Revert 98745 with respect to the addition of NEONFrm subformats for disassembly.
...
There is a better way coming up.
llvm-svn: 98777
2010-03-17 23:26:50 +00:00
69ba1bcd05
Increase format field from 5 to 6 bits. ARMII::FormMask was increased to 0x3f
...
in svn r74988 but the format field was never widened.
llvm-svn: 98768
2010-03-17 21:13:43 +00:00
Bill Wendling