Commit Graph

238394 Commits

Author SHA1 Message Date
Michael Zolotukhin b2738e41bf [LoopUnroll] Switch the default value of -unroll-runtime-epilog back to its original value.
As agreed in post-commit review of r265388, I'm switching the flag to
its original value until the 90% runtime performance regression on
SingleSource/Benchmarks/Stanford/Bubblesort is addressed.

llvm-svn: 277524
2016-08-02 21:24:14 +00:00
Jonathan Coe 77ec263e60 [clang-tidy] Fix segfault in cppcore-guidelines-special-member-functions check
Summary:
Use a set rather than a vector of defined special member functions so
that multiple declarations of the same function are only counted once.

Move some private static member functions into the cpp file.

Run clang-format on header.

Reviewers: ericLemanissier, Prazek, aaron.ballman

Subscribers: Prazek, cfe-commits, nemanjai

Projects: #clang-tools-extra

Differential Revision: https://reviews.llvm.org/D23008

llvm-svn: 277523
2016-08-02 21:18:37 +00:00
Devin Coughlin 6eb1ca7416 [CFG] Fix crash finding destructor of lifetime-extended temporary.
Fix a crash under -Wthread-safety when finding the destructor for a
lifetime-extending reference.

A patch by Nandor Licker!

Differential Revision: https://reviews.llvm.org/D22419

llvm-svn: 277522
2016-08-02 21:07:23 +00:00
Lang Hames 368c4223b8 [lli] Add the ability for OrcLazyJIT to accept multiple input modules.
LLI already supported passing multiple input modules to MCJIT via the
-extra-module option. This patch adds the plumbing to pass these modules to
the OrcLazy JIT too.

This functionality will be used in an upcoming test case for weak symbol
handling.

llvm-svn: 277521
2016-08-02 21:00:40 +00:00
Artem Belevich db4bc667af [NVPTX] remove unnecessary named metadata update that happens to break debug info.
Also added test case to verify IR changes done by NVPTXGenericToNVVM pass.

Differential Revision: https://reviews.llvm.org/D22837

llvm-svn: 277520
2016-08-02 20:58:24 +00:00
Etienne Bergeron 5d42763779 [compiler-rt] Add more interception patterns.
Summary:
These instructions where not supported on my win7 computer.
They were happening on strstr when building chrome unittests with asan.

Reviewers: rnk

Subscribers: llvm-commits, chrisha

Differential Revision: https://reviews.llvm.org/D23081

llvm-svn: 277519
2016-08-02 20:38:05 +00:00
Reid Kleckner d6371ea52a [asan] Intercept RtlRaiseException instead of kernel32!RaiseException
Summary:
On my install of Windows 10, RaiseException is a tail call to
kernelbase!RaiseException. Obviously, we fail to intercept that.
Instead, try hooking at the ntdll!RtlRaiseException layer. It is
unlikely that this layer will contain control flow.

Intercepting at this level requires adding a decoding for
'LEA ESP, [ESP + 0xXXXXXXXX]', which is a really obscure way to write
'SUB ESP, 0xXXXXXXXX' that avoids clobbering EFLAGS.

Reviewers: etienneb

Subscribers: llvm-commits, kubabrecka

Differential Revision: https://reviews.llvm.org/D23046

llvm-svn: 277518
2016-08-02 20:36:29 +00:00
Alexander Kornienko 053826f146 [docs] Fix links format.
llvm-svn: 277517
2016-08-02 20:29:47 +00:00
Alexander Kornienko 5e0a50c2d7 [clang-tidy] MPITypeMismatchCheck
This check verifies if buffer type and MPI (Message Passing Interface)
datatype pairs match. All MPI datatypes defined by the MPI standard (3.1)
are verified by this check. User defined typedefs, custom MPI datatypes and
null pointer constants are skipped, in the course of verification.

Instructions on how to apply the check can be found at:
https://github.com/0ax1/MPI-Checker/tree/master/examples

Patch by Alexander Droste!

Differential revision: https://reviews.llvm.org/D21962

llvm-svn: 277516
2016-08-02 20:29:35 +00:00
Wei Mi dc7001afb2 [LoopVectorize] Change comment for isOutOfScope in collectLoopUniforms, NFC
Update comment for isOutOfScope and add a testcase for uniform value being used
out of scope.

Differential Revision: https://reviews.llvm.org/D23073

llvm-svn: 277515
2016-08-02 20:27:49 +00:00
Reid Kleckner dabcee8b2c Remove stale CHECK lines that should have been included in r277478
We no longer assign ids to unregistered threads. We don't have any stack
trace for thread creation for these worker threads, so this shouldn't
affect report quality much.

llvm-svn: 277514
2016-08-02 20:26:59 +00:00
Tim Northover 1021d89398 AArch64: properly calculate cmpxchg status in FastISel.
We were relying on the misleadingly-names $status result to actually be the
status. Actually it's just a scratch register that may or may not be valid (and
is the inverse of the real ststus anyway). Success can be determined by
comparing the value loaded against the one we wanted to see for "cmpxchg
strong" loops like this.

Should fix PR28819.

llvm-svn: 277513
2016-08-02 20:22:36 +00:00
Eric Fiselier 84c557ad3e Pass compilers when configuring Google Benchmark.
llvm-svn: 277512
2016-08-02 20:21:07 +00:00
Etienne Bergeron eb09609f39 fix comments typos [NFC]
llvm-svn: 277511
2016-08-02 20:07:49 +00:00
Daniel Berlin 26fcea91f6 Fixes for post-commit review comments on r277480
llvm-svn: 277510
2016-08-02 20:02:21 +00:00
Xinliang David Li 14c91c4eca [Profile] track ownership of filename pattern string
Make sure runtime copy and owns the string when passed
in from external users of runtime API.

llvm-svn: 277507
2016-08-02 19:34:00 +00:00
Sanjoy Das 83a72850c7 [IRCE] Rename variable; NFC
There is nothing "Original" about "OriginalLoopInfo".

llvm-svn: 277506
2016-08-02 19:32:01 +00:00
Sanjoy Das f45e03e201 [IRCE] Preserve DomTree and LCSSA
This changes IRCE to "preserve" LCSSA and DomTree by recomputing them.
It still does not preserve LoopSimplify.

llvm-svn: 277505
2016-08-02 19:31:54 +00:00
Nicolai Haehnle 8a482b33fe AMDGPU: Stay in WQM for non-intrinsic stores
Summary:
Two types of stores are possible in pixel shaders: stores to memory that are
explicitly requested at the API level, and stores that are an implementation
detail of register spilling or lowering of arrays.

For the first kind of store, we must ensure that helper pixels have no effect
and hence WQM must be disabled. The second kind of store must always be
executed, because the written value may be loaded again in a way that is
relevant for helper pixels as well -- and there are no externally visible
effects anyway.

This is a candidate for the 3.9 release branch.

Reviewers: arsenm, tstellarAMD, mareko

Subscribers: arsenm, kzhuravl, llvm-commits

Differential Revision: https://reviews.llvm.org/D22675

llvm-svn: 277504
2016-08-02 19:31:14 +00:00
Albert Gutowski 3a9f2a5a8d test commit
llvm-svn: 277503
2016-08-02 19:25:17 +00:00
Michael Zolotukhin d9b6ad3c01 [LoopUnroll] Ensure we create prolog loops in simplified form.
llvm-svn: 277502
2016-08-02 19:19:31 +00:00
Nirav Dave 9263ae3b5a Fix handling of end-of-line preprocessor comments Attempt 2
Attempt 2: Retryign after Tsan.mman test fix.

Attempt 1: Recommitting after fixing test.

When parsing assembly where the line comment syntax is not hash, the
lexer cannot distinguish between hash's that start a hash line comment
and one that is part of an assembly statement and must be distinguished
during parsing. Previously, this was incompletely handled by not checking
for EndOfStatement at the end of statements and interpreting hash
prefixed statements as comments.

Change EndOfStatement Parsing to check for Hash comments and reintroduce
Hash statement parsing to catch previously handled cases.

Reviewers: rnk, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23017

llvm-svn: 277501
2016-08-02 19:17:54 +00:00
Nicolai Haehnle bef0e90cf1 AMDGPU: Track physical registers in SIWholeQuadMode
Summary:
There are cases where uniform branch conditions are computed in VGPRs, and
we didn't correctly mark those as WQM.

The stray change in basic-branch.ll is because invoking the LiveIntervals
analysis leads to the detection of a dead register that would otherwise not
be seen at -O0.

This is a candidate for the 3.9 branch, as it fixes a possible hang.

Reviewers: arsenm, tstellarAMD, mareko

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D22673

llvm-svn: 277500
2016-08-02 19:17:37 +00:00
Ahmed Bougacha 91bdeb1cc2 [AArch64][GlobalISel] Replace test REQUIRES with lit.local.cfg. NFC.
I forgot the REQUIRES once (see r277486).
Let's prevent it from happening again.

llvm-svn: 277499
2016-08-02 19:04:29 +00:00
Ahmed Bougacha 8a31ed2432 [AArch64] Remove useless 'import re' from CodeGen lit.local.cfg. NFC.
llvm-svn: 277498
2016-08-02 19:04:25 +00:00
Krzysztof Parzyszek 962932c2e2 [Hexagon] Prefer _io over _rr for 64-bit store with constant offset
Identify patterns where the address is aligned to an 8-byte boundary,
but both the base address and the constant offset are both proper
multiples of 4. In such cases, extract Base+4 into a separate instruc-
tion, and use S2_storerd_io, instead of using S4_storerd_rr.

llvm-svn: 277497
2016-08-02 18:50:05 +00:00
Krzysztof Parzyszek 74daece192 [Hexagon] Remove unused option
llvm-svn: 277496
2016-08-02 18:39:32 +00:00
Hubert Tong 3c02e188cf [Concepts] Add TODO and requires-clause placeholder; NFC
llvm-svn: 277495
2016-08-02 18:36:15 +00:00
Krzysztof Parzyszek 3e409e127e [Hexagon] Improvements to address mode checks in TargetLowering
- Implement getOptimalMemOpType.
- Check BaseOffset in isLegalAddressingMode.

llvm-svn: 277494
2016-08-02 18:34:31 +00:00
Chris Bieneman 54e044736f Revert "[Order Files] Remove dtrace predicate"
This reverts commit r277487.

Removing the probe predicate was a red herring. It results in more symbols being placed in the final order file, but they are symbols from outside the clang image.

llvm-svn: 277492
2016-08-02 18:23:56 +00:00
Kirill Bobyrev ef2ee1fd67 [clang-rename] fix Emacs integration script
llvm-svn: 277491
2016-08-02 18:23:08 +00:00
Nirav Dave 0e31955c86 Update Clang Parser test error message to match new parser errors
Update clang tests in light of r277489.

llvm-svn: 277490
2016-08-02 17:58:14 +00:00
Nirav Dave 8601ac11aa [MC] Fix Intel Operand assembly parsing for .set ids
Recommitting after fixing overaggressive fastpath return in parsing.

Fix intel syntax special case identifier operands that refer to a constant
(e.g. .set <ID> n) to be interpreted as immediate not memory in parsing.

Associated commit to fix clang test commited shortly.

Reviewers: rnk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D22585

llvm-svn: 277489
2016-08-02 17:56:03 +00:00
Vitaly Buka ca2f9d1cb2 Updated documentation
Reviewers: kcc, eugenis

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D22992

llvm-svn: 277488
2016-08-02 17:51:48 +00:00
Chris Bieneman f7a024b886 [Order Files] Remove dtrace predicate
Having the dtrace predicate setup to only show probes in clang filters out static initializers executed by dyld, which we do want included in the order files.

llvm-svn: 277487
2016-08-02 17:50:53 +00:00
Ahmed Bougacha 0d020190dd [AArch64][GlobalISel] Add REQUIRES: global-isel to verifier tests.
I thought the directory had a lit.local.cfg, but it doesn't.
I'll add one, but for now, add the REQUIRES line. While there,
move the triple into the IR and add a datalayout.

llvm-svn: 277486
2016-08-02 17:19:35 +00:00
Daniel Berlin de4be65313 MSVC 2013 does not implement C++11 unions properly, so remove the anoymous union for now,
and leave a FIXME.

llvm-svn: 277485
2016-08-02 16:59:51 +00:00
Ahmed Bougacha bfaddd999a [GlobalISel] Set the Selected MF property.
None of GlobalISel requires the property, but this lets us use the
verifier instead of rolling our own "all instructions selected" check.

llvm-svn: 277484
2016-08-02 16:49:25 +00:00
Ahmed Bougacha b14e944cdb [GlobalISel] Verify Selected MF property.
After instruction selection, there should be no pre-isel generic
instructions remaining, nor should generic virtual registers be
used. Verify that.

llvm-svn: 277483
2016-08-02 16:49:22 +00:00
Ahmed Bougacha b109d51865 [GlobalISel] Add Selected MachineFunction property.
Selected: the InstructionSelect pass ran and all pre-isel generic
instructions have been eliminated; i.e., all instructions are now
target-specific or non-pre-isel generic instructions (e.g., COPY).

Since only pre-isel generic instructions can have generic virtual register
operands, this also means that all generic virtual registers have been
constrained to virtual registers (assigned to register classes) and that
all sizes attached to them have been eliminated.

This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.

llvm-svn: 277482
2016-08-02 16:49:19 +00:00
Daniel Berlin c43aa5a5b6 Rewrite the use optimizer to be less memory intensive and 50% faster.
Fixes PR28670

Summary:
Rewrite the use optimizer to be less memory intensive and 50% faster.
Fixes PR28670

The new use optimizer works like a standard SSA renaming pass, storing
all possible versions a MemorySSA use could get in a stack, and just
tracking indexes into the stack.
This uses much less memory than caching N^2 alias query results.
It's also a lot faster.

The current version defers phi node walking to the normal walker.

Reviewers: george.burgess.iv

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23032

llvm-svn: 277480
2016-08-02 16:24:03 +00:00
Artur Pilipenko 2e19f59304 [LVI] NFC. Sink a condition type check from the caller down to getValueFromCondition
This is a preparatory refactoring to support conditions other than ICmpInst.

llvm-svn: 277479
2016-08-02 16:20:48 +00:00
Reid Kleckner b0e4a86e05 [asan] Remove NtWaitForWorkViaWorkerFactory interceptor
Summary:
On Windows 10, this gets called after TLS has been torn down from NTDLL,
and we crash attempting to return fake_tsd. This interceptor isn't
needed after r242948 anyway, so let's remove it. The ASan runtime can
now tolerate unregistered threads calling __asan_handle_no_return.

Reviewers: vitalybuka, etienneb

Subscribers: kubabrecka, llvm-commits

Differential Revision: https://reviews.llvm.org/D23044

llvm-svn: 277478
2016-08-02 16:17:32 +00:00
Ahmed Bougacha 4628e37e7f [GlobalISel] Set and require RegBankSelected MF property.
The InstructionSelect pass assumes that RegBankSelect ran; set the
property on all tests (thereby verifying the test inputs) and require
it in the pass.

llvm-svn: 277477
2016-08-02 16:17:18 +00:00
Ahmed Bougacha 3681c772cf [GlobalISel] Verify RegBankSelected MF property.
RegBankSelected functions shouldn't have any generic virtual
register not assigned to a bank. Verify that.

llvm-svn: 277476
2016-08-02 16:17:15 +00:00
Ahmed Bougacha 2471265508 [GlobalISel] Add RegBankSelected MachineFunction property.
RegBankSelected: the RegBankSelect pass ran and all generic virtual
registers have been assigned to a register bank.

This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.

llvm-svn: 277475
2016-08-02 16:17:10 +00:00
Matthew Simpson 18d8898317 [LV] Generate both scalar and vector integer induction variables
This patch enables the vectorizer to generate both scalar and vector versions
of an integer induction variable for a given loop. Previously, we only
generated a scalar induction variable if we knew all its users were going to be
scalar. Otherwise, we generated a vector induction variable. In the case of a
loop with both scalar and vector users of the induction variable, we would
generate the vector induction variable and extract scalar values from it for
the scalar users. With this patch, we now generate both versions of the
induction variable when there are both scalar and vector users and select which
version to use based on whether the user is scalar or vector.

Differential Revision: https://reviews.llvm.org/D22869

llvm-svn: 277474
2016-08-02 15:25:16 +00:00
Artem Dergachev 7a7004a999 [analyzer] Hotfix for buildbot failure due to unspecified triple in r277449
If a target triple is not specified, the default host triple is used,
which is not good for compiling inline assembler code.

Patch by Raphael Isemann!

llvm-svn: 277473
2016-08-02 15:16:06 +00:00
Ahmed Bougacha 24d0d4d2ec [GlobalISel] Set, require, and verify Legalized MF property.
RegBankSelect and InstructionSelect run after the legalizer and
require a Legalized function: check that all instructions are legal.

Note that this should be in the MachineVerifier, but it can't use the
MachineLegalizer as it's currently in the separate GlobalISel library.
Note that the RegBankSelect verifier checks have the same layering
problem, but we only use inline methods so end up not needing to link
against the GlobalISel library.

llvm-svn: 277472
2016-08-02 15:10:32 +00:00
Ahmed Bougacha ad30db32e6 [AArch64][GlobalISel] Mark basic binops/memops as legal.
We currently use and test these, and select most of them. Mark them
as legal even though we don't go through the full ir->asm flow yet.

This doesn't currently have standalone tests, but the verifier will
soon learn to check that the regbankselect/select tests are legal.

llvm-svn: 277471
2016-08-02 15:10:28 +00:00