Commit Graph

202 Commits

Author SHA1 Message Date
Caroline Tice 920c6c9855 Modify ARM instruction tables to allow for specifying floating point variants.
Add code to emulate VLDM ARM instruction (loading multiplt floating point registers).

Add function declarations for other floating point instructions to emulate.

llvm-svn: 128589
2011-03-31 00:02:51 +00:00
Caroline Tice 55bff33b50 Fill in code for EmulateSTRDImm and EmulateSTRDReg, to emulate the
STRD (immediate) and STRD (register) instructions.

llvm-svn: 128570
2011-03-30 19:02:56 +00:00
Greg Clayton 32e0a7509c Many improvements to the Platform base class and subclasses. The base Platform
class now implements the Host functionality for a lot of things that make 
sense by default so that subclasses can check:

int
PlatformSubclass::Foo ()
{
    if (IsHost())
        return Platform::Foo (); // Let the platform base class do the host specific stuff
    
    // Platform subclass specific code...
    int result = ...
    return result;
}

Added new functions to the platform:

    virtual const char *Platform::GetUserName (uint32_t uid);
    virtual const char *Platform::GetGroupName (uint32_t gid);

The user and group names are cached locally so that remote platforms can avoid
sending packets multiple times to resolve this information.

Added the parent process ID to the ProcessInfo class. 

Added a new ProcessInfoMatch class which helps us to match processes up
and changed the Host layer over to using this new class. The new class allows
us to search for processs:
1 - by name (equal to, starts with, ends with, contains, and regex)
2 - by pid
3 - And further check for parent pid == value, uid == value, gid == value, 
    euid == value, egid == value, arch == value, parent == value.
    
This is all hookup up to the "platform process list" command which required
adding dumping routines to dump process information. If the Host class 
implements the process lookup routines, you can now lists processes on 
your local machine:

machine1.foo.com % lldb
(lldb) platform process list 
PID    PARENT USER       GROUP      EFF USER   EFF GROUP  TRIPLE                   NAME
====== ====== ========== ========== ========== ========== ======================== ============================
99538  1      username   usergroup  username   usergroup  x86_64-apple-darwin      FileMerge
94943  1      username   usergroup  username   usergroup  x86_64-apple-darwin      mdworker
94852  244    username   usergroup  username   usergroup  x86_64-apple-darwin      Safari
94727  244    username   usergroup  username   usergroup  x86_64-apple-darwin      Xcode
92742  92710  username   usergroup  username   usergroup  i386-apple-darwin        debugserver


This of course also works remotely with the lldb-platform:

machine1.foo.com % lldb-platform --listen 1234

machine2.foo.com % lldb
(lldb) platform create remote-macosx
  Platform: remote-macosx
 Connected: no
(lldb) platform connect connect://localhost:1444
  Platform: remote-macosx
    Triple: x86_64-apple-darwin
OS Version: 10.6.7 (10J869)
    Kernel: Darwin Kernel Version 10.7.0: Sat Jan 29 15:17:16 PST 2011; root:xnu-1504.9.37~1/RELEASE_I386
  Hostname: machine1.foo.com
 Connected: yes
(lldb) platform process list 
PID    PARENT USER       GROUP      EFF USER   EFF GROUP  TRIPLE                   NAME
====== ====== ========== ========== ========== ========== ======================== ============================
99556  244    username   usergroup  username   usergroup  x86_64-apple-darwin      trustevaluation
99548  65539  username   usergroup  username   usergroup  x86_64-apple-darwin      lldb
99538  1      username   usergroup  username   usergroup  x86_64-apple-darwin      FileMerge
94943  1      username   usergroup  username   usergroup  x86_64-apple-darwin      mdworker
94852  244    username   usergroup  username   usergroup  x86_64-apple-darwin      Safari

The lldb-platform implements everything with the Host:: layer, so this should
"just work" for linux. I will probably be adding more stuff to the Host layer
for launching processes and attaching to processes so that this support should
eventually just work as well.

Modified the target to be able to be created with an architecture that differs
from the main executable. This is needed for iOS debugging since we can have
an "armv6" binary which can run on an "armv7" machine, so we want to be able
to do:

% lldb
(lldb) platform create remote-ios
(lldb) file --arch armv7 a.out

Where "a.out" is an armv6 executable. The platform then can correctly decide
to open all "armv7" images for all dependent shared libraries.

Modified the disassembly to show the current PC value. Example output:

(lldb) disassemble --frame
a.out`main:
   0x1eb7:  pushl  %ebp
   0x1eb8:  movl   %esp, %ebp
   0x1eba:  pushl  %ebx
   0x1ebb:  subl   $20, %esp
   0x1ebe:  calll  0x1ec3                   ; main + 12 at test.c:18
   0x1ec3:  popl   %ebx
-> 0x1ec4:  calll  0x1f12                   ; getpid
   0x1ec9:  movl   %eax, 4(%esp)
   0x1ecd:  leal   199(%ebx), %eax
   0x1ed3:  movl   %eax, (%esp)
   0x1ed6:  calll  0x1f18                   ; printf
   0x1edb:  leal   213(%ebx), %eax
   0x1ee1:  movl   %eax, (%esp)
   0x1ee4:  calll  0x1f1e                   ; puts
   0x1ee9:  calll  0x1f0c                   ; getchar
   0x1eee:  movl   $20, (%esp)
   0x1ef5:  calll  0x1e6a                   ; sleep_loop at test.c:6
   0x1efa:  movl   $12, %eax
   0x1eff:  addl   $20, %esp
   0x1f02:  popl   %ebx
   0x1f03:  leave
   0x1f04:  ret
   
This can be handy when dealing with the new --line options that was recently
added:

(lldb) disassemble --line
a.out`main + 13 at test.c:19
   18  	{
-> 19  		printf("Process: %i\n\n", getpid());
   20  	    puts("Press any key to continue..."); getchar();
-> 0x1ec4:  calll  0x1f12                   ; getpid
   0x1ec9:  movl   %eax, 4(%esp)
   0x1ecd:  leal   199(%ebx), %eax
   0x1ed3:  movl   %eax, (%esp)
   0x1ed6:  calll  0x1f18                   ; printf

Modified the ModuleList to have a lookup based solely on a UUID. Since the
UUID is typically the MD5 checksum of a binary image, there is no need
to give the path and architecture when searching for a pre-existing
image in an image list.

Now that we support remote debugging a bit better, our lldb_private::Module
needs to be able to track what the original path for file was as the platform
knows it, as well as where the file is locally. The module has the two 
following functions to retrieve both paths:

const FileSpec &Module::GetFileSpec () const;
const FileSpec &Module::GetPlatformFileSpec () const;

llvm-svn: 128563
2011-03-30 18:16:51 +00:00
Caroline Tice 23443245e7 Fill in EmulateLDRDRegister to emulate LDRD (register) instruction.
Remove stubs for functions not-to-be-implemented at the moment.

llvm-svn: 128559
2011-03-30 17:54:52 +00:00
Caroline Tice f0901227e3 Fill in EmulateLDRLImmediate to emulate the LDRD (immediate) ARM instruction.
llvm-svn: 128556
2011-03-30 17:11:45 +00:00
Caroline Tice e746dbf83b Fix typo in previous check-in.
llvm-svn: 128549
2011-03-30 16:05:23 +00:00
Caroline Tice 527637d64a Fill in EmulateSTRImmARM to emulate the STR (immediate,ARM) instruction.
llvm-svn: 128528
2011-03-30 06:03:24 +00:00
Caroline Tice a0e8cd5e89 Fill in EmulateSTRBImmARM to emulate the STRB (immediate, ARM) instruction.
llvm-svn: 128527
2011-03-30 05:40:56 +00:00
Caroline Tice 4cee4bd9f4 Fill in EmulateSTREX to emulate the STREX ARM instruction.
llvm-svn: 128525
2011-03-30 05:15:46 +00:00
Caroline Tice 799e203894 Fill in code in EmulateSUBReg to emulate the SUB (register) ARM instruction.
llvm-svn: 128508
2011-03-29 23:44:20 +00:00
Caroline Tice c5bcda4619 Fill in code in EmulateADDRegShift, to emulate the ADD
(register-shifted register) ARM instruction.

llvm-svn: 128500
2011-03-29 23:03:16 +00:00
Caroline Tice eba8f83479 Add subtraction context.
Add code to emulate SUB (SP minus register) ARM instruction.

Add stubs for other ARM emulation functions that need to be written.

llvm-svn: 128491
2011-03-29 21:24:06 +00:00
Caroline Tice 3f0bfdacc1 Add missing encodings for EmulateMOVRdImm (MOV register) function.
llvm-svn: 128479
2011-03-29 19:53:44 +00:00
Caroline Tice 87c19f61d4 Fix single quote characters throughout the ARM emulation stuff.
Fix bugs in various ARM istruction emulation functions:

EmulateVPUSH
   - Fix context.
   - Fix bug calculating register numbers.

EmulateVPOP
   - Fix context.
   - Fix bug calculating register numbers.

EmulateShiftIMM
   - Fix bug in assert statement.

EmulateLDMDA
   - Fix context.

EmulateLDMDB
   - Fix context.

EmulateLDMIB
   - Fix context.     

EmulateSTM
   - Fix bug calculating lowest_set_bit.     

EmulateSTMDA
   - Fix context.
   - Fix bug calculating lowest_set_bit.

EmulateSTMDB
   - Fix context.
   - Fix bug calculating lowest_set_bit.

EmulateSTMIB
   - FIx context     

EmulateLDRSBImmed
   - Fix test to match correction in corrected manual 

llvm-svn: 128409
2011-03-28 16:10:45 +00:00
Greg Clayton 0ae962735f Made the lldb_private::Opcode struct into a real boy... I mean class.
Modified the Disassembler::Instruction base class to contain an Opcode 
instance so that we can know the bytes for an instruction without needing
to keep the data around.

Modified the DisassemblerLLVM's instruction class to correctly extract the
opcode bytes if all goes well.

llvm-svn: 128248
2011-03-24 23:53:38 +00:00
Greg Clayton e0d378b334 Fixed the LLDB build so that we can have private types, private enums and
public types and public enums. This was done to keep the SWIG stuff from
parsing all sorts of enums and types that weren't needed, and allows us to
abstract our API better.

llvm-svn: 128239
2011-03-24 21:19:54 +00:00
Caroline Tice 9b281e2214 Add missing encodings for EmulateLDRRtRnImm (ARM insn emulation funciton).
llvm-svn: 128229
2011-03-24 19:23:45 +00:00
Caroline Tice 3e1fa1ad09 More fixes for ARM instruction emulation code:
- Remove duplicate write from EmulateLDRRtPCRelative.
  - Add a missing encoding to EmulateADDSPImm.
  - Fix minor problems in Thumb instruction tables.

llvm-svn: 128115
2011-03-22 22:38:28 +00:00
Greg Clayton 7a5388bf75 Split all of the core of LLDB.framework/lldb.so into a
static archive that can be linked against. LLDB.framework/lldb.so
exports a very controlled API. Splitting the API into a static
library allows other tools (debugserver for now) to use the power
of the LLDB debugger core, yet not export it as its API is not
portable or maintainable. The Host layer and many of the other
internal only APIs can now be statically linked against.

Now LLDB.framework/lldb.so links against "liblldb-core.a" instead
of compiling the .o files only for the shared library. This fix
is only for compiling with Xcode as the Makefile based build already
does this.

The Xcode projecdt compiler has been changed to LLVM. Anyone using
Xcode 3 will need to manually change the compiler back to GCC 4.2,
or update to Xcode 4.

llvm-svn: 127963
2011-03-20 04:57:14 +00:00
Caroline Tice 77c13fe304 Fix various small problems with EmulateInstructionARM::EmulateSTRRtSP.
llvm-svn: 127898
2011-03-18 19:41:00 +00:00
Caroline Tice 4c753376cb Make all the codee that attempts to read the PC consistently use
ReadCoreReg (which 'does the right thing', adding to pc when needed);
fixed places in code where extra addition was being passed along.

Fix bug in insn tables.

llvm-svn: 127838
2011-03-17 23:50:16 +00:00
Caroline Tice aaf5ddcf82 Add code to emulate STRH (Register) Arm instruction.
Remove inaccurate comments from EmulateInstruction::Context definition.

Fix contexts in a few arm instruction emulation routines.

llvm-svn: 127770
2011-03-16 22:46:55 +00:00
Caroline Tice fe28f1bff9 Fix various small bugs found in the instruction emulation functions.
llvm-svn: 127712
2011-03-16 00:06:12 +00:00
Greg Clayton e996fd30be LLDB now has "Platform" plug-ins. Platform plug-ins are plug-ins that provide
an interface to a local or remote debugging platform. By default each host OS
that supports LLDB should be registering a "default" platform that will be
used unless a new platform is selected. Platforms are responsible for things
such as:
- getting process information by name or by processs ID
- finding platform files. This is useful for remote debugging where there is 
  an SDK with files that might already or need to be cached for debug access.
- getting a list of platform supported architectures in the exact order they
  should be selected. This helps the native x86 platform on MacOSX select the
  correct x86_64/i386 slice from universal binaries.
- Connect to remote platforms for remote debugging
- Resolving an executable including finding an executable inside platform
  specific bundles (macosx uses .app bundles that contain files) and also
  selecting the appropriate slice of universal files for a given platform.

So by default there is always a local platform, but remote platforms can be
connected to. I will soon be adding a new "platform" command that will support
the following commands:
(lldb) platform connect --name machine1 macosx connect://host:port
Connected to "machine1" platform.
(lldb) platform disconnect macosx

This allows LLDB to be well setup to do remote debugging and also once 
connected process listing and finding for things like:
(lldb) process attach --name x<TAB>

The currently selected platform plug-in can now auto complete any available
processes that start with "x". The responsibilities for the platform plug-in
will soon grow and expand.

llvm-svn: 127286
2011-03-08 22:40:15 +00:00
Caroline Tice 94f87e37c8 Add code to emulate RFE Arm instruction.
Add new instruction context for RFE instruction.

Add several new helper functions to help emulate RFE instruction
(including CurrentModeIsPrivileged, BadMode, and CPSRWriteByInstr).

llvm-svn: 126965
2011-03-03 22:37:46 +00:00
Caroline Tice c8d0d3ae0b Add code to emulate UXTH Arm instruction.
llvm-svn: 126954
2011-03-03 18:48:58 +00:00
Caroline Tice 9c35f321c6 Add code to emulate UXTB Arm instruction.
llvm-svn: 126953
2011-03-03 18:27:17 +00:00
Caroline Tice 8678f2a192 Add code to emulate SXTH Arm instruction.
llvm-svn: 126951
2011-03-03 18:04:49 +00:00
Caroline Tice 67735bf069 Add code to emulate SXTB Arm instruction.
llvm-svn: 126949
2011-03-03 17:42:58 +00:00
Caroline Tice edc103e253 Fix bug where bitwise-AND was being used and it should have been bitwise-OR.
llvm-svn: 126904
2011-03-03 00:07:02 +00:00
Caroline Tice 30f40c6850 Add code to emulate ADD (immediate, Thumb) Arm instruction.
Add addition context to EmulateInstruction contexts.

llvm-svn: 126903
2011-03-02 23:57:02 +00:00
Caroline Tice 1a234ff46f Add code to emulate MUL Arm instruction.
Add new context type & info structure for  mul instruction.

llvm-svn: 126891
2011-03-02 22:43:54 +00:00
Caroline Tice a0d3b67572 Add code to emulate LDRSH (register) Arm instruction.
llvm-svn: 126881
2011-03-02 21:13:44 +00:00
Caroline Tice 1cd4459b21 Add code to emulate LDRSH (literal) Arm instruction.
llvm-svn: 126866
2011-03-02 19:45:34 +00:00
Caroline Tice d3e57ee4fc Add code to emulate LDRSH (immediate) Arm instruction.
llvm-svn: 126807
2011-03-02 00:39:42 +00:00
Caroline Tice 4776fbbd72 Add code to emulate LDRSB (register) Arm instruction.
llvm-svn: 126802
2011-03-01 23:55:59 +00:00
Caroline Tice 4947ffc80d Add code to emulate LDRSB (literal) Arm instruction.
llvm-svn: 126789
2011-03-01 22:25:17 +00:00
Caroline Tice 28c3fcccb2 Add code to emulate LDRSB (immediate) Arm instruction.
llvm-svn: 126783
2011-03-01 21:53:03 +00:00
Caroline Tice 4f0e5f8852 Add code to emulate LDRH (register) Arm instruction.
llvm-svn: 126758
2011-03-01 18:00:42 +00:00
Caroline Tice 6261d240e1 Add code to emulate LDRH (literal) Arm instruction.
llvm-svn: 126709
2011-02-28 23:15:24 +00:00
Caroline Tice adef8fb003 Add code to emulate LDRH (immediate, Thumb) arm instruction.
llvm-svn: 126692
2011-02-28 22:39:58 +00:00
Johnny Chen 699ac0e967 Add emulation for Encoding A1 of A8.6.97 MOV (register).
llvm-svn: 126456
2011-02-25 00:23:25 +00:00
Johnny Chen a517bae73c Fix typos in the opcode entries for branch instructions.
llvm-svn: 126442
2011-02-24 21:54:22 +00:00
Johnny Chen 3c970dc50d Add emulation for BXJ (Branch and Exchange Jazelle), assuming that the attempt to
switch to Jazelle state fails, thus treating BXJ as a BX operation.

llvm-svn: 126423
2011-02-24 21:01:20 +00:00
Johnny Chen bf4afa8796 Add emulation methods for Bitwise Bit Clear (immediate and register) operations.
llvm-svn: 126355
2011-02-24 01:15:17 +00:00
Johnny Chen 132548df62 Add emulation methods for "SUB (immediate, Thumb)" and "SUB (immediate, ARM)" operations.
llvm-svn: 126343
2011-02-23 23:47:56 +00:00
Johnny Chen d88d96cac9 Add emulation for "ADR" operations. Add a ThumbImm8Scaled() convenience function
and rename the original ThumbImmScaled() function to ThumbImm7Scaled().

llvm-svn: 126335
2011-02-23 21:24:25 +00:00
Johnny Chen 5278cd11ba Modify EmulateSUBSPImm() to handle the cases with generic Rd value instead of
Rd == 13.  Add opcode entries for the generic "sub (sp minus immediate)" operations.

llvm-svn: 126293
2011-02-23 01:55:07 +00:00
Johnny Chen 187b0e37c1 Add emulation methods for "SBC (immediate)" and "SBC (register)" operations.
llvm-svn: 126283
2011-02-23 01:01:21 +00:00
Greg Clayton 64195a2c8b Abtracted all mach-o and ELF out of ArchSpec. This patch is a modified form
of Stephen Wilson's idea (thanks for the input Stephen!). What I ended up
doing was:
- Got rid of ArchSpec::CPU (which was a generic CPU enumeration that mimics
  the contents of llvm::Triple::ArchType). We now rely upon the llvm::Triple 
  to give us the machine type from llvm::Triple::ArchType.
- There is a new ArchSpec::Core definition which further qualifies the CPU
  core we are dealing with into a single enumeration. If you need support for
  a new Core and want to debug it in LLDB, it must be added to this list. In
  the future we can allow for dynamic core registration, but for now it is
  hard coded.
- The ArchSpec can now be initialized with a llvm::Triple or with a C string
  that represents the triple (it can just be an arch still like "i386").
- The ArchSpec can still initialize itself with a architecture type -- mach-o
  with cpu type and subtype, or ELF with e_machine + e_flags -- and this will
  then get translated into the internal llvm::Triple::ArchSpec + ArchSpec::Core.
  The mach-o cpu type and subtype can be accessed using the getter functions:
  
  uint32_t
  ArchSpec::GetMachOCPUType () const;

  uint32_t
  ArchSpec::GetMachOCPUSubType () const;
  
  But these functions are just converting out internal llvm::Triple::ArchSpec 
  + ArchSpec::Core back into mach-o. Same goes for ELF.

All code has been updated to deal with the changes.

This should abstract us until later when the llvm::TargetSpec stuff gets
finalized and we can then adopt it.

llvm-svn: 126278
2011-02-23 00:35:02 +00:00
Johnny Chen 673badf292 Renamed macro definition of CPSR_C to be CPSR_C_POS to avoid confusions and subtle bugs.
llvm-svn: 126271
2011-02-23 00:15:56 +00:00
Johnny Chen 7deb7422bc Add emulation methods for "RSC (immediate)" and "RSC (register)" operations.
llvm-svn: 126267
2011-02-23 00:07:09 +00:00
Johnny Chen 447c001048 Add emulation methods for "RSB (immediate)" and "RSB (register)".
Plus add missing break stmts for "case" blocks.

llvm-svn: 126265
2011-02-22 23:42:58 +00:00
Johnny Chen 5f88bcc16a Add two convenience functions: DecodeImmShiftThumb() and DecodeImmShiftARM() to ARMUtils.h.
Use them within EmulateInstructionARM.cpp to save repetitive typing.

llvm-svn: 126247
2011-02-22 21:17:52 +00:00
Johnny Chen 83a4ddd0cb Add "cmp<c>.w <Rn>, #<const>" emulation to EmulateCMPImm() method,
and implement EmulateCMNImm() and EMulateCMNReg() methods.

llvm-svn: 126236
2011-02-22 19:48:22 +00:00
Johnny Chen aebcfc86df Fix the 'variants' field of "CMN (immediate)" Encoding T1 entry, it should be ARMV6T2_ABOVE, not ARMvAll.
llvm-svn: 126234
2011-02-22 19:01:11 +00:00
Johnny Chen 01ceff367a Add ARM encoding entries for "CMN (immediate)" and "CMN (register)" operations.
llvm-svn: 126179
2011-02-22 02:00:12 +00:00
Johnny Chen 5ea119468a Add ARM encoding entries for "CMP (immediate)" and "CMP (register)" operations.
Add ARM/Thumb encoding entries for "CMN (immediate)" and "CMN (register)" operations,
with the EmulateCMNImm()/Reg() methods not implemented yet for now.

llvm-svn: 126178
2011-02-22 01:56:31 +00:00
Johnny Chen c2fa8fafde Add emulation methods for "MVN (immediate)" and "MVN (register)".
llvm-svn: 126172
2011-02-22 01:01:03 +00:00
Johnny Chen e69108a78f Add emulation methods for "EOR (Immediate)", "EOR (register)",
"TEQ (immediate)", and "TEQ (register)" operations.

llvm-svn: 126160
2011-02-21 23:42:44 +00:00
Johnny Chen 28c5882cb5 Add emulation methods for "TST (immediate)" and "TST (register)".
Plus modified EmulateANDImm/Reg to delegate to TSTImm/Reg for Thumb2
32-bit instructions when Rd == '1111' and setflags is true.

llvm-svn: 126144
2011-02-21 21:24:49 +00:00
Johnny Chen ce0dec7597 Make the helper method ReadCoreReg(uint32_t reg, bool *success) more generic
which now handles R0-R12, SP, LR, as well as PC.  And refactored a lot of
calls to ReadRegisterUnsigned() to now funnel through ReadCoreReg(), instead.

llvm-svn: 126010
2011-02-19 01:36:13 +00:00
Caroline Tice 55532be31f Add code to emulate LDRB (register) Arm instruction.
llvm-svn: 125994
2011-02-18 23:52:21 +00:00
Johnny Chen ce4e629fdf Add emulation methods for "ORR (immediate)" and "ORR (register)".
Add Encoding T3 of "MOV (register)" to EmulateMOVRdRm() method and fixed
some bugs in EmulateMOVRdImm() and EmulateMOVRdRm() methods.

llvm-svn: 125992
2011-02-18 23:41:11 +00:00
Caroline Tice 27d1032b60 Add code to emulate LDRB (literal) Arm instruction.
llvm-svn: 125975
2011-02-18 22:24:22 +00:00
Johnny Chen d1fd6963f5 Add emulation methods for "ADC (immediate)" and "ADC (register)".
Plus add a helper method ReadCoreReg(uint32_t regnum, bool *success) to simplify
coding a bit.

llvm-svn: 125961
2011-02-18 21:13:05 +00:00
Caroline Tice 489517c4a4 Add code to emulate LDRB (immediate, Thumb) instruction.
llvm-svn: 125959
2011-02-18 21:06:04 +00:00
Johnny Chen faba5dd4ae Add emulation methods for "AND (immediate)" and "AND (register)".
Plus add macro definitions for APSR_C and APSR_V to simplify code.

llvm-svn: 125947
2011-02-18 19:32:20 +00:00
Caroline Tice a1bf8db478 Add code to emulate LDR (register) Arm instruction.
llvm-svn: 125945
2011-02-18 18:52:37 +00:00
Johnny Chen f401d69c85 Fix typo.
llvm-svn: 125812
2011-02-18 01:26:39 +00:00
Johnny Chen fc9d00beb7 Add emulation of Encoding A1 "A8.6.6 ADD (register)" and "A8.6.5 ADD (immediate, ARM)".
llvm-svn: 125809
2011-02-18 01:22:22 +00:00
Caroline Tice 29c9b64096 Add code to emulate LDR (immediate,ARM) instruction.
llvm-svn: 125808
2011-02-18 00:55:53 +00:00
Johnny Chen ae147cafa9 Finished renamings to make the emulation method names consistent case-wise.
llvm-svn: 125801
2011-02-18 00:07:39 +00:00
Johnny Chen a18ae1ffde Some renamings to make the emulation method names consistent case-wise.
llvm-svn: 125800
2011-02-18 00:02:28 +00:00
Johnny Chen d4926266f3 Removed redundant entry EmulateTBB() (there's an existing one EmulateTB()) and fixed some typos
in section headings.

llvm-svn: 125796
2011-02-17 23:44:53 +00:00
Johnny Chen 2a7e05a3d7 Fix a bug in EmulateTB() (TBB, TBH) where the branch length should be "twice"
the value of the byte/halfword returned from the table.

llvm-svn: 125793
2011-02-17 23:27:44 +00:00
Caroline Tice 16443905f3 Add header declarations for the remaining instructions we need to
emulate, to cover those that can change the PC.

llvm-svn: 125791
2011-02-17 23:09:13 +00:00
Johnny Chen 34dd9ba9c7 Refactoring. Abstracted the set flags operation into its own helper method
WriteFlags() and renamed WriteCoreRegisterWithFlags() to WriteCoreRegOptionalFlags().
Modified the call sites to use the helper methods.

llvm-svn: 125788
2011-02-17 22:37:12 +00:00
Johnny Chen fc5c19dec5 A8.6.6 ADD (register)
Renamed EmulateAddRdnRm() to EmulateAddReg(), and added Encoding T1 to it.
Where Encoding T2 can potentially modify the PC, causing a brnach.

llvm-svn: 125782
2011-02-17 22:03:29 +00:00
Johnny Chen 2789706059 Add EmulateTB() method to emulate "Table Branch Byte" and "Table Branch Halfword"
operations for Thumb2.

llvm-svn: 125767
2011-02-17 19:34:27 +00:00
Caroline Tice 032d2dd576 Add stubs for pseudocode functions "MemA[]" amd "MemU[]", corresponding to aligned
and unaligned memory accesses.  The new stub functions are MemARead, MemAWrite,
MemURead, and MemUWrite.  At the moment these stubs just call ReadMemoryUnsigned or
WriteMemoryUnsigned, but we can fill them out further later if we decide we need
more accurate emulation of the memory system.

Replaced all the direct calls to ReadMemoryUnsigned and WriteMemoryUnsigned in
EmulateInstructionARM.cpp with calls to the appropriate new stub function.

llvm-svn: 125766
2011-02-17 19:20:40 +00:00
Johnny Chen 0f60574fd7 Move Align(val, alignment) utility function to ARMUtils.h.
llvm-svn: 125753
2011-02-17 17:31:08 +00:00
Johnny Chen e19e4fc8dc Add comment for the helper method WriteCoreRegisterWithFlags().
llvm-svn: 125703
2011-02-17 01:49:00 +00:00
Johnny Chen 0c64b5bbb6 Refactoring. Wrap the following pseudocode from the ARM Architecture Reference Manul:
// if d == 15 then         // Can only occur for encoding A1
//     ALUWritePC(result); // setflags is always FALSE here
// else
//     R[d] = result;
//     if setflags then
//         APSR.N = result<31>;
//         APSR.Z = IsZeroBit(result);
//         APSR.C = carry;
//         // APSR.V unchanged

into a helper method WriteCoreRegisterWithFlags, and modified the existing methods
to take advantage of it.

Plus add two emulation methods (declaration only for now) for ORR (immediate) and ORR (register).

llvm-svn: 125701
2011-02-17 01:35:27 +00:00
Johnny Chen 4890c85e0a Add emulation methods for ROR (immediate), ROR (register), and RRX.
Turns out that they can be funneled through the helper methods
EmulateShiftImm()/ EmulateShiftReg() as well.

Modify EmulateShiftImm() to handle SRType_ROR and SRType_RRX.
And fix a typo in the impl of utility Shift_C() in ARMUtils.h.

llvm-svn: 125689
2011-02-16 22:14:44 +00:00
Caroline Tice eaf2e4fdf1 Add code to emulate STRB (Thumb) instruction.
llvm-svn: 125686
2011-02-16 20:22:22 +00:00
Johnny Chen 14571f4b67 Add encoding entries for LSL (immediate and register) and LSR (immediate and register) to
ARM and Thumb opcode tables.

llvm-svn: 125683
2011-02-16 19:27:43 +00:00
Johnny Chen 4b22e7e67a Add tagging for EmulateLDRRtRnImm().
llvm-svn: 125671
2011-02-16 18:35:47 +00:00
Johnny Chen 0f03baa539 Minor comment change.
llvm-svn: 125634
2011-02-16 01:31:20 +00:00
Johnny Chen 22deaa5a1a Add emulation methods for LSL (immediate), LSL (register), LSR (immediate), and LSR (register).
Create two helper methods EmulateShiftImm() and EmulateShiftReg() and have ASR, LSL, and LSR
delegate to the helper methods which take an extra ARM_ShifterType parameter.

The opcodes tables have not been updated yet to reflect these new entries.

llvm-svn: 125633
2011-02-16 01:27:54 +00:00
Caroline Tice 5b5396ba77 Add documentation tags for LDM/STM instruction families.
Add code to emulate STR (register) Arm instruction.

llvm-svn: 125623
2011-02-16 00:33:43 +00:00
Johnny Chen a79703db79 Section heading for EmulateB().
llvm-svn: 125620
2011-02-16 00:17:18 +00:00
Johnny Chen 7484e4e337 Add section headings corresponding to some of the ARM/Thumb emulation methods for better documentation.
llvm-svn: 125618
2011-02-16 00:06:18 +00:00
Johnny Chen 531dbfa5d8 A8.6.14 ASR (register)
Add EmulateASRReg() Encodings T1, T2, and A1 to the opcodes tables.

llvm-svn: 125614
2011-02-15 23:22:46 +00:00
Caroline Tice f199eea579 Add eContextRegisterLoad instruction emulation context.
Add code to emulate STR (Immediate, Thumb) instruction.

llvm-svn: 125610
2011-02-15 22:53:54 +00:00
Greg Clayton 514487e806 Made lldb_private::ArchSpec contain much more than just an architecture. It
now, in addition to cpu type/subtype and architecture flavor, contains:
- byte order (big endian, little endian)
- address size in bytes
- llvm::Triple for true target triple support and for more powerful plug-in
  selection.

llvm-svn: 125602
2011-02-15 21:59:32 +00:00
Johnny Chen f976896b83 Remove the "Register &reg" parameter from the BXWritePC(), LoadWritePC(), and ALUWritePC()
methods of EmulateInstructionARM class.  The context data structure should provide sufficient
information already.

llvm-svn: 125596
2011-02-15 21:08:58 +00:00
Johnny Chen 6f93f63955 Fix wrong mask and encoding for T2 of ASR (immediate).
llvm-svn: 125593
2011-02-15 20:14:02 +00:00
Johnny Chen a4afff97ad A8.6.14 ASR (immediate)
Add EmulateASRImm() Encodings T1, T2, and A1 to the opcodes tables.

llvm-svn: 125592
2011-02-15 20:10:55 +00:00
Caroline Tice 6e12e117d4 Add code to emulate STMIB Arm instruction.
llvm-svn: 125580
2011-02-15 18:42:15 +00:00