991cf47221
Oops. Didn't mean to leave this in.
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llvm-svn: 42626
2007-10-05 01:39:40 +00:00
79e9713b11
If a node that defines a physical register that is expensive to copy. The
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scheduler will try a number of tricks in order to avoid generating the
copies. This may not be possible in case the node produces a chain value
that prevent movement. Try unfolding the load from the node before to allow
it to be moved / cloned.
llvm-svn: 42625
2007-10-05 01:39:18 +00:00
a5e595d23a
If two instructions are both two-address code, favors (schedule closer to
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terminator) the one that has a CopyToReg use. This fixes
2006-05-11-InstrSched.ll with -new-cc-modeling-scheme.
llvm-svn: 42453
2007-09-28 22:32:30 +00:00
f72693f36e
Remove a poor scheduling heuristic.
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llvm-svn: 42443
2007-09-28 19:37:35 +00:00
038dcc5136
Trim some unneeded fields.
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llvm-svn: 42442
2007-09-28 19:24:24 +00:00
e6f92253f5
Avoid inserting a live register more than once.
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llvm-svn: 42410
2007-09-27 18:46:06 +00:00
bde499be60
Boogs.
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llvm-svn: 42388
2007-09-27 07:29:27 +00:00
1ec79b41db
Be smarter about which node to force schedule. Reduce # of duplications + copies; Added statistics.
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llvm-svn: 42387
2007-09-27 07:09:03 +00:00
cfd5f82890
Backtracking only when it won't create a cycle.
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llvm-svn: 42384
2007-09-27 00:25:29 +00:00
8e136a9dc4
- Move getPhysicalRegisterRegClass() from ScheduleDAG to MRegisterInfo.
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- Added ability to emit cross class register copies to the BBRU scheduler.
- More aggressive backtracking.
llvm-svn: 42375
2007-09-26 21:36:17 +00:00
5924bf7d3b
Added major new capabilities to scheduler (only BURR for now) to support physical register dependency. The BURR scheduler can now backtrace and duplicate instructions in order to avoid "expensive / impossible to copy" values (e.g. status flag EFLAGS for x86) from being clobbered.
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llvm-svn: 42284
2007-09-25 01:54:36 +00:00
0effc3a6b8
Use struct SDep instead of std::pair for SUnit pred and succ lists. First step
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in tracking physical register output dependencies.
llvm-svn: 42125
2007-09-19 01:38:40 +00:00
100c8d6c8f
Bug fixes.
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llvm-svn: 41900
2007-09-13 00:06:00 +00:00
54a187ea8b
Minor cleanups to reduce some spurious differences between different
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scheduler implementations.
llvm-svn: 41191
2007-08-20 19:28:38 +00:00
2182f06f2d
Skeleton of post-RA scheduler; doesn't do anything yet.
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Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
llvm-svn: 39816
2007-07-13 17:13:54 +00:00
cf2a51e8db
Remove unused variables.
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llvm-svn: 37816
2007-06-29 21:42:03 +00:00
4c1e6f3804
Remove unnecessary attributions in comments.
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llvm-svn: 37799
2007-06-29 03:42:23 +00:00
5b6f755575
Remove the "special tie breaker" because it resulted in inconsistent
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ordering and thus violated the strict weak ordering requirement of
priority_queue. Uncovered by _GLIBCXX_DEBUG.
llvm-svn: 37794
2007-06-29 02:48:09 +00:00
e3c4419953
std::set is really really terrible. Switch to SmallPtrSet to reduce compile time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec.
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llvm-svn: 37701
2007-06-22 01:35:51 +00:00
e131e3ac02
Fix a typo in a comment.
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llvm-svn: 36485
2007-04-26 19:40:56 +00:00
b9e3db67fb
Estimate a cost using the possible number of scratch registers required and use
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it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.
llvm-svn: 35109
2007-03-14 22:43:40 +00:00
2874855302
Try schedule def + use closer whne Sethi-Ullman numbers are the same.
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e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4
Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2
This creates more short live intervals which work better with the register
allocator.
llvm-svn: 35089
2007-03-13 23:25:11 +00:00
0a30b1f00f
switch the sched unit map over to use a DenseMap instead of std::map. This
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speeds up isel as a whole time by 2.6%.
llvm-svn: 33810
2007-02-03 01:34:13 +00:00
296a83cefb
Fit in 80 columns
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llvm-svn: 33745
2007-02-01 04:55:59 +00:00
6730f03370
Naming consistency.
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llvm-svn: 33026
2007-01-08 23:55:53 +00:00
961bbd393b
Fix for PR1075: bottom-up register-reduction scheduling actually increases register pressure.
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- Fixed bugs in sethi-ullman number computation and priority queue comparison
functions.
- Separate code that handles priority computation special cases from SU number computation.
llvm-svn: 33025
2007-01-08 23:50:38 +00:00
22e978a736
Removing even more <iostream> includes.
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llvm-svn: 32320
2006-12-07 20:04:42 +00:00
67fc141db5
Match TargetInstrInfo changes.
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llvm-svn: 32098
2006-12-01 21:52:58 +00:00
f24d15f969
Remove dead code; added a missing null ptr check.
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llvm-svn: 31478
2006-11-06 21:33:46 +00:00
fd2c5dd806
Changes to use operand constraints to process two-address instructions.
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llvm-svn: 31453
2006-11-04 09:44:31 +00:00
cd7b92251d
silence warning
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llvm-svn: 31397
2006-11-03 01:28:29 +00:00
de46e48420
For PR786:
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Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
llvm-svn: 31380
2006-11-02 20:25:50 +00:00
1359196c4e
Clean up.
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llvm-svn: 31359
2006-11-01 22:39:30 +00:00
47218fab42
CopyFromReg starts a live range so its use should not be considered a floater.
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llvm-svn: 31356
2006-11-01 22:17:06 +00:00
47fbeda5ce
Debug tweak.
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llvm-svn: 30959
2006-10-14 08:34:06 +00:00
3d27be1333
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
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llvm-svn: 29911
2006-08-27 12:54:02 +00:00
d86418ab20
switch the SUnit pred/succ sets from being std::sets to being smallvectors.
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This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%). More
significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms,
a 33% speedup.
llvm-svn: 29743
2006-08-17 00:09:56 +00:00
29e635d3c9
Final polish on machine pass registries.
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llvm-svn: 29471
2006-08-02 12:30:23 +00:00
03593f72db
1. Change use of "Cache" to "Default".
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2. Added argument to instruction scheduler creators so the creators can do
special things.
3. Repaired target hazard code.
4. Misc.
More to follow.
llvm-svn: 29450
2006-08-01 18:29:48 +00:00
95eda5b1f3
Introducing plugable register allocators and instruction schedulers.
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llvm-svn: 29434
2006-08-01 14:21:23 +00:00
4e153f1b91
Use an enumeration to eliminate data relocations.
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llvm-svn: 29249
2006-07-21 20:57:35 +00:00
996795b0dd
Use hidden visibility to make symbols in an anonymous namespace get
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dropped. This shrinks libllvmgcc.dylib another 67K
llvm-svn: 28975
2006-06-28 23:17:24 +00:00
e097e6f7c7
Shave another 27K off libllvmgcc.dylib with visibility hidden
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llvm-svn: 28973
2006-06-28 22:17:39 +00:00
d12c97d23a
Make sure the register pressure reduction schedulers work for non-uniform
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latency targets, e.g. PPC32.
llvm-svn: 28561
2006-05-30 18:05:39 +00:00
009f5f55f7
Turn on -sched-commute-nodes by default.
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llvm-svn: 28465
2006-05-25 08:37:31 +00:00
99f2f79e2f
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
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llvm-svn: 28279
2006-05-13 08:22:24 +00:00
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
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TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
afed73eebe
Add capability to scheduler to commute nodes for profit.
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If a two-address code whose first operand has uses below, it should be commuted
when possible.
llvm-svn: 28230
2006-05-12 01:58:24 +00:00
d38c22bdd3
Refactor scheduler code. Move register-reduction list scheduler to a
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separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
llvm-svn: 28226
2006-05-11 23:55:42 +00:00
Evan Cheng