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192 Commits

Author SHA1 Message Date
Anton Korobeynikov c6d945b11a The names of VFP variants of half-to-float conversion instructions were 
reversed. This leads to wrong codegen for float-to-half conversion
intrinsics which are used to support storage-only fp16 type.
NEON variants of same instructions are fine.

llvm-svn: 161907
 2012-08-14 23:36:01 +00:00
Richard Barton 1dc44dcedd Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time! 
llvm-svn: 159989
 2012-07-10 12:51:09 +00:00
Chad Rosier aeed158f75 Revert r159938 (and r159945) to appease the buildbots. 
llvm-svn: 159960
 2012-07-09 20:43:34 +00:00
Richard Barton c9e1c94fae Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) 
llvm-svn: 159938
 2012-07-09 16:41:33 +00:00
Lang Hames 90b2a4cbad Add a missing llvm.fma -> VFNMS pattern to the ARM backend. 
llvm-svn: 158902
 2012-06-21 06:10:00 +00:00
Lang Hames ea001225c1 Fix the order of the operands in the llvm.fma intrinsic patterns for ARM, 
<rdar://problem/11325085>.

llvm-svn: 155724
 2012-04-27 18:51:24 +00:00
Jim Grosbach 671ad2a572 Tidy up. 80 columns, whitespace, et. al. 
llvm-svn: 155399
 2012-04-23 22:04:10 +00:00
Jim Grosbach 9cc324d31a ARM some VFP tblgen'erated two-operand aliases. 
llvm-svn: 155178
 2012-04-20 00:15:00 +00:00
Evan Cheng 5efc442290 Add more fused mul+add/sub patterns. rdar://10139676 
llvm-svn: 154484
 2012-04-11 06:59:47 +00:00
Evan Cheng 48346c1cd9 Clean up ARM fused multiply + add/sub support some more: rename some isel 
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?

rdar://10139676

llvm-svn: 154480
 2012-04-11 05:33:07 +00:00
Evan Cheng 67a09fc397 Match (fneg (fma) to vfnma. rdar://10139676 
llvm-svn: 154469
 2012-04-11 01:21:25 +00:00
Evan Cheng d0007f3c83 Handle llvm.fma.* intrinsics. rdar://10914096 
llvm-svn: 154439
 2012-04-10 21:40:28 +00:00
Jim Grosbach db7db7d3a3 ARM divided syntax fmrx/fmxr mnemonics. 
llvm-svn: 152946
 2012-03-16 21:06:13 +00:00
Jim Grosbach 24d90e2ddc ARM vmrs system registers mvfr0 and mvfr1 handling. 
rdar://11058464

llvm-svn: 152881
 2012-03-16 00:27:18 +00:00
Jim Grosbach d28888dd77 ARM case-insensitive checking for APSR_nzcv. 
rdar://11056591

llvm-svn: 152846
 2012-03-15 21:34:14 +00:00
Jim Grosbach d74560b170 ARM aliases for pre-unified syntax fcmpz[sd] mnemonics. 
rdar://11056647

llvm-svn: 152834
 2012-03-15 20:48:18 +00:00
Kristof Beyls 327d2f9da5 Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton. 
llvm-svn: 152814
 2012-03-15 17:50:29 +00:00
Lang Hames 718cfbe05a Split fpscr into two registers: FPSCR and FPSCR_NZCV. 
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.

llvm-svn: 152076
 2012-03-06 00:19:55 +00:00
Jim Grosbach 8dc347fc27 ARM vpush/vpop assembler mnemonics accept an optional size suffix. 
rdar://10988114

llvm-svn: 152068
 2012-03-05 23:16:31 +00:00
Sebastian Pop 957a6583f1 updated patch for the ARM fused multiply add/sub 
In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.

Patch by Ana Pazos <apazos@codeaurora.org>

llvm-svn: 152036
 2012-03-05 17:39:52 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Anton Korobeynikov 5482b9f535 Add fused multiple+add instructions from VFPv4. 
Patch by Ana Pazos!

llvm-svn: 148658
 2012-01-22 12:07:33 +00:00
Jim Grosbach ea2319112f ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). 
rdar://10558523

llvm-svn: 147189
 2011-12-22 22:19:05 +00:00
Jim Grosbach b65dd04923 Remove some bogus comments. 
llvm-svn: 147169
 2011-12-22 19:45:01 +00:00
Jim Grosbach 489ed5929e ARM pre-UAL aliases. fcmp[sd]. 
llvm-svn: 147158
 2011-12-22 19:20:45 +00:00
Jim Grosbach 7869d8c01e ARM VFP optional data type on VMOV GPR<-->SPR. 
llvm-svn: 147104
 2011-12-21 23:24:15 +00:00
Jim Grosbach e16acacc3a ARM VFP pre-UAL mnemonic aliases for fmul[sd]. 
llvm-svn: 146892
 2011-12-19 19:43:50 +00:00
Jim Grosbach 92a939ae73 ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd]. 
llvm-svn: 146887
 2011-12-19 19:02:41 +00:00
Jim Grosbach 4b0844e191 ARM NEON two-operand aliases for VQDMULH. 
llvm-svn: 146514
 2011-12-13 20:40:37 +00:00
Jim Grosbach 2a2348e6c2 ARM add some more pre-UAL VFP mnemonics for convenience when porting old code. 
llvm-svn: 146508
 2011-12-13 20:13:48 +00:00
Jim Grosbach 9227f39c53 ARM add more 'gas' compatibility aliases for NEON instructions. 
llvm-svn: 146507
 2011-12-13 20:08:32 +00:00
Jim Grosbach 54337b8617 ARM add some more pre-UAL VFP mnemonics for convenience when porting old code. 
llvm-svn: 146300
 2011-12-10 00:01:02 +00:00
Jim Grosbach 8be2f6577e ARM add some pre-UAL VFP mnemonics for convenience when porting old code. 
llvm-svn: 146296
 2011-12-09 23:34:09 +00:00
Jim Grosbach 8cc83fa1b7 ARM convenience aliases for VSQRT. 
llvm-svn: 146201
 2011-12-08 22:51:25 +00:00
Jim Grosbach 9a6ba3c94e ARM VFP support 'fmrs/fmsr' aliases for 'vldr' 
llvm-svn: 146116
 2011-12-08 00:52:55 +00:00
Jim Grosbach 086d013e56 ARM VFP support 'flds/fldd' aliases for 'vldr' 
llvm-svn: 146115
 2011-12-08 00:49:29 +00:00
Jim Grosbach 2cf294a213 ARM tidy up and remove no longer needed InstAlias definitions. 
The TokenAlias handling of data type suffices renders these unnecessary.

llvm-svn: 146010
 2011-12-07 01:50:36 +00:00
Jim Grosbach a01033709f ARM VFP assembly parsing for VADD and VSUB two-operand forms. 
llvm-svn: 144710
 2011-11-15 22:15:10 +00:00
Jim Grosbach 84f0ba5747 ARM size suffix on VFP single-precision 'vmov' is optional. 
rdar://10435114

llvm-svn: 144698
 2011-11-15 21:18:35 +00:00
Jim Grosbach 5803f6d5a2 ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

llvm-svn: 144691
 2011-11-15 20:29:42 +00:00
Jim Grosbach c5b1bc561e ARM assembly parsing for two-operand form of 'mul' instruction. 
rdar://10449856.

llvm-svn: 144689
 2011-11-15 20:14:51 +00:00
Jim Grosbach 3e2c6f380c ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
 2011-11-14 23:03:21 +00:00
Jim Grosbach 7996b15724 ARM assembly parsing type suffix options for VLDR/VSTR. 
rdar://10435076

llvm-svn: 144575
 2011-11-14 22:28:39 +00:00
Jim Grosbach 609d113874 ARM optional size suffix for VLDR/VSTR syntax. 
llvm-svn: 144427
 2011-11-11 23:34:43 +00:00
Jim Grosbach e7fbce7acb ARM assembly parsing and encoding for VMOV immediate. 
llvm-svn: 141046
 2011-10-03 23:38:36 +00:00
Jim Grosbach 4ab23b5273 ARM assembly parsing and encoding for VMRS/FMSTAT. 
llvm-svn: 141025
 2011-10-03 21:12:43 +00:00
Jim Grosbach efc761a1eb ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
 2011-09-30 00:50:06 +00:00
Owen Anderson 3e0aa03fe9 Add missing encoding information for some of the GPR<->FP register moves. 
llvm-svn: 138780
 2011-08-29 23:15:25 +00:00
Owen Anderson 061738a680 Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing. 
llvm-svn: 138273
 2011-08-22 21:34:00 +00:00
Owen Anderson df698b032c Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. 
llvm-svn: 138269
 2011-08-22 20:27:12 +00:00