Commit Graph

61580 Commits

Author SHA1 Message Date
David Majnemer 29130c5e8d IndVarSimplify: check if loop invariant expansion can trap
IndVarSimplify is willing to move divide instructions outside of their
loop bodies if they are invariant of the loop.  However, it may not be
safe to expand them if we do not know if they can trap.

Instead, check to see if it is not safe to expand the instruction and
skip the expansion.

This fixes PR16041.

Testcase by Rafael Ávila de Espíndola.

llvm-svn: 183239
2013-06-04 17:51:58 +00:00
David Majnemer 452f1f97bd ARM: Fix crash in ARM backend inside of ARMConstantIslandPass
The ARM backend did not expect LDRBi12 to hold a constant pool operand.
Allow for LLVM to deal with the instruction similar to how it deals with
LDRi12.

This fixes PR16215.

llvm-svn: 183238
2013-06-04 17:46:15 +00:00
Vincent Lejeune 276ceb8d5f R600: Swizzle texture/export instructions
llvm-svn: 183229
2013-06-04 15:04:53 +00:00
Rafael Espindola a5e536ab0e Second part of pr16069
The problem this time seems to be a thinko. We were assuming that in the CFG

A
| \
|  B
| /
C

speculating the basic block B would cause only the phi value for the B->C edge
to be speculated. That is not true, the phi's are semantically in the edges, so
if the A->B->C path is taken, any code needed for A->C is not executed and we
have to consider it too when deciding to speculate B.

llvm-svn: 183226
2013-06-04 14:11:59 +00:00
Hans Wennborg 5cf30be6e4 Typo: s/caes/cases/ in SimplifyCFG
llvm-svn: 183219
2013-06-04 11:22:30 +00:00
Benjamin Kramer 7910e6cb0e Preserve const correctness.
GCC complains about casting away const.

llvm-svn: 183216
2013-06-04 09:09:15 +00:00
Vladimir Medic ea381916b0 Test commit for user vmedic, to verify commit access. One line of comment is added to MipsAsmParser.cpp.
llvm-svn: 183215
2013-06-04 08:28:53 +00:00
Aaron Ballman 19978553d4 Silencing an MSVC warning about mixing bool and unsigned int.
llvm-svn: 183176
2013-06-04 01:03:03 +00:00
Aaron Ballman d07f55185c Silencing an MSVC warning about */ being found outside of a comment.
llvm-svn: 183175
2013-06-04 01:01:56 +00:00
Shuxin Yang 8b8fd2171c Fix a defect in code-layout pass, improving Benchmarks/Olden/em3d/em3d by about 30%
(4.58s vs 3.2s on an oldish Mac Tower). 

  The corresponding src is excerpted bellow. The lopp accounts for about 90% of execution time.
  --------------------
    cat -n test-suite/MultiSource/Benchmarks/Olden/em3d/make_graph.c
     90 
     91         for (k=0; k<j; k++)
     92           if (other_node == cur_node->to_nodes[k]) break;

  The defective layout is sketched bellow, where the two branches need to swap.
  ------------------------------------------------------------------------
      L:
         ...
      if (cond) goto out-of-loop
      goto L

  While this code sequence is defective, I don't understand why it incurs 1/3 of 
execution time. CPU-event-profiling indicates the poor laoyout dose not increase
in br-misprediction; it dosen't increase stall cycle at all, and it dosen't 
prevent the CPU detect the loop (i.e. Loop-Stream-Detector seems to be working fine
as well)... 

   The root cause of the problem is that the layout pass calls AnalyzeBranch() 
with basic-block which is not updated to reflect its current layout.

rdar://13966341

llvm-svn: 183174
2013-06-04 01:00:57 +00:00
Nick Lewycky 688d668e5c Delete dead safety check.
llvm-svn: 183167
2013-06-03 23:15:20 +00:00
David Majnemer c82f27af2a SimplifyCFG: Do not transform PHI to select if doing so would be unsafe
PR16069 is an interesting case where an incoming value to a PHI is a
trap value while also being a 'ConstantExpr'.

We do not consider this case when performing the 'HoistThenElseCodeToIf'
optimization.

Instead, make our modifications more conservative if we detect that we
cannot transform the PHI to a select.

llvm-svn: 183152
2013-06-03 20:43:12 +00:00
David Majnemer 8e7dd2f628 SimplifyCFG: Small cleanup, use ICmpInst::isEquality()
llvm-svn: 183151
2013-06-03 20:39:50 +00:00
Rafael Espindola a61f1e9708 Update RuntimeDyldELF::findOPDEntrySection the new relocation iterators.
This was missing from r182908. I didn't noticed it at the time because the MCJIT tests were
disabled when building with cmake on ppc64 (which I fixed in r183143).

llvm-svn: 183147
2013-06-03 19:37:34 +00:00
Tom Stellard 94593ee8c3 R600/SI: Add support for work item and work group intrinsics
llvm-svn: 183138
2013-06-03 17:40:18 +00:00
Tom Stellard ed882c2f1b R600/SI: Add a calling convention for compute shaders
llvm-svn: 183137
2013-06-03 17:40:11 +00:00
Tom Stellard 046039e81b R600/SI: Custom lower i64 sign_extend
llvm-svn: 183136
2013-06-03 17:40:03 +00:00
Tom Stellard 0518ff89ba R600/SI: Adjust some instructions' out register class after ISel
This is necessary to avoid generating VGPR to SGPR copies in some
cases.

llvm-svn: 183135
2013-06-03 17:39:58 +00:00
Tom Stellard bad1f59212 R600/SI: Handle REG_SEQUENCE in fitsRegClass()
llvm-svn: 183134
2013-06-03 17:39:54 +00:00
Tom Stellard b5a97004fb R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands()
llvm-svn: 183133
2013-06-03 17:39:50 +00:00
Tom Stellard 2183b70523 R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()
The CopyToReg nodes will sometimes try to copy a value from a VGPR to an
SGPR.  This kind of copy is not possible, so we need to detect
VGPR->SGPR copies and do something else.  The current strategy is to
replace these copies with VGPR->VGPR copies and hope that all the users
of CopyToReg can accept VGPRs as arguments.

llvm-svn: 183132
2013-06-03 17:39:46 +00:00
Tom Stellard 07a10a3d3f R600/SI: Add support for global loads
llvm-svn: 183131
2013-06-03 17:39:43 +00:00
Tom Stellard 556d9aa841 R600/SI: Rework MUBUF store instructions
The lowering of stores is now mostly handled in the tablegen files.  No
more BUFFER_STORE nodes I generated during legalization.

llvm-svn: 183130
2013-06-03 17:39:37 +00:00
Vincent Lejeune 91a942b93e R600: 3 op instructions have no write bit but the result are store in PV
llvm-svn: 183111
2013-06-03 15:56:12 +00:00
Vincent Lejeune eabf83e0a2 R600: CALL_FS consumes a stack size entry
llvm-svn: 183108
2013-06-03 15:44:42 +00:00
Vincent Lejeune f83df1f1cb R600: use capital letter for PV channel
llvm-svn: 183107
2013-06-03 15:44:35 +00:00
Vincent Lejeune a09873dda7 R600: Constraints input regs of interp_xy,_zw
llvm-svn: 183106
2013-06-03 15:44:16 +00:00
Kostya Serebryany 9e62b301e6 [asan] ASan Linux MIPS32 support (llvm part), patch by Jyun-Yan Y
llvm-svn: 183104
2013-06-03 14:46:56 +00:00
Ahmed Bougacha 05d53a018a X86: sub_xmm registers are 128 bits wide.
llvm-svn: 183103
2013-06-03 14:42:40 +00:00
Manuel Klimek d0cf5b2de3 Introduce needsCleanup() for APFloat and APInt.
This is needed in clang so one can check if the object needs the
destructor called after its memory was freed. This is useful when
creating many APInt/APFloat objects with placement new, where the
overhead of tracking the pointers for cleanup is significant.

llvm-svn: 183100
2013-06-03 13:03:05 +00:00
Venkatraman Govindaraju f80d72f149 Sparc: Add support for indirect branch and blockaddress in Sparc backend.
llvm-svn: 183094
2013-06-03 05:58:33 +00:00
Rui Ueyama f4d0a8c13f [Object/COFF] Fix Windows .lib name handling.
llvm-svn: 183091
2013-06-03 00:27:03 +00:00
Venkatraman Govindaraju 774fe2e29a Sparc: When storing 0, use %g0 directly in the store instruction instead of
using two instructions (sethi and store).

llvm-svn: 183090
2013-06-03 00:21:54 +00:00
Venkatraman Govindaraju 0bbe1b210e Sparc: Combine add/or/sethi instruction with restore if possible.
llvm-svn: 183088
2013-06-02 21:48:17 +00:00
Venkatraman Govindaraju 3e8c7d98be Sparc: Perform leaf procedure optimization by default
llvm-svn: 183083
2013-06-02 02:24:27 +00:00
Nick Lewycky 3f715e260a When determining the new index for an insertelement, we may not assume that an
index greater than the size of the vector is invalid. The shuffle may be
shrinking the size of the vector. Fixes a crash!

Also drop the maximum recursion depth of the safety check for this
optimization to five.

llvm-svn: 183080
2013-06-01 20:51:31 +00:00
Venkatraman Govindaraju 28e2cd0e7e Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions.
llvm-svn: 183079
2013-06-01 20:42:48 +00:00
David Majnemer 91142c485e SimplifyCFG: Fix typo in comment for ComputeSpeculationCost
llvm-svn: 183078
2013-06-01 19:43:23 +00:00
Benjamin Kramer 7c275640e7 Move getRealLinkageName to a common place and remove all the duplicates of it.
Also simplify code a bit while there. No functionality change.

llvm-svn: 183076
2013-06-01 17:51:14 +00:00
Benjamin Kramer 320682fef8 Move object construction into [] so the temporary can be moved.
No functionality change.

llvm-svn: 183075
2013-06-01 17:51:03 +00:00
Benjamin Kramer b565f89929 APInt: Simplify code. No functionality change.
llvm-svn: 183073
2013-06-01 11:26:39 +00:00
Benjamin Kramer 6bef24f3d7 APFloat: Use isDenormal instead of hand-rolled code to check for denormals.
llvm-svn: 183072
2013-06-01 11:26:33 +00:00
Tim Northover 339bf154cc Revert r183069: "TMP: LEA64_32r fixing"
Very sorry, it was committed from the wrong branch by mistake.

llvm-svn: 183070
2013-06-01 10:23:46 +00:00
Tim Northover 57954f04b3 TMP: LEA64_32r fixing
llvm-svn: 183069
2013-06-01 10:21:54 +00:00
Tim Northover 3a1fd4c0ac X86: change MOV64ri64i32 into MOV32ri64
The MOV64ri64i32 instruction required hacky MCInst lowering because it
was allocated as setting a GR64, but the eventual instruction ("movl")
only set a GR32. This converts it into a so-called "MOV32ri64" which
still accepts a (appropriate) 64-bit immediate but defines a GR32.
This is then converted to the full GR64 by a SUBREG_TO_REG operation,
thus keeping everyone happy.

This fixes a typo in the opcode field of the original patch, which
should make the legact JIT work again (& adds test for that problem).

llvm-svn: 183068
2013-06-01 09:55:14 +00:00
Venkatraman Govindaraju 3521dcdcc4 [Sparc] Generate correct code for leaf functions with stack objects
llvm-svn: 183067
2013-06-01 04:51:18 +00:00
Ahmed Bougacha b1a4d9da3b Make SubRegIndex size mandatory, following r183020.
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.

llvm-svn: 183061
2013-05-31 23:45:26 +00:00
Andrew Trick ee9143acf5 Prevent loop-unroll from making assumptions about undefined behavior.
Fixes rdar:14036816, PR16130.

There is an opportunity to compute precise trip counts for 'or'
expressions and multi-exit loops.
rdar:14038809: Optimize trip count computation for multi-exit loops.

To do this we need to record the fact that ExitLimit assumes NSW. When
it does not we can safely assume that the loop trip count is the
minimum ExitLimt across all subexpressions and loop exits.

llvm-svn: 183060
2013-05-31 23:34:46 +00:00
Eric Christopher e1e57e5ebd Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as it
seems to have caused PR16192 and other JIT related failures.

llvm-svn: 183059
2013-05-31 23:30:45 +00:00
Eric Christopher 65ac02ad78 Const-ify some printing and dumping code for DIEValues.
llvm-svn: 183057
2013-05-31 22:50:40 +00:00