Eric Christopher
a98cd22d96
Let the immediate leaf pattern take transforms and switch the signed
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immediate patterns in arm to using the pattern.
Handles rdar://9299434
llvm-svn: 130386
2011-04-28 05:49:04 +00:00
Johnny Chen
57c892860e
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
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print out ldr, not ldr.n.
rdar://problem/9267772
llvm-svn: 130008
2011-04-22 19:12:43 +00:00
Chris Lattner
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
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Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Evan Cheng
44887f9c7e
Follow up on r127913. Fix Thumb revsh isel. rdar://9286766
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llvm-svn: 129548
2011-04-14 23:27:44 +00:00
Johnny Chen
dc8bf9ec08
Thumb disassembler was erroneously rejecting "blx sp" instruction.
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rdar://problem/9267838
llvm-svn: 129320
2011-04-11 23:33:30 +00:00
Bruno Cardoso Lopes
f922b20922
Change MRC and MRC2 instructions to model the output register properly
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llvm-svn: 128085
2011-03-22 15:06:24 +00:00
Bruno Cardoso Lopes
90d1dfe4c6
Fix encoding and add parsing support for the arm/thumb CPS instruction:
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- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
llvm-svn: 125489
2011-02-14 13:09:44 +00:00
Bruno Cardoso Lopes
d8f9b37f31
Add cdp/cdp2 instructions for thumb/thumb2
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llvm-svn: 123929
2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes
cf99dc7eb9
Add mcr* and mr*c support to thumb targets
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llvm-svn: 123917
2011-01-20 16:35:57 +00:00
Chris Lattner
2a0a3b43d7
Flag -> Glue, the ongoing saga
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llvm-svn: 122513
2010-12-23 18:28:41 +00:00
Bill Wendling
cdcc4fc048
Fix a copy-pasto. When the tBR_JTr instruction was converted to using the
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tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>
llvm-svn: 122303
2010-12-21 01:57:15 +00:00
Jim Grosbach
b5743b9d76
Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
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llvm-svn: 121990
2010-12-16 19:11:16 +00:00
Bill Wendling
f5b17c32d2
Add encodings for Thumb1 Spill and Restore pseudos.
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llvm-svn: 121929
2010-12-16 00:38:41 +00:00
Jim Grosbach
bfef309d11
Thumb1 had two patterns for the same load-from-constant-pool instruction.
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Canonicalize on tLDRpci and remove tLDRcp.
llvm-svn: 121920
2010-12-15 23:52:36 +00:00
Bill Wendling
6217ecd634
Whitespace cleanups.
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llvm-svn: 121914
2010-12-15 23:31:24 +00:00
Bill Wendling
1171e9e81d
Add some missing patterns now that tLDRB and tLDRH are split into reg and
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immediate versions.
llvm-svn: 121819
2010-12-15 00:58:57 +00:00
Bill Wendling
5ab38b59e6
Comments and cleaning.
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llvm-svn: 121809
2010-12-14 23:42:48 +00:00
Jim Grosbach
509dc2a700
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
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llvm-svn: 121798
2010-12-14 22:28:03 +00:00
Bill Wendling
ce4f87b3ba
Multiclassify the LDR/STR encoding patterns. The only functionality difference
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is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
llvm-svn: 121794
2010-12-14 22:10:49 +00:00
Bill Wendling
6dd0c07622
Use the integer scheduling intrinsic for integer loads and stores.
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llvm-svn: 121765
2010-12-14 12:33:05 +00:00
Bill Wendling
092a7bdf9f
The tLDR et al instructions were emitting either a reg/reg or reg/imm
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instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
llvm-svn: 121747
2010-12-14 03:36:38 +00:00
Owen Anderson
b0fa127f60
Fix encoding of Thumb1 LDRB and STRB.
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llvm-svn: 121581
2010-12-10 22:11:13 +00:00
Jim Grosbach
e119da1146
Thumb unconditional branch binary encoding. rdar://8754994
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llvm-svn: 121496
2010-12-10 18:21:33 +00:00
Jim Grosbach
78485ad65e
Thumb conditional branch binary encodings. rdar://8745367
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llvm-svn: 121493
2010-12-10 17:13:40 +00:00
Bill Wendling
0c4838bab7
Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the
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t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>
llvm-svn: 121417
2010-12-09 21:49:07 +00:00
Jim Grosbach
62b68112da
Rename the encoder method for t_cbtarget to match.
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llvm-svn: 121399
2010-12-09 19:04:53 +00:00
Jim Grosbach
529c7e8d1f
Thumb needs a few different encoding schemes for branch targets. Rename
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t_brtarget to be more specific.
llvm-svn: 121398
2010-12-09 19:01:46 +00:00
Bill Wendling
3392bfc8f3
The BLX instruction is encoded differently than the BL, because why not? In
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particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
llvm-svn: 121336
2010-12-09 00:39:08 +00:00
Bill Wendling
a7d6aa902a
Support the "target" encodings for the CB[N]Z instructions.
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llvm-svn: 121308
2010-12-08 23:01:43 +00:00
Bill Wendling
8a6449c46e
Add support for loading from a constant pool.
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llvm-svn: 121226
2010-12-08 01:57:09 +00:00
Jim Grosbach
49bcd6ff85
Binary encoding for ARM tLDRspi and tSTRspi.
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llvm-svn: 121186
2010-12-07 21:50:47 +00:00
Jim Grosbach
327cf8ee5f
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
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possible. They were duplicates for everything exception the source pattern
before.
llvm-svn: 121179
2010-12-07 20:41:06 +00:00
Jim Grosbach
6e517d658e
Encode the literal field for tCMPzi instruction.
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llvm-svn: 121153
2010-12-07 17:48:24 +00:00
Jim Grosbach
9e1994698d
Add fixup for Thumb1 BL/BLX instructions.
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llvm-svn: 121072
2010-12-06 23:57:07 +00:00
Jim Grosbach
ce18d7ebb5
Encode condition code for Thumb1 conditional branch instruction.
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llvm-svn: 120865
2010-12-04 00:20:40 +00:00
Bill Wendling
127d7485f1
Use correct variable names to match the patterns.
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llvm-svn: 120857
2010-12-03 23:44:24 +00:00
Jim Grosbach
a09cbbeef5
Match pattern operand names to expected encoding field names. This corrects the
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operand encoding ordering of the instruction.
llvm-svn: 120852
2010-12-03 23:21:25 +00:00
Jim Grosbach
e4fee20498
Remove incorrect BL target encoding (it's similar to, but not the same as the
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ARM instruction). Add encoding of bits 13 and 11.
llvm-svn: 120849
2010-12-03 22:33:42 +00:00
Jim Grosbach
f799579ddd
No need to declare EncoderMethod property anymore; just assign to it.
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llvm-svn: 120831
2010-12-03 19:31:00 +00:00
Jim Grosbach
6423c29e14
Add FIXMEs.
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llvm-svn: 120824
2010-12-03 18:37:17 +00:00
Bill Wendling
36110d5d1a
Don't overwrite the opcode passed into the T1Special pattern.
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llvm-svn: 120782
2010-12-03 02:02:58 +00:00
Bill Wendling
4d8ff86b9e
Add Thumb encoding for some more instructions.
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llvm-svn: 120780
2010-12-03 01:55:47 +00:00
Bill Wendling
9c25894995
Formatting. It's all the rage!
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llvm-svn: 120533
2010-12-01 02:36:55 +00:00
Bill Wendling
8ed14ae48a
More refactoring. This time the T1pI pattern.
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llvm-svn: 120532
2010-12-01 02:28:08 +00:00
Bill Wendling
c25545a1a7
s/T1pIEncode/T1pILdStEncode/g
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s/T1pIEncodeImm/T1pILdStEncodeImm/g
llvm-svn: 120524
2010-12-01 01:38:08 +00:00
Bill Wendling
7c646b924b
Renaming variables to coincide with documentation. No functionality change.
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llvm-svn: 120522
2010-12-01 01:32:02 +00:00
Bill Wendling
490240a5d9
Refactor T1sI and T1sIt encodings into helper classes.
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llvm-svn: 120518
2010-12-01 01:20:15 +00:00
Bill Wendling
4915f56669
Refactor the T1sIt encodings into a parent class to get rid of all of the "let"
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statements.
llvm-svn: 120512
2010-12-01 00:48:44 +00:00
Bill Wendling
05632cb5cc
Rename operands to match ARM documentation. No functionality change.
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llvm-svn: 120500
2010-11-30 23:54:45 +00:00
Bill Wendling
a9e3df7aa0
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
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t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
llvm-svn: 120482
2010-11-30 22:57:21 +00:00