fb54821398
[Sparc] Add support to disassemble sparc memory instructions.
...
llvm-svn: 202575
2014-03-01 07:46:33 +00:00
facca1f049
SPARC: Implement TRAP lowering. Matches what GCC emits.
...
llvm-svn: 201994
2014-02-23 21:43:52 +00:00
ced9226b0f
[Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.
...
llvm-svn: 200963
2014-02-07 07:34:49 +00:00
50f32d949b
[SparcV9] Use correct register class (I64RegClass) to hold the address of _GLOBAL_OFFSET_TABLE_ in sparcv9.
...
llvm-svn: 200368
2014-01-29 03:35:08 +00:00
cd4d9ac62a
[Sparc] Add support for parsing floating point instructions.
...
llvm-svn: 199033
2014-01-12 04:48:54 +00:00
0d288d3105
[Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl.
...
llvm-svn: 198909
2014-01-10 01:48:17 +00:00
6ff62cc539
[Sparc] Multiclass for loads/stores. No functionality change intended.
...
llvm-svn: 198893
2014-01-09 21:49:18 +00:00
b3b7c38983
[Sparc] Add support for parsing branch instructions and conditional moves.
...
llvm-svn: 198738
2014-01-08 06:14:52 +00:00
0458b599f8
[Sparc] Add support for parsing memory operands in sparc AsmParser.
...
llvm-svn: 198658
2014-01-07 01:49:11 +00:00
dfcccc7db0
[Sparc] Add initial implementation of disassembler for sparc
...
llvm-svn: 198591
2014-01-06 08:08:58 +00:00
5f1cce50e6
[Sparc] Add initial implementation of MC Code emitter for sparc.
...
llvm-svn: 198533
2014-01-05 02:13:48 +00:00
c2dee7dc74
[Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.
...
llvm-svn: 198484
2014-01-04 11:30:13 +00:00
9a3da52ea2
[Sparc] Handle atomic loads/stores in sparc backend.
...
llvm-svn: 198286
2014-01-01 22:11:54 +00:00
acf0233a46
[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does.
...
llvm-svn: 198280
2014-01-01 19:00:10 +00:00
3e3a29a2e9
[SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns.
...
This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.
llvm-svn: 198157
2013-12-29 07:15:09 +00:00
9c338504e5
[Sparc]: Implement LEA pattern for sparcv9.
...
llvm-svn: 195575
2013-11-24 20:07:35 +00:00
5ae77f7564
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode.
...
llvm-svn: 193957
2013-11-03 12:28:40 +00:00
2ea4c2880c
[Sparc] Implement JIT for SPARC.
...
No new testcases. However, this patch makes all supported JIT testcases in
test/ExecutionEngine pass on Sparc.
llvm-svn: 192176
2013-10-08 07:15:22 +00:00
8223c553cf
[Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use DelaySlotFiller to fill the delay slot instead.
...
llvm-svn: 192160
2013-10-08 02:50:29 +00:00
f482d3d338
[Sparc] Do not emit nop after fcmp* instruction with V9.
...
llvm-svn: 192056
2013-10-06 07:06:44 +00:00
1230342fd2
[Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.
...
addx/subx does not modify conditional codes whereas addxcc/subxx does.
llvm-svn: 192053
2013-10-06 02:11:10 +00:00
94629eb861
[Sparc] Use correct instruction pattern for CMPri.
...
llvm-svn: 191180
2013-09-22 18:54:54 +00:00
51270837aa
[Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter.
...
llvm-svn: 191168
2013-09-22 09:54:42 +00:00
709d154d69
[Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended.
...
llvm-svn: 191167
2013-09-22 09:18:26 +00:00
2fb440fbad
[Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended.
...
llvm-svn: 191166
2013-09-22 08:51:55 +00:00
cb1dca602c
[Sparc] Add support for TLS in sparc.
...
llvm-svn: 191164
2013-09-22 06:48:52 +00:00
59039dc1bf
[Sparc] Add support for soft long double (fp128).
...
llvm-svn: 189780
2013-09-03 04:11:59 +00:00
35e0c382d5
[Sparc] Add long double (f128) instructions to sparc backend.
...
llvm-svn: 189198
2013-08-25 18:30:06 +00:00
0c00704f27
Use register masks on SPARC call instructions.
...
llvm-svn: 189085
2013-08-23 02:33:47 +00:00
f625773bca
[Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions.
...
llvm-svn: 188738
2013-08-20 01:26:14 +00:00
7dae9ce021
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.
...
llvm-svn: 183613
2013-06-08 15:32:59 +00:00
dc82ac0dcc
[Sparc]: Use cmp instruction instead of subcc to compare integers.
...
llvm-svn: 183463
2013-06-07 00:03:36 +00:00
a54533ed78
Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,
...
llvm-svn: 183243
2013-06-04 18:33:25 +00:00
f80d72f149
Sparc: Add support for indirect branch and blockaddress in Sparc backend.
...
llvm-svn: 183094
2013-06-03 05:58:33 +00:00
774fe2e29a
Sparc: When storing 0, use %g0 directly in the store instruction instead of
...
using two instructions (sethi and store).
llvm-svn: 183090
2013-06-03 00:21:54 +00:00
4a78c86a6a
Implement SPselectfcc for i64 operands.
...
Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).
llvm-svn: 182221
2013-05-19 20:20:54 +00:00
ead983cec9
Handle i64 FrameIndex nodes in SPARC v9 mode.
...
llvm-svn: 182216
2013-05-19 19:14:24 +00:00
65d3287282
Fix the SETHIimm pattern for 64-bit code.
...
Don't ignore the high 32 bits of the immediate.
llvm-svn: 179985
2013-04-21 21:18:03 +00:00
dc1ed57858
Fix patterns for 64-bit pointers.
...
This fixes the pic32 code model for SPARC v9.
llvm-svn: 179469
2013-04-14 01:53:23 +00:00
8cfaffaade
Add SPARC v9 support for select on 64-bit compares.
...
This requires v9 cmov instructions using the %xcc flags instead of the
%icc flags.
Still missing:
- Select floats on %xcc flags.
- Select i64 on %fcc flags.
llvm-svn: 178737
2013-04-04 03:08:00 +00:00
d9bbdfd3cc
Add 64-bit compare + branch for SPARC v9.
...
The same compare instruction is used for 32-bit and 64-bit compares. It
sets two different sets of flags: icc and xcc.
This patch adds a conditional branch instruction using the xcc flags for
64-bit compares.
llvm-svn: 178621
2013-04-03 04:41:44 +00:00
c1d1a4816e
Add 64-bit shift instructions.
...
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
instructions are still usable as zero and sign extensions.
This adds new F3_Sr and F3_Si instruction formats that probably should
be used for the 32-bit shifts as well. They don't really encode an
simm13 field.
llvm-svn: 178525
2013-04-02 04:09:12 +00:00
739d722ef7
Add predicates for distinguishing 32-bit and 64-bit modes.
...
The 'sparc' architecture produces 32-bit code while 'sparcv9' produces
64-bit code.
It is also possible to run 32-bit code using SPARC v9 instructions with:
llc -march=sparc -mattr=+v9
llvm-svn: 178524
2013-04-02 04:09:06 +00:00
5ad3b35377
Add an I64Regs register class for 64-bit registers.
...
We are going to use the same registers for 32-bit and 64-bit values, but
in two different register classes. The I64Regs register class has a
larger spill size and alignment.
The addition of an i64 register class confuses TableGen's type
inference, so it is necessary to clarify the type of some immediates and
the G0 register.
In 64-bit mode, pointers are i64 and should use the I64Regs register
class. Implement getPointerRegClass() to dynamically provide the pointer
register class depending on the subtarget. Use ptr_rc and iPTR for
memory operands.
Finally, add the i64 type to the IntRegs register class. This register
class is not used to hold i64 values, I64Regs is for that. The type is
required to appease TableGen's type checking in output patterns like this:
def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>;
SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and
TableGen doesn't know to check the type of register sub-classes.
llvm-svn: 178522
2013-04-02 04:08:54 +00:00
9619fc0bd1
Clean up Sparc patterns.
...
The types of register variables no longer need to be specified in output
patterns.
llvm-svn: 177845
2013-03-24 19:37:04 +00:00
83aa671f09
Give Sparc instruction patterns direct types instead of register classes.
...
Also update the documentation since Sparc is the nicest backend, and
used as an example in WritingAnLLVMBackend.
llvm-svn: 177835
2013-03-24 00:56:20 +00:00
b1f7c28765
Use direct types in Sparc def : Pat patterns.
...
The SelectionDAG graph has MVT type labels, not register classes, so
this makes it clearer what is happening.
This notation is also robust against adding more types to the IntRegs
register class.
llvm-svn: 177829
2013-03-23 20:35:05 +00:00
ef8bf3cd1f
Move MRI liveouts to Sparc return instructions.
...
llvm-svn: 174413
2013-02-05 18:16:58 +00:00
acf7c47e64
Add missing SDNP properties on the flushw node.
...
llvm-svn: 162515
2012-08-24 00:31:13 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
...
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
a82203f875
Generate correct Sparc32 ABI compliant code for functions that return a struct.
...
llvm-svn: 126108
2011-02-21 03:42:44 +00:00
7a0c350079
Added ICC, FCC as uses of movcc instruction to generate correct code when -mattr=v9 is used.
...
llvm-svn: 124027
2011-01-22 11:36:24 +00:00
ef8cf45eb1
Sparc backend:
...
Rename FLUSH to FLUSHW.
Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used.
llvm-svn: 123997
2011-01-21 22:00:00 +00:00
058e12476c
Sparc backend: Implements a delay slot filler that attempt to fill delay slots
...
with useful instructions.
llvm-svn: 123884
2011-01-20 05:08:26 +00:00
d964580fea
Implement RETURNADDR and FRAMEADDR lowering in SPARC backend.
...
llvm-svn: 123310
2011-01-12 05:08:36 +00:00
ee347f8091
Remove SPARC backend getpcx instruction's Uses. Also, insert an assert to
...
ensure %o7 is not assigned as the destination of getpcx instruction.
llvm-svn: 123304
2011-01-12 03:52:59 +00:00
3b71b0ae3d
Fix SPARC backend call instruction so that arguments passed through registers
...
are correctly marked as used instead of passing all possible argument registers
as used.
llvm-svn: 123301
2011-01-12 03:18:21 +00:00
4d6ade0e31
SPARC backend: correct ICC/FCC uses for ADDX and SELECT_CC
...
llvm-svn: 123281
2011-01-11 22:38:28 +00:00
2f15503d5a
Multiple SPARC backend fixes: added Y register; updated select_cc, subx, subxcc defs/uses;
...
and fixed CustomInserter.
llvm-svn: 122607
2010-12-28 20:39:17 +00:00
2a0a3b43d7
Flag -> Glue, the ongoing saga
...
llvm-svn: 122513
2010-12-23 18:28:41 +00:00
f02b4a686a
Don't call Predicate_* methods directly from Sparc target.
...
Modernize predicates a bit.
The Predicate_* methods are not used by TableGen any longer. They are only
emitted for the sake of legacy code.
llvm-svn: 111263
2010-08-17 18:17:12 +00:00
d7a7356be6
Remove isTwoAddress from Sparc.
...
llvm-svn: 106466
2010-06-21 20:22:35 +00:00
8e9b895c37
tidy up
...
llvm-svn: 98901
2010-03-18 23:57:57 +00:00
9fd22f68f2
Set isBarrier = 1 on return instructions, as they are control barriers.
...
llvm-svn: 86851
2009-11-11 18:11:07 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
840c700654
several major improvements to the sparc backend: support for weak linkage
...
and PIC codegen. Patch by Venkatraman Govindaraju!
llvm-svn: 81877
2009-09-15 17:46:24 +00:00
71425084f1
test commit
...
llvm-svn: 80070
2009-08-26 04:50:17 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
f9bbcd1afd
Major calling convention code refactoring.
...
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 01:29:28 +00:00
2753955fc0
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
...
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
llvm-svn: 57385
2008-10-11 22:08:30 +00:00
effb894453
Rename ConstantSDNode::getValue to getZExtValue, for consistency
...
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
llvm-svn: 56159
2008-09-12 16:56:44 +00:00
0e7b00d79f
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
eac0c96371
Use SDTNone instead of duplicating it.
...
llvm-svn: 48346
2008-03-13 23:07:40 +00:00
97925ec704
Final de-tabification.
...
llvm-svn: 47663
2008-02-27 06:33:05 +00:00
1ea55cf816
This commit changes:
...
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
llvm-svn: 46140
2008-01-17 19:59:44 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
...
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
6e68381e02
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
...
llvm-svn: 44960
2007-12-12 23:12:09 +00:00
77b13af9a6
Unifacalize the CALLSEQ{START,END} stuff.
...
llvm-svn: 44045
2007-11-13 09:19:02 +00:00
f359fed9f9
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
...
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
llvm-svn: 44037
2007-11-13 00:44:25 +00:00
3e18e504ae
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
...
llvm-svn: 41863
2007-09-11 19:55:27 +00:00
ac1591be42
No more noResults.
...
llvm-svn: 40132
2007-07-21 00:34:19 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
...
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
eb7128465d
remove redundant/dead vars
...
llvm-svn: 31434
2006-11-03 23:47:20 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
d376e9f4ac
adjcallstackup/down clobbers the stack pointer
...
llvm-svn: 30909
2006-10-12 17:57:58 +00:00
577ef7694e
Add properties to ComplexPattern.
...
llvm-svn: 30891
2006-10-11 21:03:53 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
bad9d2ee49
Use a couple of multiclass patterns to factor some integer ops.
...
llvm-svn: 30039
2006-09-01 22:28:02 +00:00
38e6d1d5af
remove a bunch of comments
...
llvm-svn: 30038
2006-09-01 22:16:22 +00:00
81b645a76b
CALLSEQ_* produces chain even if that's not needed.
...
llvm-svn: 29603
2006-08-11 09:03:33 +00:00
8587f8885d
Some notes and thoughts to myself
...
llvm-svn: 28182
2006-05-09 04:58:46 +00:00
747cf60696
The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter
...
instructions are expensive.
llvm-svn: 26298
2006-02-21 18:04:32 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
fcb8a3aa76
Use the auto-generated call matcher. Remove a broken impl of the frameaddr/returnaddr
...
intrinsics.
Autogen frameindex matcher
llvm-svn: 26107
2006-02-10 07:35:42 +00:00
0c4dea4cb2
Update to new-style flags usage, simplifying the .td file
...
llvm-svn: 26106
2006-02-10 06:58:25 +00:00
c75d5b093d
add an option to turn on LSR.
...
llvm-svn: 26080
2006-02-09 05:06:36 +00:00
158e1f519c
Rename SPARC V8 target to be the LLVM SPARC target.
...
llvm-svn: 25985
2006-02-05 05:50:24 +00:00
Venkatraman Govindaraju