24faa87075
[VE] Update VELIntrinsic tests
...
Update comment and style of regression tests for VELIntrinsic
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94490
2021-01-13 00:12:50 +09:00
d02de13932
[VE] Support additional VMRGW and VMV intrinsic instructions
...
Support missing VMRGW and VMV intrinsic instructions and add regression
tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94300
2021-01-11 20:50:31 +09:00
b72ca79982
[VE] Support intrinsic to isnert/extract_subreg of v512i1
...
Support insert/extract_subreg intrinsic instructions for v512i1
registers and add regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94298
2021-01-11 20:40:10 +09:00
5ead757f1d
[VE] Support pack_f32p and pack_f32a intrinsic instructions
...
Support pack_f32p and pack_f32a intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94296
2021-01-08 22:59:11 +09:00
12167632bc
[VE] Add SVOB intrinsic instruction
...
Add SVOB intrinsic instruction and a regression test.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94279
2021-01-08 18:49:17 +09:00
aefedb1707
[VE] Add logical mask intrinsic instructions
...
Add andm, orm, xorm, eqvm, nndm, negm, pcvm, lzvm, and tovm intrinsic
instructions, a few pseudo instructions to expand logical intrinsic
using VM512, a mechnism to expand such pseudo instructions, and
regression tests. Also, assign vector mask types and vector mask
register classes correctly. This is required to use VM512 registers
as function arguments.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93093
2020-12-15 01:34:31 +09:00
87f308ab3d
[VE] Add vgt and vsc intrinsic instructions
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Add vgt and vsc intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93032
2020-12-11 18:23:43 +09:00
4b1e329255
[VE] Add vector reduce intrinsic instructions
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Add vrmax, vrmin, vfrmax, vfrmin, vrand, vror, and vrxor intrinsic
instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92941
2020-12-10 22:21:17 +09:00
1a2147fead
[VE] Add vsum and vfsum intrinsic instructions
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Add vsum and vfsum intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92938
2020-12-10 01:11:53 +09:00
398f29fbb0
[VE] Add vfmk intrinsic instructions
...
Add vfmk intrinsic instructions, a few pseudo instructions to expand
vfmk intrinsic using VM512 correctly, and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92758
2020-12-10 00:08:20 +09:00
95ea50e4ad
[VE] Correct LVLGen (LVL instruction insert pass)
...
SX Aurora VE uses an intermediate representation similar to VP as its MIR.
VE itself uses invidiual VL register as its own vector length register at
the hardware level. So, LLVM needs to insert load VL (LVL) instruction just
before vector instructions if the value of VL is changed. This LVLGen pass
generates LVL instructions for such purpose. Previously, a bug is pointed
out in D91416. This patch correct this bug and add a regression test.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D92716
2020-12-09 06:33:53 +09:00
9d4501e2b4
[VE] Add vcp and vex intrinsic instructions
...
Add vcp and vex intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92752
2020-12-07 22:56:55 +09:00
03898b79fb
[VE] Add vrcp, vrsqrt, vcvt, vmrg, and vshf intrinsic instructions
...
Add vrcp, vrsqrt, vcvt, vmrg, and vshf intrinsic instructions and
regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92750
2020-12-07 20:30:12 +09:00
67dbc8195d
[VE] Add vfmad, vfmsb, vfnmad, and vfnmsb intrinsic instructions
...
Add vfmad, vfmsb, vfnmad, and vfnmsb intrinsic instructions and
regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92697
2020-12-07 19:28:17 +09:00
23034a4a63
[VE] Add vfsqrt, vfcmp, vfmax, and vfmin intrinsic instructions
...
Add vfsqrt, vfcmp, vfmax, and vfmin intrinsic instructions and
regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92651
2020-12-05 07:52:14 +09:00
e936d1e113
[VE] Add vfadd, vfsub, vfmul, and vfdiv intrinsic instructions
...
Add vfadd, vfsub, vfmul, and vfdiv intrinsic instructions and
regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92649
2020-12-04 21:58:51 +09:00
1365718778
[VE] Add vsll, vsrl, vsla, vsra, and vsfa intrinsic instructions
...
Add vsll, vsrl, vsla, vsra, and vsfa intrinsic instructions and
regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92550
2020-12-03 23:19:58 +09:00
b91238173d
[VE] Add veqv and vseq intrinsic instructions
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Add veqv and vseq intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92527
2020-12-03 17:39:24 +09:00
dd0159bd81
[VE] Add vand, vor, and vxor intrinsic instructions
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Add vand, vor, and vxor intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92454
2020-12-02 22:52:54 +09:00
c1762bcf0a
[VE] Add vcmp, vmax, and vmin intrinsic instructions
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Add vcmp, vmax, and vmin intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92387
2020-12-02 11:16:52 +09:00
10b164d2f7
[VE] Add vmul and vdiv intrinsic instructions
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Add vmul and vdiv intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92377
2020-12-01 23:03:49 +09:00
c3fe6ea22e
[VE] Add vadd and vsub intrinsic instructions
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Add vadd and vsub intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92332
2020-12-01 19:57:22 +09:00
44a679eaa4
[VE] Change the behaviour of truncate
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Change the way to truncate i64 to i32 in I64 registers. VE assumed
sext values previously. Change it to zext values this time to make
it match to the LLVM behaviour.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92226
2020-11-30 22:12:45 +09:00
132d6d73ea
[VE] Add vmv intrinsic instructions
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Add vmv intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91700
2020-11-19 08:05:35 +09:00
3a5c0ea895
[VE] Add vbrd intrinsic instructions
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Add vbrd intrinsic instructions and a regression test.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91569
2020-11-17 19:04:18 +09:00
38621c45a8
[VE] Add lvm/svm intrinsic instructions
...
Add lvm/svm intrinsic instructions and a regression test. Change
RegisterInfo to specify that VM0/VMP0 are constant and reserved
registers. This modifies a vst regression test, so update it.
Also add pseudo instructions for VM512 register classes
and mechanism to expand them after register allocation.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91541
2020-11-17 07:05:36 +09:00
44a4f93925
[VE] Optimize leaf functions
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Optimize leaf functions by not generating save/restore for callee saved
registers. Update regression tests also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91539
2020-11-17 00:38:01 +09:00
37e7a80aed
[VE] Add lsv/lvs intrinsic instructions
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Add lsv/lvs intrinsic instructions and a regression test.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91526
2020-11-16 23:42:51 +09:00
e0c92c6c03
[VE] Add pfchv intrinsic instructions
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Add pfchv intrinsic instructions and a regression test.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91522
2020-11-16 20:10:44 +09:00
1c00d096a6
[VE] LVLGen sets VL before vector insts
...
The VE backend represents vector instructions with an explicit 'i32'
vector length operand. In the VE ISA, the vector length is always read
from the VL hardware register. The LVLGen pass inserts 'lvl'
instructions as necessary to set VL to the right value before each
vector instruction.
Reviewed By: kaz7
Differential Revision: https://reviews.llvm.org/D91416
2020-11-16 09:19:14 +01:00
02ab46ef73
[VE] Add vst intrinsic instructions
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Add vst intrinsic instructions and a regression test.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91406
2020-11-13 19:11:57 +09:00
410626c9b5
[VE] Support vld intrinsics
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Add intrinsics for vector load instructions. Add a regression test also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91332
2020-11-13 07:34:42 +09:00
Kazushi (Jam) Marukawa