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6 Commits

Author SHA1 Message Date
Alex Bradbury 65d6ea5e68 [RISCV] Codegen support for RV32F floating point comparison operations 
This patch also includes extensive tests targeted at select and br+fcmp IR
inputs. A sequence of br+fcmp required support for FPR32 registers to be added
to RISCVInstrInfo::storeRegToStackSlot and
RISCVInstrInfo::loadRegFromStackSlot.

llvm-svn: 328104
 2018-03-21 15:11:02 +00:00
Alex Bradbury 80c8eb7696 [RISCV] Add codegen for RV32F floating point load/store 
As part of this, add support for load/store from the constant pool. This is
used to materialise f32 constants.

llvm-svn: 327979
 2018-03-20 13:26:12 +00:00
Alex Bradbury 76c29ee815 [RISCV] Add codegen for RV32F arithmetic and conversion operations 
Currently, only a soft floating point ABI is supported.

llvm-svn: 327976
 2018-03-20 12:45:35 +00:00
Alex Bradbury fa7e4ec837 [RISCV] Implement floating point assembler pseudo instructions 
Adds the assembler aliases for the floating point instructions
which can be mapped to a single canonical instruction. The missing
pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

This patch builds upon D40902.

Differential Revision: https://reviews.llvm.org/D41071

Patch by Mario Werner.

llvm-svn: 320569
 2017-12-13 11:37:19 +00:00
Alex Bradbury 4dd94e0ccd [RISCV] MC layer support for the standard RV64F instruction set extension 
llvm-svn: 320028
 2017-12-07 11:02:55 +00:00
Alex Bradbury 0d6cf90663 [RISCV] MC layer support for the standard RV32F instruction set extension 
The most interesting part of this patch is probably the handling of 
rounding mode arguments. Sadly, the RISC-V assembler handles floating point 
rounding modes as a special "argument" when it would be more consistent to 
handle them like the atomics, opcode suffixes. This patch supports parsing 
this optional parameter, using InstAlias to allow parsing these floating point 
instructions when no rounding mode is specified.

Differential Revision: https://reviews.llvm.org/D39893

llvm-svn: 320020
 2017-12-07 10:26:05 +00:00