Commit Graph

12 Commits

Author SHA1 Message Date
Fangrui Song f66b767abe [ELF][AArch64] Allow PT_LOAD to have overlapping p_offset ranges
Ported the D64906 technique to AArch64. It deletes 3 alignments at
PT_LOAD boundaries for the default case: the size of an aarch64 binary
decreases by at most 192kb.

If `sh_addralign(.tdata) < sh_addralign(.tbss)`,
we can potentially make `p_vaddr(PT_TLS)%p_align(PT_TLS) != 0`.

ld.so that are known to have problems if p_vaddr%p_align!=0:

* musl<=1.1.22
* FreeBSD 13.0-CURRENT (and before) rtld-elf arm64

New test aarch64-tls-vaddr-align.s checks that our workaround makes p_vaddr%p_align = 0.

Reviewed By: ruiu

Differential Revision: https://reviews.llvm.org/D64930

llvm-svn: 369344
2019-08-20 08:34:56 +00:00
Fangrui Song 3628d948f5 [ELF][test] Fix aarch64-condb-reloc.s
llvm-svn: 366534
2019-07-19 08:00:22 +00:00
Fangrui Song c2a5459d52 [ELF][AArch64] Improve some aarch64-*.s tests
* Delete aarch64-tls-static.s: it is covered by aarch64-tlsdesc.c
* Add --no-show-raw-insn to llvm-objdump -d tests
* When linking an executable with %t.so, the path %t.so will be recorded in the DT_NEEDED entry if %t.so doesn't have DT_SONAME. The DT_NEEDED has varying lengths on different systems.
  Add -soname to make tests more robust. This issue will become outstanding if we allow overlapping PT_LOAD (D64930).

llvm-svn: 366532
2019-07-19 06:33:36 +00:00
Fangrui Song 5387c2cd17 [llvm-objdump] Print newlines before and after "Disassembly of section ...:"
This improves readability and the behavior is consistent with GNU objdump.

The new test test/tools/llvm-objdump/X86/disassemble-section-name.s
checks we print newlines before and after "Disassembly of section ...:"

Differential Revision: https://reviews.llvm.org/D61127

llvm-svn: 359668
2019-05-01 10:40:48 +00:00
Fangrui Song b159906a9a [test] Change llvm-readobj -long-option to --long-option or well-known short options. NFC
Also change some options that have different semantics (cause confusion) in llvm-readelf mode:

-s => -S
-t => --symbols
-sd => --section-data

llvm-svn: 359651
2019-05-01 05:49:01 +00:00
Fangrui Song 07f8daf05e [ELF] Simplify RelRo, TLS, NOBITS section ranks and make RW PT_LOAD start with RelRo
Old: PT_LOAD(.data | PT_GNU_RELRO(.data.rel.ro .bss.rel.ro) | .bss)
New: PT_LOAD(PT_GNU_RELRO(.data.rel.ro .bss.rel.ro) | .data .bss)

The placement of | indicates page alignment caused by PT_GNU_RELRO. The
new layout has simpler rules and saves space for many cases.

Old size: roundup(.data) + roundup(.data.rel.ro)
New size: roundup(.data.rel.ro + .bss.rel.ro) + .data

Other advantages:

* At runtime the 3 memory mappings decrease to 2.
* start(PT_TLS) = start(PT_GNU_RELRO) = start(RW PT_LOAD). This
  simplifies binary manipulation tools.
  GNU strip before 2.31 discards PT_GNU_RELRO if its
  address is not equal to the start of its associated PT_LOAD.
  This has been fixed by https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=f2731e0c374e5323ce4cdae2bcc7b7fe22da1a6f
  But with this change, we will be compatible with GNU strip before 2.31
* Before, .got.plt (non-relro by default) was placed before .got (relro
  by default), which made it impossible to have _GLOBAL_OFFSET_TABLE_
  (start of .got.plt on x86-64) equal to the end of .got (R_GOT*_FROM_END)
  (https://bugs.llvm.org/show_bug.cgi?id=36555). With the new ordering, we
  can improve on this regard if we'd like to.

Reviewers: ruiu, espindola, pcc

Subscribers: emaste, arichardson, llvm-commits, joerg, jdoerfert

Differential Revision: https://reviews.llvm.org/D56828

llvm-svn: 356117
2019-03-14 03:47:45 +00:00
Dimitry Andric c9de3b4d26 Align AArch64 and i386 image base to superpage
Summary:

As for x86_64, the default image base for AArch64 and i386 should be
aligned to a superpage appropriate for the architecture.

On AArch64, this is 2 MiB, on i386 it is 4 MiB.

Reviewers: emaste, grimar, javed.absar, espindola, ruiu, peter.smith, srhines, rprichard

Reviewed By: ruiu, peter.smith

Subscribers: jfb, markj, arichardson, krytarowski, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D50297

llvm-svn: 342746
2018-09-21 16:58:13 +00:00
Joel Galenson 0f6e12bcdf Modify tests to show PLT entry labels
llvm-svn: 340616
2018-08-24 16:22:42 +00:00
Fangrui Song eb75b8f8f7 [ELF] Move `# REQUIRES:` line to the top
llvm-svn: 335625
2018-06-26 16:58:19 +00:00
Peter Collingbourne 628ec9f193 ELF: Place relro sections after non-relro sections in r/w segment.
This is in preparation for my next change, which will introduce a relro
nobits section. That requires that relro sections appear at the end of the
progbits part of the r/w segment so that the relro nobits section can appear
contiguously.

Because of the amount of churn required in the test suite, I'm making this
change separately.

llvm-svn: 291523
2017-01-10 01:21:30 +00:00
Eugene Leviant ee8dcfbdf7 [ELF] Set max page size to 64K for AArch64
Differential revision: https://reviews.llvm.org/D25079

llvm-svn: 283200
2016-10-04 08:58:55 +00:00
George Rimar 4102bfbe71 [ELF/AARCH64] - Implemented R_AARCH64_CONDBR19 relocation.
R_AARCH64_CONDBR19 is calculated as S+A-P,
Set the immediate field of a conditional branch instruction to bits [20:2] of X; check -2^20 ≤ X< 2^20.

Afaik there is no document for AARCH64 instruction encoding from official for unknown reason, so 
I used gold source code and next link as a reference for implementation: http://kitoslab-eng.blogspot.ru/2012/10/armv8-aarch64-instruction-encoding.html. From which is clear that immediate field of a conditional branch instruction is 5 bits off. That is proved by output which is is equal to gold/bfd now.

Differential revision: http://reviews.llvm.org/D15809

llvm-svn: 257333
2016-01-11 14:22:00 +00:00