984cfe8322
Clarify invalidation strategy in comment.
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llvm-svn: 160997
2012-07-30 21:16:22 +00:00
7e9f6d7d58
Fix grammar-o. Fixes PR13482!
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llvm-svn: 160996
2012-07-30 21:10:51 +00:00
f308c128ea
Assert that all trace candidate blocks have been visited by the PO.
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When computing a trace, all the candidates for pred/succ must have been
visited. Filter out back-edges first, though. The PO traversal ignores
them.
Thanks to Andy for spotting this in review.
llvm-svn: 160995
2012-07-30 21:10:27 +00:00
a12a7d5f74
Hook into PassManager's analysis verification.
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By overriding Pass::verifyAnalysis(), the pass contents will be verified
by the pass manager.
llvm-svn: 160994
2012-07-30 20:57:50 +00:00
91244268d7
Consider address spaces for hashing and CSEing DAG nodes. Otherwise two loads from different x86 segments but the same address would get CSEd
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llvm-svn: 160987
2012-07-30 20:23:19 +00:00
d79864c59b
Typo.
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llvm-svn: 160981
2012-07-30 20:09:37 +00:00
5c490f1b8f
Fix a bug in ARMMachObjectWriter::RecordRelocation() in ARMMachObjectWriter.cpp
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where the other_half of the movt and movw relocation entries needs to get set
and only with the 16 bits of the other half.
rdar://10038370
llvm-svn: 160978
2012-07-30 18:46:15 +00:00
7361846f32
Add MachineInstr::isTransient().
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This is a cleaned up version of the isFree() function in
MachineTraceMetrics.cpp.
Transient instructions are very unlikely to produce any code in the
final output. Either because they get eliminated by RegisterCoalescing,
or because they are pseudo-instructions like labels and debug values.
llvm-svn: 160977
2012-07-30 18:34:14 +00:00
3df6c46fdd
Add MachineTraceMetrics::verify().
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This function verifies the consistency of cached data in the
MachineTraceMetrics analysis.
llvm-svn: 160976
2012-07-30 18:34:11 +00:00
eb488fe165
Verify that the CFG hasn't changed during invalidate().
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The MachineTraceMetrics analysis must be invalidated before modifying
the CFG. This will catch some of the violations of that rule.
llvm-svn: 160969
2012-07-30 17:36:49 +00:00
fee94ca15b
Add MachineBasicBlock::isPredecessor().
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A->isPredecessor(B) is the same as B->isSuccessor(A), but it can
tolerate a B that is null or dangling. This shouldn't happen normally,
but it it useful for verification code.
llvm-svn: 160968
2012-07-30 17:36:47 +00:00
77f1b9c477
When constant folding GEP expressions, keep the address space information of pointers.
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Together with Ran Chachick <ran.chachick@intel.com>
llvm-svn: 160954
2012-07-30 07:25:20 +00:00
efd97044a3
Mark MOVZX16/MOVSX16 as neverHasSideEffects/mayLoad
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llvm-svn: 160953
2012-07-30 07:14:07 +00:00
c6b7ef61f4
Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.
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llvm-svn: 160951
2012-07-30 06:48:11 +00:00
08ead0b14e
Remove some unnecessary filter checks. They were already covered by IsCodeGenOnly
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llvm-svn: 160950
2012-07-30 06:27:19 +00:00
6f4ad80dc8
Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already.
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llvm-svn: 160949
2012-07-30 05:39:34 +00:00
b58dc17025
Simplify code that filtered certain instructions in two different ways. No functional change.
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llvm-svn: 160948
2012-07-30 05:10:05 +00:00
60a58ac3e2
Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway.
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llvm-svn: 160946
2012-07-30 04:53:00 +00:00
ac172e225d
Remove trailing whitespace.
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llvm-svn: 160945
2012-07-30 04:48:12 +00:00
14eac5dda8
Give VCVTTPD2DQ priority over CVTTPD2DQ.
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llvm-svn: 160942
2012-07-30 02:20:32 +00:00
f881d385da
Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.
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llvm-svn: 160941
2012-07-30 02:14:02 +00:00
415b3586d0
Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern.
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llvm-svn: 160939
2012-07-30 01:38:57 +00:00
28402efcb6
Fix load types on intrinsic forms of SS2SD and SD2SS AVX/SSE convert instruction patterns.
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llvm-svn: 160938
2012-07-29 23:26:34 +00:00
b6767f3acd
Move more SSE/AVX convert instruction patterns into their definitions.
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llvm-svn: 160937
2012-07-29 22:30:06 +00:00
ef2932125d
APInt: Simplify code.
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No functionality change.
llvm-svn: 160929
2012-07-29 12:33:29 +00:00
f87dd7c01b
Revert r160920 and r160919 due to dragonegg and clang selfhost failure
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llvm-svn: 160927
2012-07-29 02:44:09 +00:00
d2c3bdd269
Add testcases for GlobalOpt changes in r160693 and r160757.
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llvm-svn: 160925
2012-07-29 01:15:37 +00:00
fc93281c07
Fold patterns for some of the SSE/AVX convert instructions into their instruction definitions.
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llvm-svn: 160922
2012-07-28 18:59:19 +00:00
024797b9a2
Mark some of the SSE/AVX convert instructions as mayLoad/neverHasSideEffects.
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llvm-svn: 160921
2012-07-28 18:36:39 +00:00
9de95e779c
X86 Peephole: fold loads to the source register operand if possible.
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Trying to fix the bot by specifying a triple in the failing testing cases.
llvm-svn: 160920
2012-07-28 17:51:24 +00:00
0fa3ab88ba
X86 Peephole: fold loads to the source register operand if possible.
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Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.
rdar://10554090 and rdar://11873276
llvm-svn: 160919
2012-07-28 16:48:01 +00:00
44f9b5343d
Make CVTSS2SI instruction definition consistent with CVTSD2SI.
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llvm-svn: 160914
2012-07-28 08:28:23 +00:00
1c1aef07b8
Fix up memory load types for SSE scalar convert intrinsic patterns.
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llvm-svn: 160913
2012-07-28 07:59:59 +00:00
32367c063b
X86 Peephole: fix PR13475 in optimizeCompare.
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It is possible that an instruction can use and update EFLAGS.
When checking the safety, we should check the usage of EFLAGS first before
declaring it is safe to optimize due to the update.
llvm-svn: 160912
2012-07-28 03:15:46 +00:00
940534371b
Reenable a basic SSA DAG builder optimization.
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Jakob fixed ProcessImplicifDefs in r159149.
llvm-svn: 160910
2012-07-28 01:48:15 +00:00
0563369755
Add more debug output to MachineTraceMetrics.
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llvm-svn: 160905
2012-07-27 23:58:38 +00:00
1152202cc2
Keep track of the head and tail of the trace through each block.
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This makes it possible to quickly detect blocks that are outside the
trace.
llvm-svn: 160904
2012-07-27 23:58:36 +00:00
86ca9f9e11
Add a DW_AT_high_pc for CUs that are a single address range. Update
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all tests accordingly.
Fixes PR13351.
Patch by shinichiro hamaji!
llvm-svn: 160899
2012-07-27 22:00:05 +00:00
7dfe7abdee
Also compute register mask lists under -new-live-intervals.
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llvm-svn: 160898
2012-07-27 21:56:39 +00:00
bd9f2ba4d6
Typos.
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llvm-svn: 160897
2012-07-27 21:41:59 +00:00
249716e8ae
Teach CodeGenPrep to look past bitcast when it's duplicating return instruction
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into predecessor blocks to enable tail call optimization.
rdar://11958338
llvm-svn: 160894
2012-07-27 21:21:26 +00:00
97e14e02f1
Eliminate the IS_PHI_DEF flag and VNInfo::setIsPHIDef().
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A value number is a PHI def if and only if it begins at a block
boundary. This can be derived from the def slot, a separate flag is not
necessary.
llvm-svn: 160893
2012-07-27 21:11:14 +00:00
4021a7bf25
Add a -new-live-intervals experimental option.
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This option replaces the existing live interval computation with one
based on LiveRangeCalc.cpp. The new algorithm does not depend on
LiveVariables, and it can be run at any time, before or after leaving
SSA form.
llvm-svn: 160892
2012-07-27 20:58:46 +00:00
8e87a75be7
Fixing problems with X86_64_32 relocations and making the assertions more readable.
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llvm-svn: 160889
2012-07-27 20:30:12 +00:00
bc65e8f94e
Add <imp-def> of super-register when lowering SUBREG_TO_REG.
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Patch by Tyler Nowicki!
llvm-svn: 160888
2012-07-27 20:19:49 +00:00
718b007fe9
SmallVector: Crank up verbosity of asserts per Chandler's request.
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Also add assertions to validate the iterator in the insert method overloads.
llvm-svn: 160882
2012-07-27 19:05:58 +00:00
c25f88b703
The TimePassesIsEnabled has since moved to PassManager.cpp.
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llvm-svn: 160881
2012-07-27 19:03:02 +00:00
782d5c434f
Test commit, clean up comment
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llvm-svn: 160880
2012-07-27 18:39:47 +00:00
85591f899d
fix PR13390: do not loop forever with self-referencing self instructions
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llvm-svn: 160876
2012-07-27 18:21:15 +00:00
20c7eb3549
fix infinite loop in instcombine in the presence of a (malformed) self-referencing select inst.
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This can happen as long as the instruction is not reachable. Instcombine does generate these unreachable malformed selects when doing RAUW
llvm-svn: 160874
2012-07-27 18:03:57 +00:00
Jakob Stoklund Olesen