bdb25b3ce5
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
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Avoid relying on implicit_def values, and odd sized G_INSERT/G_EXTRACT
2020-08-24 10:07:30 -04:00
901e3317fe
GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS
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This switches from using G_EXTRACT in odd cases to widen with undef
and unmerge.
2020-08-22 10:25:53 -04:00
432720f1c4
[GlobalISel] Combine sext([sz]ext) -> [sz]ext, zext(zext) -> zext
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Summary:
Combine sext(zext x) to (zext x) since the sign-bit is 0
after the zero-extension.
Combine sext(sext x) to (sext x) and ext(zext x) to (zext x)
since the intermediate step is not needed.
Reviewers: arsenm, volkan, aemerson, aditya_nandakumar
Reviewed By: arsenm
Subscribers: jvesely, wdng, nhaehnle, rovka, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D77210
2020-04-08 11:24:29 +02:00
0ed4744bb5
AMDGPU/GlobalISel: Lower 64-bit uaddo/usubo
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Summary: Add more test cases for signed and unsigned add/sub with overflow.
Reviewers: arsenm, rampitec, kerbowa
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D75051
2020-02-24 23:08:14 +00:00
05f2a04ba7
AMDGPU/GlobalISel: Legalize G_SEXT_INREG
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Split the VALU 64-bit case in RegBankSelect.
2020-02-04 13:23:53 -08:00
34ed76e180
GlobalISel: Implement lower for G_SADDO/G_SSUBO
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Port directly from SelectionDAG, minus the path using
ISD::SADDSAT/ISD::SSUBSAT.
llvm-svn: 375042
2019-10-16 20:46:32 +00:00
Matt Arsenault