Commit Graph

5529 Commits

Author SHA1 Message Date
Chris Lattner 9834ad2fc6 Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 is
set, so disable the pattern in that case.

llvm-svn: 28884
2006-06-20 22:38:59 +00:00
Chris Lattner 7e742e46ac Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation.  For example, we now compile this:

static unsigned long long Y;
void test3() {
  Y = 0xF0F00F00;
}

into:

_test3:
        li r2, 3840
        lis r3, ha16(_Y)
        xoris r2, r2, 61680
        std r2, lo16(_Y)(r3)
        blr

GCC produces:

_test3:
        li r0,0
        lis r2,ha16(_Y)
        ori r0,r0,61680
        sldi r0,r0,16
        ori r0,r0,3840
        std r0,lo16(_Y)(r2)
        blr

llvm-svn: 28883
2006-06-20 22:34:10 +00:00
Evan Cheng 164a221b65 __i386__, __i386, etc. are not defined for x86-64. Use __x86_64__.
llvm-svn: 28881
2006-06-20 22:11:12 +00:00
Chris Lattner d6e160d14d 64-bit bugfix: 0xFFFF0000 cannot be formed with a single lis.
llvm-svn: 28880
2006-06-20 21:39:30 +00:00
Chris Lattner 2d4e8f7e86 Add some patterns for globals, so we can now compile this:
static unsigned long long X, Y;
void test1() {
  X = Y;
}

into:

_test1:
        lis r2, ha16(_Y)
        lis r3, ha16(_X)
        ld r2, lo16(_Y)(r2)
        std r2, lo16(_X)(r3)
        blr

llvm-svn: 28879
2006-06-20 21:23:06 +00:00
Chris Lattner 868a75bec6 Remove some now-unneeded casts from instruction patterns. With the casts
removed, tblgen produces identical output to with them in.

llvm-svn: 28867
2006-06-20 00:39:56 +00:00
Chris Lattner 94d18df658 Add some patterns for ppc64
llvm-svn: 28866
2006-06-20 00:38:36 +00:00
Chris Lattner dbec49d574 Remove some ugly now-redundant casts.
llvm-svn: 28864
2006-06-20 00:25:29 +00:00
Chris Lattner 55594634d7 Fix some mismatched type constraints
llvm-svn: 28862
2006-06-20 00:12:37 +00:00
Evan Cheng cd58e9d8b9 Minor clean up.
llvm-svn: 28860
2006-06-19 19:25:30 +00:00
Rafael Espindola a88966fd5e initial implementation of ARMRegisterInfo::eliminateFrameIndex
fixes test/Regression/CodeGen/ARM/ret_arg5.ll

llvm-svn: 28854
2006-06-18 00:08:07 +00:00
Evan Cheng a54b9643aa A new entry.
llvm-svn: 28848
2006-06-17 00:45:49 +00:00
Chris Lattner 49cadab385 Implement the getPointerRegClass method, which is required for the ptr_rc
magic to work.

llvm-svn: 28847
2006-06-17 00:01:04 +00:00
Evan Cheng d2e9a67cd9 Later models likely to have Yonah like attributes.
llvm-svn: 28843
2006-06-16 21:58:49 +00:00
Chris Lattner 638ee4ee15 Upgrade some load/store instructions to use the proper addressing mode stuff.
llvm-svn: 28841
2006-06-16 21:29:41 +00:00
Chris Lattner e8fe5e2bf4 In 64-bit mode, addr mode operands use G8RC instead of GPRC.
llvm-svn: 28840
2006-06-16 21:29:03 +00:00
Chris Lattner a5190ae7a9 fix some assumptions that pointers can only be 32-bits. With this, we can
now compile:

static unsigned long X;
void test1() {
  X = 0;
}

into:

_test1:
        lis r2, ha16(_X)
        li r3, 0
        stw r3, lo16(_X)(r2)
        blr

Totally amazing :)

llvm-svn: 28839
2006-06-16 21:01:35 +00:00
Chris Lattner b429983988 Split 64-bit instructions out into a separate .td file
llvm-svn: 28838
2006-06-16 20:22:01 +00:00
Chris Lattner 61d703183e Force 64-bit register availability in 64-bit mode. For real.
llvm-svn: 28837
2006-06-16 20:05:06 +00:00
Chris Lattner a7d9db2fa5 Remove the -darwin and -aix llc options, inferring darwinism and aixism from
the target triple & subtarget info.  woo.

llvm-svn: 28835
2006-06-16 18:50:48 +00:00
Chris Lattner f3b5b92e58 Don't pass target name into TargetData anymore, it is never used or needed.
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.

llvm-svn: 28830
2006-06-16 18:22:52 +00:00
Chris Lattner 7f043b52ff Remove ctor with each piece specifyable (which causes overload ambiguities),
add a new init method.

llvm-svn: 28828
2006-06-16 18:11:26 +00:00
Chris Lattner 16682fff2b Document the subtarget features better, make sure that 64-bit mode, 64-bit
support, and 64-bit register use are all consistent with each other.

Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently.  This not makes ppc64 blow up on lots
of stuff :)

llvm-svn: 28825
2006-06-16 17:50:12 +00:00
Chris Lattner a35f306740 Rename some subtarget features. A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.

llvm-svn: 28824
2006-06-16 17:34:12 +00:00
Chris Lattner 0c4aa14deb First baby step towards ppc64 support. This adds a new -march=ppc64 backend
that is currently just like ppc32 :)

llvm-svn: 28813
2006-06-16 01:37:27 +00:00
Chris Lattner cb29586ce4 Add a note that Nate noticed.
llvm-svn: 28808
2006-06-15 21:33:31 +00:00
Jim Laskey 19f964e048 1. Support standard dwarf format (was bootstrapping in Apple format.)
2. Add vector support.

llvm-svn: 28807
2006-06-15 20:51:43 +00:00
Evan Cheng 66f0e09313 Vector extract / insert index operand should have ptr type.
llvm-svn: 28798
2006-06-15 08:19:05 +00:00
Evan Cheng 94bb93f8f7 Type of extract_element index operand should be iPTR.
llvm-svn: 28797
2006-06-15 08:18:06 +00:00
Evan Cheng de7156f12c Type of vector extract / insert index operand should be iPTR.
llvm-svn: 28796
2006-06-15 08:14:54 +00:00
Evan Cheng c8734381ac X86 call instructions can take variable number of operands. Parameters of
vector types are passed via XMM registers.

llvm-svn: 28789
2006-06-14 22:24:55 +00:00
Chris Lattner 37c1c44c14 add a note
llvm-svn: 28787
2006-06-14 21:26:18 +00:00
Evan Cheng ca25486603 Add argument registers to the end of call operand list (partial fix).
llvm-svn: 28783
2006-06-14 18:17:40 +00:00
Jim Laskey f67bec0579 Place dwarf headers at earliest possible point. Well behaved when skipping
functions.

llvm-svn: 28781
2006-06-14 11:35:03 +00:00
Andrew Lenharth 7c69df968c I am sure I had commited this workaround before. Perhaps soon I should sort it all out
llvm-svn: 28772
2006-06-13 20:34:47 +00:00
Andrew Lenharth f570feeae3 It really helps to be returning to the correct place
llvm-svn: 28769
2006-06-13 18:27:39 +00:00
Chris Lattner c5bb8ab1d5 Port some bugfixes in shift handling from SimplifyDemandedBits over to
ComputeMaskedBits.  DemandedMasks and KnownZero/One masks should never have
bits set out of the range of the base datatype.

llvm-svn: 28768
2006-06-13 16:52:37 +00:00
Jim Laskey 8cac9cd5f6 TargetLowering::ComputeMaskedBits was not clearing reciprocal bits on shifts.
llvm-svn: 28765
2006-06-13 13:08:58 +00:00
Evan Cheng 17ca732b6a Cygwin support: use _alloca to allocate stack if > 4k. Patch by Anton Korobeynikov.
llvm-svn: 28764
2006-06-13 05:14:44 +00:00
Chris Lattner ac59ab515a Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register
allocated, thus live across the save/reload.  This fixes

llc-beta /MultiSource/Applications/spiff/spiff
llc-beta /MultiSource/Benchmarks/sim/sim:
llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc
llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest:
llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow
llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio
llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode
llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg

and probably others, with -regalloc=local.

llvm-svn: 28761
2006-06-12 23:59:16 +00:00
Chris Lattner 6b043a24a1 Fix spilling and reloading of CR regs to reload the right values. This fixes
Olden/power (and probably others) with -regalloc=local.

llvm-svn: 28760
2006-06-12 21:50:57 +00:00
Andrew Lenharth 80528499cf Let the alpha breakage begin. First Formals and RET. next Calls
llvm-svn: 28753
2006-06-12 18:09:24 +00:00
Andrew Lenharth 0e57b2cb92 Start on my todo list
llvm-svn: 28752
2006-06-12 16:07:18 +00:00
Rafael Espindola 4e76015e0b lower more then 4 formal arguments. The offset is currently hard coded.
implement SelectFrameIndex

llvm-svn: 28751
2006-06-12 12:28:08 +00:00
Chris Lattner b055c8737f Work around a nasty tblgen bug where it doesn't add operands for varargs
nodes correctly.

llvm-svn: 28745
2006-06-10 01:15:02 +00:00
Chris Lattner 006b2c6ab9 Fix a problem exposed by the local allocator. CALL instructions are not marked
as using incoming argument registers, so the local allocator would clobber them
between their set and use.  To fix this, we give the call instructions a variable
number of uses in the CALL MachineInstr itself, so live variables understands
the live ranges of these register arguments.

llvm-svn: 28744
2006-06-10 01:14:28 +00:00
Evan Cheng beedf824e3 Comments to appease sabre.
llvm-svn: 28737
2006-06-09 06:25:10 +00:00
Evan Cheng 0e14a56d35 Minor compilation speed improvement.
llvm-svn: 28736
2006-06-09 06:24:42 +00:00
Chris Lattner ba1ed585ee Add support for "m" inline asm constraints.
llvm-svn: 28728
2006-06-08 18:03:49 +00:00
Evan Cheng dc614c193e Added X86FunctionInfo subclass of MachineFunction to record whether the
function that is being lowered is forced to use FP. Currently this is only
true for main() / Cygwin.

llvm-svn: 28703
2006-06-06 23:30:24 +00:00