Commit Graph

84346 Commits

Author SHA1 Message Date
Dehao Chen 49359bf3d7 Recommit r251680 (also need to update clang test)
Update the discriminator assignment algorithm

* If a scope has already been assigned a discriminator, do not reassign a nested discriminator for it.
* If the file and line both match, even if the column does not match, we should assign a new discriminator for the stmt.

original code:
; #1 int foo(int i) {
; #2 if (i == 3 || i == 5) return 100; else return 99;
; #3 }

; i == 3: discriminator 0
; i == 5: discriminator 2
; return 100: discriminator 1
; return 99: discriminator 3

llvm-svn: 251689
2015-10-30 05:07:15 +00:00
Craig Topper 9377f01f21 [X86] Use is128BitVector/is256BitVector/is512BitVector in place of getSizeInBits == in some places. NFC
llvm-svn: 251687
2015-10-30 04:31:18 +00:00
Craig Topper 62c3ed0ae3 [X86] Minor formatting fixes. NFC.
llvm-svn: 251686
2015-10-30 04:31:14 +00:00
Dehao Chen 4d84b9321e Revert r251680:
Update the discriminator assignment algorithm

* If a scope has already been assigned a discriminator, do not reassign a nested discriminator for it.
* If the file and line both match, even if the column does not match, we should assign a new discriminator for the stmt.

original code:
; #1 int foo(int i) {
; #2 if (i == 3 || i == 5) return 100; else return 99;
; #3 }

; i == 3: discriminator 0
; i == 5: discriminator 2
; return 100: discriminator 1
; return 99: discriminator 3

llvm-svn: 251685
2015-10-30 04:29:05 +00:00
Lang Hames fd6e8dc369 [Orc] Expose the compile callback API through the C bindings.
llvm-svn: 251683
2015-10-30 03:20:21 +00:00
Craig Topper 9ef327c962 [X86] Use MVT instead of EVT in some places. NFC
Prior to this the compiled code probably had extra checks for extended types that won't ever execute.

llvm-svn: 251682
2015-10-30 03:19:12 +00:00
Dehao Chen 9a5d2b18e0 Update the discriminator assignment algorithm
* If a scope has already been assigned a discriminator, do not reassign a nested discriminator for it.
* If the file and line both match, even if the column does not match, we should assign a new discriminator for the stmt.

original code:
; #1 int foo(int i) {
; #2 if (i == 3 || i == 5) return 100; else return 99;
; #3 }

; i == 3: discriminator 0
; i == 5: discriminator 2
; return 100: discriminator 1
; return 99: discriminator 3

llvm-svn: 251680
2015-10-30 02:38:29 +00:00
Alexey Samsonov 46c1ce6ff5 Let the users of LLVMSymbolizer decide whether they want to symbolize inlined frames.
Introduce LLVMSymbolizer::symbolizeInlinedCode() instead of switching
on PrintInlining option passed to the constructor. This will be needed
once we retrun structured data (instead of std::string) from
LLVMSymbolizer and move printing logic out.

llvm-svn: 251675
2015-10-30 00:40:20 +00:00
Alexey Samsonov e46bd74147 [LLVMSymbolize] Simplify SymbolizableObjectFile::symbolizeInlinedCode(). NFC.
llvm-svn: 251672
2015-10-30 00:02:55 +00:00
Filipe Cabecinhas 14323e02e6 Revert "Don't assert if materializing before seeing any function bodies"
This reverts r251667 since it broke the bots.

llvm-svn: 251671
2015-10-30 00:00:58 +00:00
Alexey Samsonov 76f7ecb83a [LLVMSymbolize] Move printing the description of a global into a separate function. NFC.
llvm-svn: 251669
2015-10-29 23:49:19 +00:00
Filipe Cabecinhas bcfd1f0c56 Don't assert if materializing before seeing any function bodies
This assert was reachable from user input. A minimized test case (no
FUNCTION_BLOCK_ID record) is attached.

Bug found with afl-fuzz

llvm-svn: 251667
2015-10-29 23:37:28 +00:00
Alexey Samsonov 8df3a07aa8 [LLVMSymbolize] Move ModuleInfo into a separate class (SymbolizableModule).
Summary:
This is mostly NFC. It is a first step in cleaning up LLVMSymbolize
library. It removes "ModuleInfo" class which bundles together ObjectFile
and its debug info context in favor of:
  * abstract SymbolizableModule in public headers;
  * SymbolizableObjectFile subclass in implementation.

Additionally, SymbolizableObjectFile is now created via factory, so we
can properly detect object parsing error at this stage instead of keeping
the broken half-parsed object. As a next step, we would be able to
propagate the error all the way back to the library user.

Further improvements might include:
  * factoring out the logic of finding appropriate file with debug info
    for a given object file, and caching all parsed object files into a
    separate class [A].
  * factoring out DILineInfo rendering [B].
This would make what is now a heavyweight "LLVMSymbolizer" a relatively
straightforward class, that calls into [A] to turn filepath into a
SymbolizableModule, delegates actual symbolization to concrete SymbolizableModule
implementation, and lets [C] render the result.

Reviewers: dblaikie, echristo, rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14099

llvm-svn: 251662
2015-10-29 22:21:37 +00:00
Simon Pilgrim ca56a72af9 [X86][SSE] Shuffle blends with zero
This patch generalizes the zeroing of vector elements with the BLEND instructions. Currently a zero vector will only blend if the shuffled elements are correctly inline, this patch recognises when a vector input is zero (or zeroable) and modifies a local copy of the shuffle mask to support a blend. As a zeroable vector input may not be all zeroes, the zeroable vector is regenerated if necessary.

Differential Revision: http://reviews.llvm.org/D14050

llvm-svn: 251659
2015-10-29 22:11:28 +00:00
Lang Hames 3f88a9ea2c [Orc] Teach IndirectStubsManager to manage an expandable pool of stubs, rather
than a pre-allocated slab of stubs. Also add a convenience method for creating a
single stub, rather than a whole block a time.

llvm-svn: 251658
2015-10-29 22:04:22 +00:00
Dehao Chen 7ddf7865b4 clang-format lib/Transforms/Utils/AddDiscriminators.cpp
llvm-svn: 251656
2015-10-29 21:25:33 +00:00
Chandler Carruth c518ebddf3 [FunctionAttrs] Provide a single SCC node set to all of the
transformations in FunctionAttrs rather than building a new one each
time.

This isn't trivial because there are different heuristics from different
passes for exactly what set they want. The primary difference is whether
an *overridable* function completely disables the synthesis of
attributes. I've modeled this by directly testing for overridable, and
using the common set that excludes external and opt-none functions.

This does cause some changes by disabling more optimizations in the face
of opt-none. Specifically, we were still optimizing *calls* to opt-none
functions based on their attributes, just not the bodies. It seems
better to be conservative on both fronts given the intended semanticas
here (best effort to not assume or disturb anything). I've not tried to
test this change as it seems complex, brittle, and not important to the
implicit contract of opt-none. Instead, it seems more like a choice that
should be dictated by the simplified implementation and the change to be
acceptable differences within the space of opt-none.

A big benefit here is that these transformations no longer rely on the
legacy pass manager's SCC types, they just work on generic sets of
function pointers. This will make it easy to re-use their logic in the
new pass manager.

I've also made the transforms static functions instead of members where
trivial while I was touching the signatures.

llvm-svn: 251640
2015-10-29 18:29:15 +00:00
Jonas Paulsson 45d5c673ec [SystemZ] Make the CCRegs regclass non-allocatable.
This was discovered to be necessary while running memchr-01.ll with
-verify-machinstrs, because it is not allowed to have a phys reg live
accross block boundaries while on SSA form, if the register is
allocatable (expect in entry block and landing pads).

In this test case, stringRRE pseudos are expanded after isel by adding
a loop block which produces a live out CC register. To make the test
pass, it was also necessary to not say that StringRRELoop pseudo uses
R0L, this is only true for the StringRRE opcode.

-verify-machineinstrs added to memchr-01.ll test.

New test case int-cmp-51.ll to test that MachineCSE can eliminate
an identical compare (which it couldn't do before).

Reviewed by Ulrich Weigand

llvm-svn: 251634
2015-10-29 16:13:55 +00:00
Marek Olsak 6f6d318e16 AMDGPU/SI: handle undef for llvm.SI.packf16
llvm-svn: 251632
2015-10-29 15:29:09 +00:00
Marek Olsak 74d084f466 AMDGPU/SI: use S_OR for fneg (fabs f32)
llvm-svn: 251631
2015-10-29 15:29:05 +00:00
Marek Olsak f924dd6f3c AMDGPU/SI: use S_AND for i1 trunc
llvm-svn: 251630
2015-10-29 15:05:03 +00:00
Zoran Jovanovic 796ed6d937 [mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is used
Summary:
This commit resolves wrong opcodes for ll and sc instructions for r6 architecutres, which were generated in method MipsTargetLowering::emitAtomicBinary.

Author: Jelena.Losic

Reviewers: dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D13593

llvm-svn: 251629
2015-10-29 14:40:19 +00:00
Artyom Skrobov 0ff1ce4038 Recognize that ARM1176JZ[F]-S support TrustZone
Summary:
ARMv6KZ cores were set up incorrectly in ARM.td; also, the SMI mnemonic
(the old name for SMC, as defined in ARMv6KZ) wasn't supported.

Reviewers: jmolloy, rengolin

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D14154

llvm-svn: 251627
2015-10-29 13:56:19 +00:00
Adhemerval Zanella 1edb084919 [sanitizer] [msan] Unify aarch64 mapping
This patch unify the 39-bit and 42-bit mapping for aarch64 to use only
one instrumentation algorithm.  This removes compiler flag 
SANITIZER_AARCH64_VMA requirement for MSAN on aarch64.

The mapping to use now is for 39 and 42-bits:

    0x00000000000ULL-0x01000000000ULL  MappingDesc::INVALID
    0x01000000000ULL-0x02000000000ULL  MappingDesc::SHADOW
    0x02000000000ULL-0x03000000000ULL  MappingDesc::ORIGIN
    0x03000000000ULL-0x04000000000ULL  MappingDesc::SHADOW
    0x04000000000ULL-0x05000000000ULL  MappingDesc::ORIGIN
    0x05000000000ULL-0x06000000000ULL  MappingDesc::APP
    0x06000000000ULL-0x07000000000ULL  MappingDesc::INVALID
    0x07000000000ULL-0x08000000000ULL  MappingDesc::APP

And only for 42-bits:

    0x08000000000ULL-0x09000000000ULL  MappingDesc::INVALID
    0x09000000000ULL-0x0A000000000ULL  MappingDesc::SHADOW
    0x0A000000000ULL-0x0B000000000ULL  MappingDesc::ORIGIN
    0x0B000000000ULL-0x0F000000000ULL  MappingDesc::INVALID
    0x0F000000000ULL-0x10000000000ULL  MappingDesc::APP
    0x10000000000ULL-0x11000000000ULL  MappingDesc::INVALID
    0x11000000000ULL-0x12000000000ULL  MappingDesc::APP
    0x12000000000ULL-0x17000000000ULL  MappingDesc::INVALID
    0x17000000000ULL-0x18000000000ULL  MappingDesc::SHADOW
    0x18000000000ULL-0x19000000000ULL  MappingDesc::ORIGIN
    0x19000000000ULL-0x20000000000ULL  MappingDesc::INVALID
    0x20000000000ULL-0x21000000000ULL  MappingDesc::APP
    0x21000000000ULL-0x26000000000ULL  MappingDesc::INVALID
    0x26000000000ULL-0x27000000000ULL  MappingDesc::SHADOW
    0x27000000000ULL-0x28000000000ULL  MappingDesc::ORIGIN
    0x28000000000ULL-0x29000000000ULL  MappingDesc::SHADOW
    0x29000000000ULL-0x2A000000000ULL  MappingDesc::ORIGIN
    0x2A000000000ULL-0x2B000000000ULL  MappingDesc::APP
    0x2B000000000ULL-0x2C000000000ULL  MappingDesc::INVALID
    0x2C000000000ULL-0x2D000000000ULL  MappingDesc::SHADOW
    0x2D000000000ULL-0x2E000000000ULL  MappingDesc::ORIGIN
    0x2E000000000ULL-0x2F000000000ULL  MappingDesc::APP
    0x2F000000000ULL-0x39000000000ULL  MappingDesc::INVALID
    0x39000000000ULL-0x3A000000000ULL  MappingDesc::SHADOW
    0x3A000000000ULL-0x3B000000000ULL  MappingDesc::ORIGIN
    0x3B000000000ULL-0x3C000000000ULL  MappingDesc::APP
    0x3C000000000ULL-0x3D000000000ULL  MappingDesc::INVALID
    0x3D000000000ULL-0x3E000000000ULL  MappingDesc::SHADOW
    0x3E000000000ULL-0x3F000000000ULL  MappingDesc::ORIGIN
    0x3F000000000ULL-0x40000000000ULL  MappingDesc::APP

And although complex it provides a better memory utilization that
previous one.

llvm-svn: 251624
2015-10-29 13:02:30 +00:00
Daniel Jasper 1de905a667 Fix use-after-free. Thanks ASAN for giving me a detailed report :-).
llvm-svn: 251623
2015-10-29 12:49:37 +00:00
Vasileios Kalintiris 2f412684a9 [mips] Check the register class before replacing materializations of zero with $zero in microMIPS.
Summary:
The microMIPS register class GPRMM16 does not contain the $zero register.
However, MipsSEDAGToDAGISel::replaceUsesWithZeroReg() would replace uses
of the $dst register:

  [d]addiu, $dst, $zero, 0

with the $zero register, without checking for membership in the register
class of the target machine operand.

Reviewers: dsanders

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D13984

llvm-svn: 251622
2015-10-29 10:17:16 +00:00
Jonas Paulsson 72640f1c9f [MachineVerifier] Analyze MachineMemOperands for mem-to-mem moves.
Since the verifier will give false reports if it incorrectly thinks MI is
loading or storing using an FI, it is necessary to scan memoperands and
find out how the FI is used in the instruction. This should be relatively
rare.

Needed to make CodeGen/SystemZ/spill-01.ll pass, which now runs with this flag.

Reviewed by Quentin Colombet.

llvm-svn: 251620
2015-10-29 08:28:35 +00:00
Cong Hou 45bd8ce64c Revert the revision 251592 as it fails a test on some platforms.
llvm-svn: 251617
2015-10-29 05:35:22 +00:00
Matthias Braun f2f194455f Revert "ScheduleDAGInstrs: Remove IsPostRA flag"
It broke 3 arm testcases.

This reverts commit r251608.

llvm-svn: 251615
2015-10-29 05:06:41 +00:00
Philip Reames 70efccd7dd Fix an unused variable warning which broke the clang-cmake-mips builder
llvm-svn: 251614
2015-10-29 04:21:49 +00:00
JF Bastien 7b452e2c63 [WebAssembly] Update opcode name format for conversions
Summary:
Conversion opcode name format should be f64.convert_u/i64 not f64_convert_u

Author: s3ththompson
Reviewers: jfb
Subscribers: sunfish, jfb, llvm-commits, dschuff
Differential Revision: http://reviews.llvm.org/D14160

llvm-svn: 251613
2015-10-29 04:10:52 +00:00
Xinliang David Li 7a88ad6476 [PGO] Do not emit runtime hook user function for Linux
Clang driver now injects -u<hook_var> flag in the linker 
command line, in which case user function is not needed 
any more.

Differential Revision: http://reviews.llvm.org/D14033

llvm-svn: 251612
2015-10-29 04:08:31 +00:00
Matthias Braun dc7580aa88 MachineScheduler: Fix typo in debug message
Maybe I just missed the humor there ;-)

llvm-svn: 251609
2015-10-29 03:57:28 +00:00
Matthias Braun 7ffadd0087 ScheduleDAGInstrs: Remove IsPostRA flag
This was a layering violation in ScheduleDAGInstrs (and
MachineSchedulerBase) they both shouldn't know directly whether they are
used by the PostMachineScheduler or the MachineScheduler.

llvm-svn: 251608
2015-10-29 03:57:24 +00:00
Matthias Braun b0c437bc76 MachineScheduler: Use ranged for and slightly simplify the code
llvm-svn: 251607
2015-10-29 03:57:17 +00:00
Philip Reames eb3e9dad7f [LVI/CVP] Teach LVI about range metadata
Somewhat shockingly for an analysis pass which is computing constant ranges, LVI did not understand the ranges provided by range metadata.

As part of this change, I included a change to CVP primarily because doing so made it much easier to write small self contained test cases. CVP was previously only handling the non-local operand case, but given that LVI can sometimes figure out information about instructions standalone, I don't see any reason to restrict this.  There could possibly be a compile time impact from this, but I suspect it should be minimal.  If anyone has an example which substaintially regresses, please let me know.  I could restrict the block local handling to ICmps feeding Terminator instructions if needed.  

Note that this patch continues a somewhat bad practice in LVI. In many cases, we know facts about values, and separate context sensitive facts about values. LVI makes no effort to distinguish and will frequently cache the same value fact repeatedly for different contexts. I would like to change this, but that's a large enough change that I want it to go in separately with clear documentation of what's changing. Other examples of this include the non-null handling, and arguments.

As a meta comment: the entire motivation of this change was being able to write smaller (aka reasonable sized) test cases for a future patch teaching LVI about select instructions.

Differential Revision: http://reviews.llvm.org/D13543

llvm-svn: 251606
2015-10-29 03:57:17 +00:00
Lang Hames 645a22a1b7 [Orc] Add support for RuntimeDyld::setProcessAllSections.
llvm-svn: 251604
2015-10-29 03:52:58 +00:00
Philip Reames dbbd77921d [InstSimplify] sgt on i1s also encodes implication
Follow on to http://reviews.llvm.org/D13074, implementing something pointed out by Sanjoy. His truth table from his comment on that bug summarizes things well:
LHS | RHS | LHS >=s RHS | LHS implies RHS
0 | 0 | 1 (0 >= 0) | 1
0 | 1 | 1 (0 >= -1) | 1
1 | 0 | 0 (-1 >= 0) | 0
1 | 1 | 1 (-1 >= -1) | 1

The key point is that an "i1 1" is the value "-1", not "1".

Differential Revision: http://reviews.llvm.org/D13756

llvm-svn: 251597
2015-10-29 03:19:10 +00:00
Philip Reames 846e3e41ed [SimplifyCFG] Constant fold a branch implied by it's incoming edge
The most common use case is when eliminating redundant range checks in an example like the following:
c = a[i+1] + a[i];

Note that all the smarts of the transform (the implication engine) is already in ValueTracking and is tested directly through InstructionSimplify.

Differential Revision: http://reviews.llvm.org/D13040

llvm-svn: 251596
2015-10-29 03:11:49 +00:00
Davide Italiano a904e520c2 [SimplifyLibCalls] Factor out common unsafe-math checks.
llvm-svn: 251595
2015-10-29 02:58:44 +00:00
Benjamin Kramer 4e4ca38bcf Remove CRLF line endings.
llvm-svn: 251594
2015-10-29 02:33:05 +00:00
Cong Hou abe042bb3e Add a flag vectorizer-maximize-bandwidth in loop vectorizer to enable using larger vectorization factor.
To be able to maximize the bandwidth during vectorization, this patch provides a new flag vectorizer-maximize-bandwidth. When it is turned on, the vectorizer will determine the vectorization factor (VF) using the smallest instead of widest type in the loop. To avoid increasing register pressure too much, estimates of the register usage for different VFs are calculated so that we only choose a VF when its register usage doesn't exceed the number of available registers.

llvm-svn: 251592
2015-10-29 01:28:44 +00:00
Hal Finkel 7d0e34eb33 [PowerPC] Recurse through constants when looking for TLS globals
We cannot form ctr-based loops around function calls, including calls to
__tls_get_addr used for PIC TLS variables. References to such TLS variables,
however, might be buried within constant expressions, and so we need to search
the entire constant expression to be sure that no references to such TLS
variables exist.

Fixes PR25256, reported by Eric Schweitz. This is a slightly-modified version
of the patch suggested by Eric in the bug report, and a test case I created.

llvm-svn: 251582
2015-10-28 23:43:00 +00:00
Hal Finkel bdd292ae22 [PowerPC] Don't return unsupported register classes for asm constraints
As a follow-up to r251566, do the same for the other optionally-supported
register classes (mostly for vector registers). Don't return an unavailable
register class (which would cause an assert later), but fail cleanly when
provided an unsupported inline asm constraint.

llvm-svn: 251575
2015-10-28 23:03:45 +00:00
Tim Northover 5e6fce6492 ARM: add watchOS default version support function.
It's useful for Clang's Driver faff.

llvm-svn: 251574
2015-10-28 22:57:14 +00:00
Tim Northover f8e47e4868 ARM: add support for WatchOS's compact unwind information.
llvm-svn: 251573
2015-10-28 22:56:36 +00:00
Tim Northover 8b40366b54 ARM: teach backend about WatchOS and TvOS libcalls.
The most substantial changes are again for watchOS: libcalls are hard-float if
needed and sincos has a different calling convention.

llvm-svn: 251571
2015-10-28 22:51:16 +00:00
Tim Northover e0ccdc6de9 ARM: add backend support for the ABI used in WatchOS
At the LLVM level this ABI is essentially a minimal modification of AAPCS to
support 16-byte alignment for vector types and the stack.

llvm-svn: 251570
2015-10-28 22:46:43 +00:00
Tim Northover 2d4d161519 ARM: support .watchos_version_min and .tvos_version_min.
These MachO file directives are used by linkers and other tools to provide
compatibility information, much like the existing .ios_version_min and
.macosx_version_min.

llvm-svn: 251569
2015-10-28 22:36:05 +00:00
Diego Novillo 748b3ffe3b SamplePGO - Add flag to check sampling coverage.
This adds the flag -mllvm -sample-profile-check-coverage=N to the
SampleProfile pass. N is the percent of input sample records that the
user expects to apply.  If the pass does not use N% (or more) of the
sample records in the input, it emits a warning.

This is useful to detect some forms of stale profiles. If the code has
drifted enough from the original profile, there will be records that do
not match the IR anymore.

This will not detect cases where a sample profile record for line L is
referring to some other instructions that also used to be at line L.

llvm-svn: 251568
2015-10-28 22:30:25 +00:00
Hal Finkel 34d4149452 [PowerPC] Cleanly reject asm crbit constraint with -crbits
When crbits are disabled, cleanly reject the constraint (return the register
class only to cause an assert later).

llvm-svn: 251566
2015-10-28 22:25:52 +00:00
Hal Finkel 1140e1704b Revert "r251451 - [AliasSetTracker] Use mod/ref information for UnknownInstr"
It looks like this broke the stage 2 builder:
  http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto/6989/

Original commit message:

AliasSetTracker does not need to convert the access mode to ModRefAccess if the
new visited UnknownInst has only 'REF' modrefinfo to existing pointers in the
sets.

Patch by Andrew Zhogin!

llvm-svn: 251562
2015-10-28 22:13:41 +00:00
Lang Hames f7c4f187c7 [Orc] Remove the 'takeOwnershipOfBuffers' kludge.
Keno Fischer fixed the underlying issue that necessitated this in r236341.

llvm-svn: 251560
2015-10-28 22:10:27 +00:00
Sanjoy Das c88f5d3c2c [SCEV] Compute max backedge count for loops with "shift ivs"
This teaches SCEV to compute //max// backedge taken counts for loops
like

    for (int i = k; i != 0; i >>>= 1)
      whatever();

SCEV yet cannot represent the exact backedge count for these loops, and
this patch does not change that.  This is really geared towards teaching
SCEV that loops like the above are *not* infinite.

llvm-svn: 251558
2015-10-28 21:27:14 +00:00
Sanjoy Das 13e63a2f21 [JumpThreading] Use dominating conditions to prove implications
Summary:
If P branches to Q conditional on C and Q branches to R conditional on
C' and C => C' then the branch conditional on C' can be folded to an
unconditional branch.

Reviewers: reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13972

llvm-svn: 251557
2015-10-28 21:27:08 +00:00
Xinliang David Li cf4a128c6e [PGO] RawProf Reader code cleanup
Add a couple of helper methods to make the primary
raw profile reader interface's implementation more
readable. It also hides more format details. This
patch has no functional change.

llvm-svn: 251546
2015-10-28 19:34:04 +00:00
Cong Hou da4e8aeec6 [X86] A small fix in X86/X86TargetTransformInfo.cpp: check a value type is simple before calling getSimpleVT().
llvm-svn: 251538
2015-10-28 18:15:46 +00:00
Igor Laevsky 559d170021 [AliasAnalysis] Take into account readnone attribute for the function arguments
Differential Revision: http://reviews.llvm.org/D13992

llvm-svn: 251535
2015-10-28 17:54:48 +00:00
JF Bastien ddaa1c7eb1 WebAssembly: disable some loop-idiom recognition
memset/memcpy aren't fully supported yet. We should invert this test
once they are supported.

llvm-svn: 251534
2015-10-28 17:50:23 +00:00
Diego Novillo a8a3bd2100 SamplePGO - Clear per-function data after applying a profile.
The pass was keeping around a lot of per-function data (visited blocks,
edges, dominance, etc) that is just taking up memory for no reason. In
fact, from function to function it could potentially confuse the
propagator since some maps are indexed by line offsets which can be
common between functions.

llvm-svn: 251531
2015-10-28 17:40:22 +00:00
Igor Laevsky 36e84c0fc7 [AliasAnalysis] Take into account readonly attribute for the function arguments
In getArgModRefInfo we consider all arguments as having MRI_ModRef.
However for arguments marked with readonly attribute we can return 
more precise answer - MRI_Ref.

Differential Revision: http://reviews.llvm.org/D13992

llvm-svn: 251525
2015-10-28 16:42:00 +00:00
Chad Rosier 7142da0ed4 Typo.
llvm-svn: 251521
2015-10-28 15:08:33 +00:00
Chad Rosier 7967614b2b Reapply: [LIR] Add support for creating memsets from loops with a negative stride.
The simple fix is to prevent forming memcpy from loops with a negative stride.

llvm-svn: 251518
2015-10-28 14:38:49 +00:00
James Molloy ef607a2089 [GlobalOpt] Add newlines to DEBUG messages
I think these were affected by a change way back when to stop printing newlines in Value::dump() by default. This change simply allows the debug output to be readable.

NFC.

llvm-svn: 251517
2015-10-28 14:30:53 +00:00
Artyom Skrobov b43981076a [ARM] Allow SP in rGPR, starting from ARMv8
Summary:
This patch handles assembly and disassembly, but not codegen, as of yet.

Additionally, it fixes a bug whereby SP and PC as shifted-reg operands
were treated as predictable in ARMv7 Thumb; and it enables the tests
for invalid and unpredictable instructions to run on both ARMv7 and ARMv8.

Reviewers: jmolloy, rengolin

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D14141

llvm-svn: 251516
2015-10-28 13:58:36 +00:00
Benjamin Kramer 039b10423a Put global classes into the appropriate namespace.
Most of the cases belong into an anonymous namespace. No
functionality change intended.

llvm-svn: 251515
2015-10-28 13:54:36 +00:00
Chad Rosier 8eb2a18a9f Revert "[LIR] Add support for creating memsets from loops with a negative stride."
This reverts commit r251512.  This is causing LNT/chomp to fail.

llvm-svn: 251513
2015-10-28 13:54:09 +00:00
Chad Rosier d6a6bd5501 [LIR] Add support for creating memsets from loops with a negative stride.
http://reviews.llvm.org/D14125

llvm-svn: 251512
2015-10-28 12:55:34 +00:00
Hrvoje Varga 18148671ee [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI and WAIT instructions
Differential Revision: http://reviews.llvm.org/D12628

llvm-svn: 251510
2015-10-28 11:04:29 +00:00
Vasileios Kalintiris 694ba6cecc [Orc] Remove unnecessary semicolon. NFC.
llvm-svn: 251509
2015-10-28 11:02:01 +00:00
James Molloy c67dec690f [GlobalsAA] An indirect global that is initialized is not fair game
When checking if an indirect global (a global with pointer type) is only assigned by allocation functions, first check if the global is itself initialized. If it is, it's not only assigned by allocation functions.

This fixes PR25309. Thanks to David Majnemer for reducing the test case!

llvm-svn: 251508
2015-10-28 10:41:29 +00:00
Craig Topper 93d4a9e117 [X86] Make some for loops over MVTs more explicit (and shorter) by just mentioning all the relevant types in an initializer list. NFC
llvm-svn: 251500
2015-10-28 05:48:32 +00:00
Chen Li 8d23a9bbef Revert r251492 "[IndVarSimplify] Rewrite loop exit values with their
initial values from loop preheader", because it broke some bots.

llvm-svn: 251498
2015-10-28 05:15:51 +00:00
Craig Topper 3a47587c41 Use range-based for loops and use initializer list to remove a small static array. NFC
llvm-svn: 251494
2015-10-28 04:53:27 +00:00
Chen Li 032a5d0cea [IndVarSimplify] Rewrite loop exit values with their initial values from loop preheader
Summary:
This patch adds support to check if a loop has loop invariant conditions which lead to loop exits. If so, we know that if the exit path is taken, it is at the first loop iteration. If there is an induction variable used in that exit path whose value has not been updated, it will keep its initial value passing from loop preheader. We can therefore rewrite the exit value with
its initial value. This will help remove phis created by LCSSA and enable other optimizations like loop unswitch.


Reviewers: sanjoy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13974

llvm-svn: 251492
2015-10-28 04:45:47 +00:00
Xinliang David Li 140f4c4f29 [PGO] Indexed Prof Reader refactoring (NFC)
Change InstrProfReaderIndex from typedef into a wrapper
class with helper methods. This makes the index profile
reader code more readable. It also hides the implementation 
detail of the index format and make it more flexible to allow 
support different (or more than one) format in the future.

llvm-svn: 251491
2015-10-28 04:20:31 +00:00
Craig Topper 4b27576001 Remove templates from CostTableLookup functions. All instantiations had the same type.
This also lets us remove the versions of the functions that took a statically sized array as we can rely on ArrayRef implicit conversion now.

llvm-svn: 251490
2015-10-28 04:02:12 +00:00
Hal Finkel f4052340a4 [PowerPC] Replace cntlz[.] with cntlzw[.]
cntlz is the old POWER mnemonic. cntlzw is the PowerPC mnemonic.

This change fixes an issue when -no-integrated-as: The opcode cntlz is
unrecognized by gas

Alias the POWER mnemonic cntlz[.] to the PowerPC mnemonic cntlzw[.]
This is done for because the POWER cntlz mnemonic has be used by LLVM for
a very long time. We need to make sure that assembly programs
that are using the cntlz[.] do not break with this change.

Change PowerPC tests to reflect the insn change from cntlz to cntlzw.
Add assembly test to verify cntlz[.] is encoded correctly.

Patch by Tom Rix!

llvm-svn: 251489
2015-10-28 03:26:45 +00:00
Sanjoy Das 3ef1e689c9 [ValueTracking] Expose `implies` via ValueTracking, NFC
Summary: This will allow a later patch to `JumpThreading` use this functionality.

Reviewers: reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13971

llvm-svn: 251488
2015-10-28 03:20:19 +00:00
Sanjoy Das 1d1929aace [ValueTracking] Use !range metadata more aggressively in KnownBits
Summary:
Teach `computeKnownBitsFromRangeMetadata` to use `!range` metadata more
aggressively.

Reviewers: majnemer, nlewycky, jingyue

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14100

llvm-svn: 251487
2015-10-28 03:20:15 +00:00
Sanjoy Das 4ff3cf6d92 [SelectionDAG] Don't inspect !range metadata for extended loads
Summary:
Don't call `computeKnownBitsFromRangeMetadata` for extended loads --
this can cause a mismatch between the width of the !range metadata and
the width of the APInt's accumulating `KnownZero` (and `KnownOne` in the
future).  This isn't a problem now, but will be after a future change.

Note: this can be made more aggressive in the future.

Reviewers: nlewycky

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14107

llvm-svn: 251486
2015-10-28 03:20:10 +00:00
Lang Hames 130a7c4152 [Orc] Re-add C bindings for the Orc APIs, with a fix to remove the union that
was causing builder failures.

The bindings were originally added in r251472, and reverted in r251473 due to
the builder failures.

llvm-svn: 251482
2015-10-28 02:40:04 +00:00
Lang Hames f6bd01097a [Orc] Revert the C bindngs commit, r251472, while I debug some builder failures.
llvm-svn: 251473
2015-10-28 01:03:09 +00:00
Lang Hames ec6151066f [Orc] Add experimental C bindings for Orc.
llvm-svn: 251472
2015-10-28 00:28:26 +00:00
James Y Knight 14eedd189b Make the SelectionDAG graph printer use SDNode::PersistentId labels.
r248010 changed the -debug output to use short ids, but did not
similarly modify the graph printer. Change to be consistent, for ease of
cross-reference.

llvm-svn: 251465
2015-10-27 23:09:03 +00:00
Peter Collingbourne 128a9760e0 Bitcode: Fix more unsigned integer overflow bugs.
llvm-svn: 251464
2015-10-27 23:01:25 +00:00
David Majnemer 492937095f [SimplifyCFG] Don't DCE catchret because the successor is unreachable
CatchReturnInst has side-effects: it runs a destructor.  This destructor
could conceivably run forever/call exit/etc. and should not be removed.

llvm-svn: 251461
2015-10-27 22:43:56 +00:00
Vedant Kumar ad6d6e7423 [IR] Limit bits used for CallingConv::ID, update tests
Use 10 bits to represent calling convention ID's instead of 13, and
update the bitcode compatibility tests accordingly. We now error-out in
the bitcode reader when we see bad calling conv ID's.

Thanks to rnk and dexonsmith for feedback!

Differential Revision: http://reviews.llvm.org/D13826

llvm-svn: 251452
2015-10-27 21:17:06 +00:00
Hal Finkel b1bb739166 [AliasSetTracker] Use mod/ref information for UnknownInstr
AliasSetTracker does not need to convert the access mode to ModRefAccess if the
new visited UnknownInst has only 'REF' modrefinfo to existing pointers in the
sets.

Patch by Andrew Zhogin!

llvm-svn: 251451
2015-10-27 20:37:04 +00:00
Sanjay Patel bbd4c79c8f Use the 'arcp' fast-math-flag when combining repeated FP divisors
This is a usage of the IR-level fast-math-flags now that they are propagated to SDNodes. 
This was originally part of D8900.

Removing the global 'enable-unsafe-fp-math' checks will require auto-upgrade and 
possibly other changes.

Differential Revision: http://reviews.llvm.org/D9708

llvm-svn: 251450
2015-10-27 20:27:25 +00:00
David Majnemer 235acde953 [ScalarEvolutionExpander] PHI on a catchpad can be used on both edges
A PHI on a catchpad might be used by both edges out of the catchpad,
feeding back into a loop.  In this case, just use the insertion point.
Anything more clever would require new basic blocks or PHI placement.

llvm-svn: 251442
2015-10-27 19:48:28 +00:00
Jun Bum Lim c9879ecfbc [AArch64]Merge halfword loads into a 32-bit load
This recommits r250719, which caused a failure in SPEC2000.gcc
because of the incorrect insert point for the new wider load.

Convert two halfword loads into a single 32-bit word load with bitfield extract
instructions. For example :
  ldrh w0, [x2]
  ldrh w1, [x2, #2]
becomes
  ldr w0, [x2]
  ubfx w1, w0, #16, #16
  and  w0, w0, #ffff

llvm-svn: 251438
2015-10-27 19:16:03 +00:00
NAKAMURA Takumi 6f49ecc3c4 Whitespace.
llvm-svn: 251437
2015-10-27 19:02:52 +00:00
NAKAMURA Takumi 7ef7293b40 Revert r251291, "Loop Vectorizer - skipping "bitcast" before GEP"
It causes miscompilation of llvm/lib/ExecutionEngine/Interpreter/Execution.cpp.
See also PR25324.

llvm-svn: 251436
2015-10-27 19:02:36 +00:00
Diego Novillo aa55507ff9 Tidy a comment. NFC.
llvm-svn: 251434
2015-10-27 18:41:46 +00:00
Cong Hou 07eeb8001e Create a new interface addSuccessorWithoutWeight(MBB*) in MBB to add successors when optimization is disabled.
When optimization is disabled, edge weights that are stored in MBB won't be used so that we don't have to store them. Currently, this is done by adding successors with default weight 0, and if all successors have default weights, the weight list will be empty. But that the weight list is empty doesn't mean disabled optimization (as is stated several times in MachineBasicBlock.cpp): it may also mean all successors just have default weights.

We should discourage using default weights when adding successors, because it is very easy for users to forget update the correct edge weights instead of using default ones (one exception is that the MBB only has one successor). In order to detect such usages, it is better to differentiate using default weights from the case when optimizations is disabled.

In this patch, a new interface addSuccessorWithoutWeight(MBB*) is created for when optimization is disabled. In this case, MBB will try to maintain an empty weight list, but it cannot guarantee this as for many uses of addSuccessor() whether optimization is disabled or not is not checked. But it can guarantee that if optimization is enabled, then the weight list always has the same size of the successor list.

Differential revision: http://reviews.llvm.org/D13963

llvm-svn: 251429
2015-10-27 17:59:36 +00:00
Charlie Turner ab3215fa11 [SLP] Be more aggressive about reduction width selection.
Summary:
This change could be way off-piste, I'm looking for any feedback on whether it's an acceptable approach.

It never seems to be a problem to gobble up as many reduction values as can be found, and then to attempt to reduce the resulting tree. Some of the workloads I'm looking at have been aggressively unrolled by hand, and by selecting reduction widths that are not constrained by a vector register size, it becomes possible to profitably vectorize. My test case shows such an unrolling which SLP was not vectorizing (on neither ARM nor X86) before this patch, but with it does vectorize.

I measure no significant compile time impact of this change when combined with D13949 and D14063. There are also no significant performance regressions on ARM/AArch64 in SPEC or LNT.

The more principled approach I thought of was to generate several candidate tree's and use the cost model to pick the cheapest one. That seemed like quite a big design change (the algorithms seem very much one-shot), and would likely be a costly thing for compile time. This seemed to do the job at very little cost, but I'm worried I've misunderstood something!

Reviewers: nadav, jmolloy

Subscribers: mssimpso, llvm-commits, aemerson

Differential Revision: http://reviews.llvm.org/D14116

llvm-svn: 251428
2015-10-27 17:59:03 +00:00
Charlie Turner cd6e8cf8c2 [SLP] Try a bit harder to find reduction PHIs
Summary:
Currently, when the SLP vectorizer considers whether a phi is part of a reduction, it dismisses phi's whose incoming blocks are not the same as the block containing the phi. For the patterns I'm looking at, extending this rule to allow phis whose incoming block is a containing loop latch allows me to vectorize certain workloads.

There is no significant compile-time impact, and combined with D13949, no performance improvement measured in ARM/AArch64 in any of SPEC2000, SPEC2006 or LNT.

Reviewers: jmolloy, mcrosier, nadav

Subscribers: mssimpso, nadav, aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D14063

llvm-svn: 251425
2015-10-27 17:54:16 +00:00
Charlie Turner 74c387feb7 [SLP] Treat SelectInsts as reduction values.
Summary:
Certain workloads, in particular sum-of-absdiff loops, can be vectorized using SLP if it can treat select instructions as reduction values.

The test case is a bit awkward. The AArch64 cost model needs some tuning to not be so pessimistic about selects. I've had to tweak the SLP threshold here.

Reviewers: jmolloy, mzolotukhin, spatel, nadav

Subscribers: nadav, mssimpso, aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D13949

llvm-svn: 251424
2015-10-27 17:49:11 +00:00
Diego Novillo c04270d2e4 Fix SamplePGO segfault when debug info is missing.
When emitting a remark for a conditional branch annotation, the remark
uses the line location information of the conditional branch in the
message.  In some cases, that information is unavailable and the
optimization would segfaul. I'm still not sure whether this is a bug or
WAI, but the optimizer should not die because of this.

llvm-svn: 251420
2015-10-27 17:37:00 +00:00
Reid Kleckner fb1c1c7e4d [ms-inline-asm] Leave alignment in bytes if the native assembler uses bytes
The existing behavior was correct on Darwin, which is probably the
platform it was written for.

Before this change, we would rewrite "align 8" to ".align 3" and then
fail to make it through the integrated assembler because 3 is not a
power of 2.

Differential Revision: http://reviews.llvm.org/D14120

llvm-svn: 251418
2015-10-27 17:32:48 +00:00
Rui Ueyama 5579e0b88a Rename qsort -> multikey_qsort. NFC.
`qsort` as a file-scope local function name was confusing.

llvm-svn: 251414
2015-10-27 16:57:50 +00:00
Asaf Badouh c7cb880669 [X86][AVX512] [X86][AVX512] add convert float to half
convert float to half with mask/maskz for the reg to reg version and mask for the reg to mem version (there is no maskz version for reg to mem).

Differential Revision: http://reviews.llvm.org/D14113

llvm-svn: 251409
2015-10-27 15:37:17 +00:00
Charlie Turner 458e79b814 [ARM] Expand ROTL and ROTR of vector value types
Summary: After D13851 landed, we saw backend crashes when compiling the reduced test case included in this patch. The right fix seems to be to allow these vector types for expansion in instruction selection.

Reviewers: rengolin, t.p.northover

Subscribers: RKSimon, t.p.northover, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D14082

llvm-svn: 251401
2015-10-27 10:25:20 +00:00
Mehdi Amini 891c0973df Do not use "else" when both branches return (NFC)
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 251398
2015-10-27 08:12:08 +00:00
David Majnemer dd9a815746 [ScalarEvolutionExpander] Properly insert no-op casts + EH Pads
We want to insert no-op casts as close as possible to the def.  This is
tricky when the cast is of a PHI node and the BasicBlocks between the
def and the use cannot hold any instructions.  Iteratively walk EH pads
until we hit a non-EH pad.

This fixes PR25326.

llvm-svn: 251393
2015-10-27 07:36:42 +00:00
Michael Kuperstein e1194bdb4f [X86] Make elfiamcu an OS, not an environment.
GNU tools require elfiamcu to take up the entire OS field, so, e.g.
i?86-*-linux-elfiamcu is not considered a legal triple.
Make us compatible.

Differential Revision: http://reviews.llvm.org/D14081

llvm-svn: 251390
2015-10-27 07:23:59 +00:00
Davide Italiano c692688cbd [SimplifyLibCalls] Use range-based loop. No functional change.
llvm-svn: 251383
2015-10-27 04:17:51 +00:00
Craig Topper ee0c859788 Convert cost table lookup functions to return a pointer to the entry or nullptr instead of the index.
This avoid mentioning the table name an extra time and allows the lookup to be done directly in the ifs by relying on the bool conversion of the pointer.

While there make use of ArrayRef and std::find_if.

llvm-svn: 251382
2015-10-27 04:14:24 +00:00
Chandler Carruth 69798fb5ec [function-attrs] Refactor code to handle shorter code with early exits.
No functionality changed here, but the indentation is substantially
reduced and IMO the code is much easier to read. I've also added some
helpful comments.

This is just a clean-up I wrote while studying the code, and that has
been in my backlog for a while.

llvm-svn: 251381
2015-10-27 01:41:43 +00:00
Sanjoy Das 63d2b77961 [ValueTracking] Don't special case wrapped ConstantRanges; NFCI
Use `getUnsignedMax` directly instead of special casing a wrapped
ConstantRange.

The previous code would have been "buggy" (and this would have been a
semantic change) if LLVM allowed !range metadata to denote full
ranges. E.g. in

  %val = load i1, i1* %ptr, !range !{i1 1, i1 1} ;; == full set

ValueTracking would conclude that the high bit (IOW the only bit) in
%val was zero.

Since !range metadata does not allow empty or full ranges, this change
is just a minor stylistic improvement.

llvm-svn: 251380
2015-10-27 01:36:06 +00:00
Sanjay Patel 309c4f93e5 [x86] replace integer logic ops with packed SSE FP logic ops
If we have an operand to a bitwise logic op that's already in
an XMM register and the result is going to be sent to an XMM
register, then use an SSE logic op to avoid moves between the
integer and vector register files.

Related commits:
http://reviews.llvm.org/rL248395
http://reviews.llvm.org/rL248399
http://reviews.llvm.org/rL248404
http://reviews.llvm.org/rL248409
http://reviews.llvm.org/rL248415

This should solve PR22428:
https://llvm.org/bugs/show_bug.cgi?id=22428

llvm-svn: 251378
2015-10-27 01:28:07 +00:00
Sanjoy Das 49edd3b3a8 [SCEV] Refactor out ScalarEvolution::getDataLayout; NFC
llvm-svn: 251375
2015-10-27 00:52:09 +00:00
Steve King fee370be72 Fix llc crash processing S/UREM for -Oz builds caused by rL250825.
When taking the remainder of a value divided by a constant, visitREM()
attempts to convert the REM to a longer but faster sequence of instructions.
This conversion calls combine() on a speculative DIV instruction. Commit
rL250825 may cause this combine() to return a DIVREM, corrupting nearby nodes.
Flow eventually hits unreachable().

This patch adds a test case and a check to prevent visitREM() from trying
to convert the REM instruction in cases where a DIVREM is possible.
See http://reviews.llvm.org/D14035

llvm-svn: 251373
2015-10-27 00:14:06 +00:00
Daniel Sanders 5bf6eab6b8 [mips][ias] Fold needsExpansion() and expandInstruction() together. NFC.
Summary:
Previously we maintained two separate switch statements that had to be kept in
sync. This patch merges them into a single switch.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D14012

llvm-svn: 251369
2015-10-26 23:50:00 +00:00
Oleksiy Vyalov 6c2403f3fa Use Twin instead of std::to_string.
http://reviews.llvm.org/D14095

llvm-svn: 251365
2015-10-26 22:37:36 +00:00
Ivan Krasin 465fbe25c4 Fix indents. It's a follow up to r251353.
llvm-svn: 251364
2015-10-26 22:35:40 +00:00
Alexey Samsonov 0fb6451ade [LLVMSymbolize] Don't use LLVMSymbolizer::Options in ModuleInfo. NFC.
LLVMSymbolizer::Options is mostly used in LLVMSymbolizer class anyway.
Let's keep their usage restricted to that class, especially given that
it's worth to move ModuleInfo to a different header, independent from
the symbolizer class.

llvm-svn: 251363
2015-10-26 22:34:56 +00:00
Sanjay Patel e9b500f722 reorganize logic; NFCI (retry r251349)
This is a preliminary step before adding another optimization
to PerformBITCASTCombine().

..and I really hope it's NFC this time!

llvm-svn: 251357
2015-10-26 21:54:14 +00:00
Ivan Krasin 298639a5fd Move imported entities into DwarfCompilationUnit to speed up LTO linking.
Summary:
In particular, this CL speeds up the official Chrome linking with LTO by
1.8x.

See more details in https://crbug.com/542426

Reviewers: dblaikie

Subscribers: jevinskie

Differential Revision: http://reviews.llvm.org/D13918

llvm-svn: 251353
2015-10-26 21:36:35 +00:00
Tim Northover 939f089242 ARM: make sure VFP loads and stores are properly aligned.
Both VLDRS and VLDRD fault if the memory is not 4 byte aligned, which wasn't
really being checked before, leading to faults at runtime.

llvm-svn: 251352
2015-10-26 21:32:53 +00:00
Sanjay Patel f29fed423a revert r251349; it included code for a functional change
llvm-svn: 251350
2015-10-26 21:28:02 +00:00
Sanjay Patel fdf75452e4 reorganize logic; NFCI
This is a preliminary step before adding another optimization
to PerformBITCASTCombine().

llvm-svn: 251349
2015-10-26 21:24:09 +00:00
Keno Fischer 277bfaefaf Initialize BasicAAWrapperPass in it's constructor
Summary: This idiom is used elsewhere in LLVM, but was overlooked here.

Reviewers: chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13628

llvm-svn: 251348
2015-10-26 21:22:58 +00:00
Alexey Samsonov ff8a80b477 Fix build failure on GCC 4.7 (old libstdc++ doesn't have std::map::emplace).
llvm-svn: 251347
2015-10-26 21:20:37 +00:00
David Blaikie efbb29153e Remove use of std::map<>::emplace which is not supported on some older versions of libstdc++
llvm-svn: 251346
2015-10-26 21:10:36 +00:00
Diego Novillo e822b63681 Remove unused local variable. NFC.
llvm-svn: 251344
2015-10-26 20:50:26 +00:00
Peter Collingbourne 99fac80db2 ARM/ELF: Restore original (pre-r251322) logic for deciding whether to use GOT.
Unbreaks linking with gold, which cannot resolve direct relocations referring
to global symbols.

llvm-svn: 251342
2015-10-26 20:46:44 +00:00
Alexey Samsonov f3ecfd3af4 [LLVMSymbolize] Use symbol table only if function linkage name was requested.
Now it's enough to just specify -functions=short without additionally
providing -use-symbol-table=false.

llvm-svn: 251339
2015-10-26 20:12:29 +00:00
Alexey Samsonov 1d3f3271ac Fix build error by fully qualifying llvm::make_unique.
llvm-svn: 251338
2015-10-26 20:12:27 +00:00
Rui Ueyama df94852a60 Optimize StringTableBuilder.
This is a patch to improve StringTableBuilder's performance. That class'
finalize function is very hot particularly in LLD because the function
does tail-merge strings in string tables or SHF_MERGE sections.

Generic std::sort-style sorter is not efficient for sorting strings.
The function implemented in this patch seems to be more efficient.

Here's a benchmark of LLD to link Clang with or without this patch.
The numbers are medians of 50 runs.

-O0
real 0m0.455s
real 0m0.430s (5.5% faster)

-O3
real 0m0.487s
real 0m0.452s (7.2% faster)

Since that is a benchmark of the whole linker, the speedup of
StringTableBuilder itself is much more than that.

http://reviews.llvm.org/D14053

llvm-svn: 251337
2015-10-26 19:58:29 +00:00
Alexey Samsonov 7a952e53f9 [LLVMSymbolize] Use std::unique_ptr more extensively to clarify ownership.
llvm-svn: 251336
2015-10-26 19:41:23 +00:00
Igor Laevsky 1ef06559f4 [RS4GC] Strip noalias attribute after statepoint rewrite
We should remove noalias along with dereference and dereference_or_null attributes 
because statepoint could potentially touch the entire heap including noalias objects.

Differential Revision: http://reviews.llvm.org/D14032

llvm-svn: 251333
2015-10-26 19:06:01 +00:00
Diego Novillo 7963ea1996 SamplePGO - Add optimization reports.
This adds a couple of optimization remarks to the SamplePGO
transformation. When it decides to inline a hot function (to mimic the
inline stack and repeat useful inline decisions in the original build).

It will also report branch destinations. For instance, given the code
fragment:

     6      if (i < 1000)
     7        sum -= i;
     8      else
     9        sum += -i * rand();

If the 'else' branch is taken most of the time, building this code with
-Rpass=sample-profile will produce:

a.cc:9:14: remark: most popular destination for conditional branches at small.cc:6:9 [-Rpass=sample-profile]
      sum += -i * rand();
             ^

llvm-svn: 251330
2015-10-26 18:52:53 +00:00
David Blaikie 7b54b525cd Remove assert(false) in favor of asserting the if conditional it is contained within.
Also adjust the code to avoid 3 redundant map lookups.

llvm-svn: 251327
2015-10-26 18:41:13 +00:00
David Blaikie 94c83370b5 Move the canonical header to the top of its matching cpp file as per coding convention
This ensures that the header will be verified to be standalone (and
avoid mistakes like the one fixed in r251178)

llvm-svn: 251326
2015-10-26 18:40:56 +00:00
Mehdi Amini 5d303285b9 Add an (optional) identification block in the bitcode
Processing bitcode from a different LLVM version can lead to
unexpected behavior. The LLVM project guarantees autoupdating
bitcode from a previous minor revision for the same major, but
can't make any promise when reading bitcode generated from a
either a non-released LLVM, a vendor toolchain, or a "future"
LLVM release. This patch aims at being more user-friendly and
allows a bitcode produce to emit an optional block at the
beginning of the bitcode that will contains an opaque string
intended to describe the bitcode producer information. The
bitcode reader will dump this information alongside any error it
reports.

The optional block also includes an "epoch" number, monotonically
increasing when incompatible changes are made to the bitcode. The
reader will reject bitcode whose epoch is different from the one
expected.

Differential Revision: http://reviews.llvm.org/D13666

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 251325
2015-10-26 18:37:00 +00:00
Evgeniy Stepanov d1aad26589 [safestack] Fast access to the unsafe stack pointer on AArch64/Android.
Android libc provides a fixed TLS slot for the unsafe stack pointer,
and this change implements direct access to that slot on AArch64 via
__builtin_thread_pointer() + offset.

This change also moves more code into TargetLowering and its
target-specific subclasses to get rid of target-specific codegen
in SafeStackPass.

This change does not touch the ARM backend because ARM lowers
builting_thread_pointer as aeabi_read_tp, which is not available
on Android.

The previous iteration of this change was reverted in r250461. This
version leaves the generic, compiler-rt based implementation in
SafeStack.cpp instead of moving it to TargetLoweringBase in order to
allow testing without a TargetMachine.

llvm-svn: 251324
2015-10-26 18:28:25 +00:00
Peter Collingbourne 97aae40880 ARM/ELF: Better codegen for global variable addresses.
In PIC mode we were previously computing global variable addresses (or GOT
entry addresses) by adding the PC, the PC-relative GOT displacement and
the GOT-relative symbol/GOT entry displacement. Because the latter two
displacements are fixed, we ended up performing one more addition than
necessary.

This change causes us to compute addresses using a single PC-relative
displacement, resulting in a shorter code sequence. This reduces code size
by about 4% in a recent build of Chromium for Android.

As a result of this change we no longer need to compute the GOT base address
in the ARM backend, which allows us to remove the Global Base Reg pass and
SDAG lowering for the GOT.

We also now no longer use the GOT when addressing a symbol which is known
to be defined in the same linkage unit. Specifically, the symbol must have
either hidden visibility or a strong definition in the current module in
order to not use the the GOT.

This is a change from the previous behaviour where we would use the GOT to
address externally visible symbols defined in the same module. I think the
only cases where this could matter are cases involving symbol interposition,
but we don't really support that well anyway.

Differential Revision: http://reviews.llvm.org/D13650

llvm-svn: 251322
2015-10-26 18:23:16 +00:00
Alexey Samsonov 145b0fd2a0 Refactor: Simplify boolean conditional return statements in lib/Transforms/Instrumentation
Summary: Use clang-tidy to simplify boolean conditional return statements.

Differential Revision: http://reviews.llvm.org/D9996

Patch by Richard (legalize@xmission.com)!

llvm-svn: 251318
2015-10-26 18:06:40 +00:00
Cong Hou fff8ccf579 Check the case that the numerator and denominator are both zeros when getting edge probabilities in BPI and return 100% in this case.
This issue is triggered in PGO mode when bootstrapping LLVM. It seems that it is not guaranteed that edge weights are always greater than zero which are read from profile data.

llvm-svn: 251317
2015-10-26 18:00:17 +00:00
Alexey Samsonov 57f8837ada Move parts of llvm-symbolizer tool into LLVMSymbolize library.
Summary: See http://lists.llvm.org/pipermail/llvm-dev/2015-October/091624.html

Reviewers: echristo

Subscribers: llvm-commits, aizatsky

Differential Revision: http://reviews.llvm.org/D13998

llvm-svn: 251316
2015-10-26 17:56:12 +00:00
Jonas Paulsson 83553d0cac [SystemZ] LTGFR use regclass should be GR32, not GR64.
Discovered by testing int-cmp-44.ll with -verify-machineinstrs (added to
test run).

llvm-svn: 251299
2015-10-26 15:03:49 +00:00
Jonas Paulsson 7da3820882 [SystemZ] Also clear kill flag for index reg in splitMove().
Discovered by running fp-move-05.ll with -verify-machineinstrs (added
to test case run).

llvm-svn: 251298
2015-10-26 15:03:41 +00:00
Jonas Paulsson 9525b2c0c8 [SystemZ] Don't forget the CC def op on LTEBRCompare pseudos
Discovered by running fp-cmp-02.ll with -verify-machineinstrs (now added
to test run).

llvm-svn: 251297
2015-10-26 15:03:32 +00:00
Jonas Paulsson dab7407258 [SystemZ] Tie operands in SystemZShorteInst if MI becomes 2-address.
Discovered by testing fp-add-02.ll with -verify-machineinstrs.

Test case updated to always run with -verify-machineinstrs.

llvm-svn: 251296
2015-10-26 15:03:07 +00:00
Vasileios Kalintiris 165121f326 [mips] Check for the correct error message in tests for interrupt attributes.
Instead of XFAIL-ing the tests with the wrong usage of the "interrupt"
attribute, we should check that we emit the correct error messages to
the user.

llvm-svn: 251295
2015-10-26 14:24:30 +00:00
James Molloy 493e57de01 [ValueTracking] Extend r251146 to catch a fairly common case
Even though we may not know the value of the shifter operand, it's possible we know the shifter operand is non-zero. This can allow us to infer more known bits - for example:

  %1 = load %p !range {1, 5}
  %2 = shl %q, %1

We don't know %1, but we do know that it is nonzero so %2[0] is known zero, and importantly %2 is known non-zero.

Calling isKnownNonZero is nontrivially expensive so use an Optional to run it lazily and cache its result.

llvm-svn: 251294
2015-10-26 14:10:46 +00:00
Elena Demikhovsky 7a77149391 Loop Vectorizer - skipping "bitcast" before GEP
Vectorization of memory instruction (Load/Store) is possible when the pointer is coming from GEP. The GEP analysis allows to estimate the profit.
In some cases we have a "bitcast" between GEP and memory instruction.
I added code that skips the "bitcast".

http://reviews.llvm.org/D13886

llvm-svn: 251291
2015-10-26 13:42:41 +00:00
Igor Breger e4ddc3f4cd AVX512: Enabled VPBROADCASTB lowering for v64i8 vectors.
Differential Revision: http://reviews.llvm.org/D13896

llvm-svn: 251287
2015-10-26 13:01:02 +00:00
Vasileios Kalintiris 43dff0c033 [mips] Interrupt attribute support for mips32r2+.
Summary:
This patch adds support for using the "interrupt" attribute on Mips
for interrupt handling functions. At this time only mips32r2+ with the
o32 ABI with the static relocation model is supported. Unsupported
configurations will be rejected

Patch by Simon Dardis (+ clang-format & some trivial changes to follow the
LLVM coding standards by me).

Reviewers: mpf, dsanders

Subscribers: dsanders, vkalintiris, llvm-commits

Differential Revision: http://reviews.llvm.org/D10768

llvm-svn: 251286
2015-10-26 12:38:43 +00:00
Igor Breger 684af8156c AVX-512: Use correct extract vector length.
Bug https://llvm.org/bugs/show_bug.cgi?id=25318

Differential Revision: http://reviews.llvm.org/D14062

llvm-svn: 251285
2015-10-26 12:26:34 +00:00
Silviu Baranga b892e35520 [InstCombine] Teach instcombine not to create extra PHI nodes when folding GEPs
Summary:
InstCombine tries to transform GEP(PHI(GEP1, GEP2, ..)) into GEP(GEP(PHI(...))
when possible. However, this may leave the old PHI node around. Even if we
do end up folding the GEPs, having an extra PHI node might not be beneficial.

This change makes the transformation more conservative. We now only do this if
the PHI has only one use, and can therefore be removed after the transformation.

Reviewers: jmolloy, majnemer

Subscribers: mcrosier, mssimpso, llvm-commits

Differential Revision: http://reviews.llvm.org/D13887

llvm-svn: 251281
2015-10-26 10:25:05 +00:00
James Molloy 72222f5dca [ARM] Handle the inline asm constraint type 'o'
This means "memory with offset" and requires very little plumbing to get working. This fixes PR25317.

llvm-svn: 251280
2015-10-26 10:04:52 +00:00
Benjamin Kramer 8604457f2e Drop code after unreachable. No functionality change.
llvm-svn: 251278
2015-10-26 09:55:45 +00:00
Igor Breger f8e461f920 AVX512: Add AVX-512 not materializable instructions.
Otherwise value can be reused , despite its value could be changed - produces incorrect assembler.

https://llvm.org/bugs/show_bug.cgi?id=25270

Differential Revision: http://reviews.llvm.org/D14057

llvm-svn: 251275
2015-10-26 08:37:12 +00:00
Lang Hames 4df7ba7a16 [Orc] Add license header to OrcTargetSupport.
llvm-svn: 251274
2015-10-26 06:40:28 +00:00
David Majnemer 0993e0b8a1 [MC] Add support for GNU as-compatible binary operator precedence
GNU as and Darwin give the various binary operators different
precedence.  LLVM's MC supported the Darwin semantics but not the GNU
semantics.

This fixes PR25311.

llvm-svn: 251271
2015-10-26 03:15:34 +00:00
David Majnemer a375b26144 [MC] Don't crash when .word is given bogus values
We didn't validate that the .word directive was given a sane value,
leading to crashes when we attempt to write out the object file.

Instead, perform some validation and issue a diagnostic pointing at the
start of the diagnostic.

llvm-svn: 251270
2015-10-26 02:45:50 +00:00
Benjamin Kramer 8ceb323bb4 Convert assert(false) into llvm_unreachable where it makes sense.
llvm-svn: 251266
2015-10-25 22:28:27 +00:00
Davide Italiano f04d89bdb4 [ScalarEvolution] Throw away dead code.
llvm-svn: 251256
2015-10-25 20:00:49 +00:00
Davide Italiano 2071f4cc5a [ScalarEvolution] Get rid of NDEBUG in header (correctly this time).
llvm-svn: 251255
2015-10-25 19:55:24 +00:00
Sanjoy Das 15c4c4604f [LCSSA] Unbreak build, don't reuse L; NFC
The build broke in r251248.

llvm-svn: 251251
2015-10-25 19:27:17 +00:00
Davide Italiano 0c34243ac1 [ScalarEvolution] Get rid of NDEBUG in header.
llvm-svn: 251249
2015-10-25 19:13:36 +00:00
Sanjoy Das 331521c688 [LCSSA] Use range for loops; NFC
llvm-svn: 251248
2015-10-25 19:08:32 +00:00
Simon Pilgrim ec6db262e0 [X86][SSE4A] Fix for EXTRQI shuffle lowering.
Incorrect range test - found during fuzz testing.

llvm-svn: 251245
2015-10-25 17:40:54 +00:00
Elena Demikhovsky 092858588a Scalarizer for masked.gather and masked.scatter intrinsics.
When the target does not support these intrinsics they should be converted to a chain of scalar load or store operations.
If the mask is not constant, the scalarizer will build a chain of conditional basic blocks.
I added isLegalMaskedGather() isLegalMaskedScatter() APIs.

Differential Revision: http://reviews.llvm.org/D13722

llvm-svn: 251237
2015-10-25 15:37:55 +00:00
Michael Kuperstein eaa16005af [X86] Use correct calling convention for MCU psABI libcalls
When using the MCU psABI, compiler-generated library calls should pass
some parameters in-register. However, since inreg marking for x86 is currently
done by the front end, it will not be applied to backend-generated calls.

This is a workaround for PR3997, which describes a similar issue for -mregparm.

Differential Revision: http://reviews.llvm.org/D13977

llvm-svn: 251223
2015-10-25 08:14:05 +00:00
Michael Kuperstein fe897623f3 [X86] Add support for elfiamcu triple
This adds support for the i?86-*-elfiamcu triple, which indicates the IAMCU psABI is used.

Differential Revision: http://reviews.llvm.org/D13977

llvm-svn: 251222
2015-10-25 08:07:37 +00:00
Craig Topper eda02a905e Remove two unnecessary conversions from MVT to EVT. NFC
llvm-svn: 251219
2015-10-25 03:15:29 +00:00
Craig Topper 7bf52c9d26 Use MVT::SimpleValueType instead of MVT in template parameter. NFC
llvm-svn: 251217
2015-10-25 00:27:14 +00:00
Rafael Espindola 84921b9860 Refactor: Simplify boolean conditional return statements in lib/CodeGen.
Patch by Richard.

llvm-svn: 251213
2015-10-24 23:11:13 +00:00
Simon Pilgrim 53c2bff5fe [X86][SSE] Use lowerVectorShuffleWithUNPCK instead of custom matches.
Most 128-bit and 256-bit shuffles were manually matching UNPCK patterns - use lowerVectorShuffleWithUNPCK to be more thorough.

llvm-svn: 251211
2015-10-24 22:45:04 +00:00
Simon Pilgrim fdfed5143c [X86][SSE] lowerVectorShuffleWithUNPCK - use equivalent shuffle mask test.
Use isShuffleEquivalent to match UNPCK shuffles - better support for build vector inputs.

llvm-svn: 251207
2015-10-24 20:48:08 +00:00
Michael Zolotukhin 1eeb2da7d4 Refactor: Simplify boolean conditional return statements in lib/Transforms/Vectorize (NFC).
Summary: Use clang-tidy to simplify boolean conditional return statements

Differential Revision: http://reviews.llvm.org/D10003

Patch by Richard<legalize@xmission.com>

llvm-svn: 251206
2015-10-24 20:16:42 +00:00
Simon Pilgrim 3448cbcc51 [DAGCombiner] Tidy up ConstantFP commutation. NFCI
Move ConstantFP canonicalization of commutative instructions to start of 2-op node creation (matches integer) - simplifies constant folding code.

llvm-svn: 251203
2015-10-24 20:06:18 +00:00
Benjamin Kramer 5611561e99 Use all_of to simplify control flow. NFC.
llvm-svn: 251202
2015-10-24 19:30:37 +00:00
Yaron Keren 57fa135b40 Add libuuid to required system libraries list for mingw.
This list is produced by llvm-config --system-libs to be used
by external programs using the llvm libraries, such as creduce.
In r250501 llvm/Support/Windows/Path.inc started to use the constant
FOLDERID_Profile from libuuid.

llvm-svn: 251201
2015-10-24 19:27:28 +00:00
Benjamin Kramer 74b6d3b967 Use find_if to simplify control flow. NFC.
llvm-svn: 251200
2015-10-24 19:03:15 +00:00
Simon Pilgrim 7430804fe1 [DAGCombiner] Generalize masking of constant rotates.
We don't need a mask of a rotation result to be a constant splat - any constant scalar/vector can be usefully folded.

Followup to D13851.

llvm-svn: 251197
2015-10-24 18:44:52 +00:00
Craig Topper 272d6a57bb Call the version of ConvertCostTableLookup that takes a statically sized array rather than pointer and size. NFC
llvm-svn: 251196
2015-10-24 18:40:22 +00:00
Hans Wennborg 34d40434a7 X86ISelLowering: Support tail calls to/from callee pop functions
This enables tail calls with thiscall, stdcall, vectorcall and
fastcall functions.

Differential Revision: http://reviews.llvm.org/D13999

llvm-svn: 251190
2015-10-24 16:47:10 +00:00
Simon Pilgrim e379fe0ddb Fix unused variable warning. NFC.
llvm-svn: 251189
2015-10-24 13:41:45 +00:00
Simon Pilgrim d5ef318b5b [X86][XOP] Add support for lowering vector rotations
This patch adds support for lowering to the XOP VPROT / VPROTI vector bit rotation instructions.

This has required changes to the DAGCombiner rotation pattern matching to support vector types - so far I've only changed it to support splat vectors, but generalising this further is feasible in the future.

Differential Revision: http://reviews.llvm.org/D13851

llvm-svn: 251188
2015-10-24 13:17:26 +00:00
Benjamin Kramer 7ecf8c22cf [TblGen] ArrayRefize TGParser. No functional change intended.
llvm-svn: 251186
2015-10-24 12:46:45 +00:00
Benjamin Kramer 557b601b08 [BasicAliasAnalysis] Simplify expression, no functional change.
(-1) - x + 1 is the same as -x.

llvm-svn: 251185
2015-10-24 11:38:01 +00:00
NAKAMURA Takumi 26c3872666 ScalarReplAggregates.cpp: Try to appease clash of anonymous::SROA in modules build.
llvm-svn: 251181
2015-10-24 06:42:42 +00:00
Sanjoy Das a7e13782f1 Extract out getConstantRangeFromMetadata; NFC
The loop idiom creating a ConstantRange is repeated twice in the
codebase, time to give it a name and a home.

The loop is also repeated in `rangeMetadataExcludesValue`, but using
`getConstantRangeFromMetadata` there would not be an NFC -- the range
returned by `getConstantRangeFromMetadata` may contain a value that none
of the subranges did.

llvm-svn: 251180
2015-10-24 05:37:35 +00:00
Sanjoy Das bb5ffc50b7 Fix whitespace issues in two places; NFC
llvm-svn: 251179
2015-10-24 05:37:28 +00:00
Kostya Serebryany 9cc3b0ddb6 [libFuzzer] add -merge flag to merge corpora
llvm-svn: 251168
2015-10-24 01:16:40 +00:00
Matt Arsenault 2ea0a23f18 AMDGPU: Print modifiers when dumping AMDGPUOperand
llvm-svn: 251160
2015-10-24 00:12:56 +00:00
Igor Laevsky dde0029a25 [RS4GC] Rename stripDereferenceabilityInfo into stripNonValidAttributes.
llvm-svn: 251157
2015-10-23 22:42:44 +00:00
Rafael Espindola 21956e4007 Add a RAW mode to StringTableBuilder.
In this mode it just tries to tail merge the strings without imposing any other
format constrains. It will not, for example, add a null byte between them.

Also add support for keeping a tentative size and offset if we decide to
not optimize after all.

This will be used shortly in lld for merging SHF_STRINGS sections.

llvm-svn: 251153
2015-10-23 21:48:05 +00:00
Chen Li 7009cd3554 Revert rL251061 [SimplifyCFG] Extend SimplifyResume to handle phi of trivial landing pad.
llvm-svn: 251149
2015-10-23 21:13:01 +00:00
Hal Finkel f2199b2178 Handle non-constant shifts in computeKnownBits, and use computeKnownBits for constant folding in InstCombine/Simplify
First, the motivation: LLVM currently does not realize that:

  ((2072 >> (L == 0)) >> 7) & 1 == 0

where L is some arbitrary value. Whether you right-shift 2072 by 7 or by 8, the
lowest-order bit is always zero. There are obviously several ways to go about
fixing this, but the generic solution pursued in this patch is to teach
computeKnownBits something about shifts by a non-constant amount. Previously,
we would give up completely on these. Instead, in cases where we know something
about the low-order bits of the shift-amount operand, we can combine (and
together) the associated restrictions for all shift amounts consistent with
that knowledge. As a further generalization, I refactored all of the logic for
all three kinds of shifts to have this capability. This works well in the above
case, for example, because the dynamic shift amount can only be 0 or 1, and
thus we can say a lot about the known bits of the result.

This brings us to the second part of this change: Even when we know all of the
bits of a value via computeKnownBits, nothing used to constant-fold the result.
This introduces the necessary code into InstCombine and InstSimplify. I've
added it into both because:

  1. InstCombine won't automatically pick up the associated logic in
     InstSimplify (InstCombine uses InstSimplify, but not via the API that
     passes in the original instruction).

  2. Putting the logic in InstCombine allows the resulting simplifications to become
     part of the iterative worklist

  3. Putting the logic in InstSimplify allows the resulting simplifications to be
     used by everywhere else that calls SimplifyInstruction (inlining, unrolling,
     and many others).

And this requires a small change to our definition of an ephemeral value so
that we don't break the rest case from r246696 (where the icmp feeding the
@llvm.assume, is also feeding a br). Under the old definition, the icmp would
not be considered ephemeral (because it is used by the br), but this causes the
assume to remove itself (in addition to simplifying the branch structure), and
it seems more-useful to prevent that from happening.

llvm-svn: 251146
2015-10-23 20:37:08 +00:00
Tim Northover d4f55c0b1b GVN: don't try to replace instruction with itself.
After some look-ahead PRE was added for GEPs, an instruction could end
up in the table of candidates before it was actually inspected. When
this happened the pass might decide it was the best candidate to
replace itself. This didn't go well.

Should fix PR25291

llvm-svn: 251145
2015-10-23 20:30:02 +00:00
Rafael Espindola a9b3944c0e Fix the variable names to match the LLVM style.
llvm-svn: 251143
2015-10-23 20:15:35 +00:00
Sanjoy Das 52f7b08b4a [SCEV] Fix stylistic issue in MatchBinaryAddToConst; NFCI
Instead of checking `(FlagsPresent & ExpectedFlags) != 0`, check
`(FlagsPresent & ExpectedFlags) == ExpectedFlags`.  Right now they're
equivalent since `ExpectedFlags` can only be either `FlagNUW` or
`FlagNSW`, but if we ever pass in `ExpectedFlags` as `FlagNUW | FlagNSW`
then checking `(FlagsPresent & ExpectedFlags) != 0` would be wrong.

llvm-svn: 251142
2015-10-23 20:09:57 +00:00
Sanjoy Das 0a1bee8a80 [Inliner] Don't inline through callsites with operand bundles
Summary:
This change teaches the LLVM inliner to not inline through callsites
with unknown operand bundles.  Currently all operand bundles are
"unknown" operand bundles but in the near future we will add support for
inlining through some select kinds of operand bundles.

Reviewers: reames, chandlerc, majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14001

llvm-svn: 251141
2015-10-23 20:09:55 +00:00
Reid Kleckner f02e33ce42 [X86] Clean up the tail call eligibility logic
Summary:
The logic here isn't straightforward because our support for
TargetOptions::GuaranteedTailCallOpt.

Also fix a bug where we were allowing tail calls to cdecl functions from
fastcall and vectorcall functions. We were special casing thiscall and
stdcall callers rather than checking for any convention that requires
clearing stack arguments before returning.

Reviewers: hans

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14024

llvm-svn: 251137
2015-10-23 19:35:38 +00:00
Lang Hames 3fef117ba5 [RuntimeDyld][COFF] Fix a think-o in the handling of the IMAGE_REL_AMD64_ADDR64
relocation that was introduced in r250733.

llvm-svn: 251135
2015-10-23 18:46:43 +00:00
Kostya Serebryany 94660b3c36 [libFuzzer] remove some old code; also make __sanitizer_get_total_unique_caller_callee_pairs weak so that newer libFuzzer works with older asan
llvm-svn: 251133
2015-10-23 18:37:58 +00:00
Matt Arsenault 382557ec72 AMDGPU: Fix parsing of 32-bit literals with sign bit set
llvm-svn: 251132
2015-10-23 18:07:58 +00:00
Artyom Skrobov 5a6e39454e [ARM] Renaming +t2dsp feature into +dsp, as discussed on llvm-dev
llvm-svn: 251125
2015-10-23 17:19:19 +00:00
Oleg Ranevskyy 6389dd9fa2 [ARM CodeGen] @llvm.debugtrap call may be removed when restoring callee saved registers
Summary:
When ARMFrameLowering::emitPopInst generates a "pop" instruction to restore the callee saved registers, it checks if the LR register is among them. If so, the function may decide to remove the basic block's terminator and replace it with a "pop" to the PC register instead of LR.

This leads to a problem when the block's terminator is preceded by a "llvm.debugtrap" call. The MI iterator points to the trap in such a case, which is also a terminator. If the function decides to restore LR to PC, it erroneously removes the trap.

Reviewers: asl, rengolin

Subscribers: aemerson, jfb, rengolin, dschuff, llvm-commits

Differential Revision: http://reviews.llvm.org/D13672

llvm-svn: 251123
2015-10-23 17:17:59 +00:00
Oleg Ranevskyy 5f78c5c293 Test commit: fix typo in comment.
llvm-svn: 251122
2015-10-23 17:10:44 +00:00
Joseph Tremoulet 3d0fbf1d74 [CodeGen] Mark setjmp/catchret MBBs address-taken
Summary:
This ensures that BranchFolding (and similar) won't remove these blocks.

Also allow AsmPrinter::EmitBasicBlockStart to process MBBs which are
address-taken but do not have BBs that are address-taken, since otherwise
its call to getAddrLabelSymbolTableToEmit would fail an assertion on such
blocks.  I audited the other callers of getAddrLabelSymbolTableToEmit
(and getAddrLabelSymbol); they all have BBs known to be address-taken
except for the call through getAddrLabelSymbol from
WinException::create32bitRef; that call is actually now unreachable, so
I've removed it and updated the signature of create32bitRef.

This fixes PR25168.

Reviewers: majnemer, andrew.w.kaylor, rnk

Subscribers: pgavlin, llvm-commits

Differential Revision: http://reviews.llvm.org/D13774

llvm-svn: 251113
2015-10-23 15:06:05 +00:00
James Molloy 05a896a8d1 [BasicAA] Bugfix for r251016
If the loaded type sizes don't match the element type of the sequential type, all bets are off and the addresses may, indeed, overlap.

Surprisingly, this just got caught in one test, on one builder, out of the 30+ builders testing this change. Congratulations go to http://lab.llvm.org:8011/builders/clang-aarch64-lnt/builds/5205.

llvm-svn: 251112
2015-10-23 14:17:03 +00:00
James Molloy 5b18b4ce96 Revert "[AArch64]Merge halfword loads into a 32-bit load"
This reverts commit r250719. This introduced a codegen fault in SPEC2000.gcc, when compiled for Cortex-A53.

llvm-svn: 251108
2015-10-23 10:41:38 +00:00
Sanjoy Das 42801100e1 [SCEV] Get rid of an unnecessary lambda; NFC
llvm-svn: 251099
2015-10-23 06:57:21 +00:00
Zlatko Buljan 2cf61020b8 [mips][microMIPS] Implement SHLL.PH, SHLL_S.PH, SHLL.QB, SHLLV.PH, SHLLV_S.PH, SHLLV.QB, SHLLV_S.W, SHLL_S.W, SHRA.QB and SHRA_R.QB instructions
Differential Revision: http://reviews.llvm.org/D13929

llvm-svn: 251098
2015-10-23 06:39:29 +00:00
Sanjoy Das 0714e3e245 [SCEV] Fix a latent bug in `getPreStartForExtend`
I could not come up a way to test this -- I think this bug is latent
today, and will not actually result in a miscompile.

In `getPreStartForExtend`, SCEV constructs `PreStart` as a sum of all of
`SA`'s operands except `Op`.  It also uses `SA`'s no-wrap flags, and
this is problematic because removing an element from an add expression
can make it signed-wrap.  E.g. if `SA` was `(127 + 1 + -1)`, then it
could safely be `<nsw>` (since `sext(127) + sext(1) + sext(-1)` ==
`sext(127 + 1 + -1)`), but `(127 + 1)` (== `PreStart` if `Op` is `-1`)
is not `<nsw>`.

Transferring `<nuw>` from `SA` to `PreStart` is safe, as far as I can
tell.

llvm-svn: 251097
2015-10-23 06:33:47 +00:00
Dylan McKay 57cee79f7c [AVR] Add ELF constants to headers
Also adds a 'trivial' ELF file. This was generated by assembling
and linking a file with the symbol main which contains a single
return instruction.

llvm-svn: 251096
2015-10-23 06:05:55 +00:00
Xinliang David Li 8ee08b0f70 Add more intrumentation/runtime helper interfaces (NFC)
This patch converts the remaining references to literal
strings for names of profile runtime entites (such as
profile runtime hook, runtime hook use function, profile
init method, register function etc).

Also added documentation for all the new interfaces.

llvm-svn: 251093
2015-10-23 04:22:58 +00:00
Mehdi Amini d42ae865b8 SLPVectorizer: AllSameOpcode* starts "true" only for instructions
r251085 wasn't as NFC as intended...

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 251087
2015-10-23 01:04:45 +00:00
Mehdi Amini bf6ee32ca5 SLPVectorizer: refactor reorderInputsAccordingToOpcode (NFC)
This is intended to simplify the changes needed to solve PR25247.

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 251085
2015-10-23 00:46:17 +00:00
Davide Italiano fbb958c24b [CodeGen] Remove usage of NDEBUG in header.
Moreover, this seems unused.

llvm-svn: 251081
2015-10-23 00:17:40 +00:00
Kostya Serebryany 2e9fca9f88 [libFuzzer] use the indirect caller-callee counter as an independent search heuristic
llvm-svn: 251078
2015-10-22 23:55:39 +00:00
Kostya Serebryany 09d2a5f6e1 [libFuzzer] more refactoring the code that checks the coverage. NFC
llvm-svn: 251075
2015-10-22 22:56:45 +00:00
Kostya Serebryany 007c9b25f4 [libFuzzer] refactoring the code that checks the coverage. NFC
llvm-svn: 251074
2015-10-22 22:50:47 +00:00
Kostya Serebryany b36025619c [libFuzzer] remove the deprecated 'tokens' feature
llvm-svn: 251069
2015-10-22 21:48:09 +00:00
Justin Bogner f98df7a0d1 LoopPass: Remove redoLoop, it isn't used. NFC
In r251064 I removed a logically unreachable call to `redoLoop`, and
now there aren't any callers of this API at all. Remove the needless
complexity.

llvm-svn: 251067
2015-10-22 21:31:34 +00:00
Justin Bogner 35e46cdd04 LoopPass: Simplify the API for adding a new loop. NFC
The insertLoop() API is only used to add new loops, and has confusing
ownership semantics. Simplify it by replacing it with addLoop().

llvm-svn: 251064
2015-10-22 21:21:32 +00:00
Chen Li c6e28782d8 [SimplifyCFG] Extend SimplifyResume to handle phi of trivial landing pad.
Summary: Currently SimplifyResume can convert an invoke instruction to a call instruction if its landing pad is trivial. In practice we could have several invoke instructions with trivial landing pads and share a common rethrow block, and in the common rethrow block, all the landing pads join to a phi node. The patch extends SimplifyResume to check the phi of landing pad and their incoming blocks. If any of them is trivial, remove it from the phi node and convert the invoke instruction to a call instruction.  

Reviewers: hfinkel, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13718

llvm-svn: 251061
2015-10-22 20:48:38 +00:00
Xinliang David Li 83bc4220ce Add helper functions and remove hard coded references to instProf related name/name-prefixes
This is a clean up patch that defines instr prof section and variable 
name prefixes in a common header with access helper functions. 
clang FE change will be done as a follow up once this patch is in.

Differential Revision: http://reviews.llvm.org/D13919

llvm-svn: 251058
2015-10-22 20:32:12 +00:00
David Majnemer e0675fb8fb [Sink] Don't check BB.empty()
As an invariant, BasicBlocks cannot be empty when passed to a transform.
This is not the case for MachineBasicBlocks and the Sink pass was ported
from the MachineSink pass which would explain the check's existence.

llvm-svn: 251057
2015-10-22 20:29:08 +00:00
Alexey Samsonov f4fb5f500c [ASan] Enable instrumentation of dynamic allocas by default.
llvm-svn: 251056
2015-10-22 20:07:28 +00:00
Sanjoy Das eeca9f6fd4 [SCEV] Commute zero extends through <nuw> additions
llvm-svn: 251052
2015-10-22 19:57:38 +00:00
Sanjoy Das 6e78b17b43 [SCEV] Opportunistically interpret unsigned constraints as signed
Summary:
An unsigned comparision is equivalent to is corresponding signed version
if both the operands being compared are positive.  Teach SCEV to use
this fact when profitable.

Reviewers: atrick, hfinkel, reames, nlewycky

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13687

llvm-svn: 251051
2015-10-22 19:57:34 +00:00
Sanjoy Das 1123148d40 [SCEV] Teach SCEV some axioms about non-wrapping arithmetic
Summary:
 - A s<  (A + C)<nsw> if C >  0
 - A s<= (A + C)<nsw> if C >= 0
 - (A + C)<nsw> s<  A if C <  0
 - (A + C)<nsw> s<= A if C <= 0

Right now `C` needs to be a constant, but we can later generalize it to
be a non-constant if needed.

Reviewers: atrick, hfinkel, reames, nlewycky

Subscribers: sanjoy, llvm-commits

Differential Revision: http://reviews.llvm.org/D13686

llvm-svn: 251050
2015-10-22 19:57:29 +00:00
Sanjoy Das a060e602fd [SCEV] Commute sign extends through nsw additions
Summary: Depends on D13613.

Reviewers: atrick, hfinkel, reames, nlewycky

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13685

llvm-svn: 251049
2015-10-22 19:57:25 +00:00
Sanjoy Das 8f27415c05 [SCEV] Mark AddExprs as nsw or nuw if legal
Summary:
This uses `ScalarEvolution::getRange` and not potentially control
dependent `nsw` and `nuw` bits on the arithmetic instruction.

Reviewers: atrick, hfinkel, nlewycky

Subscribers: llvm-commits, sanjoy

Differential Revision: http://reviews.llvm.org/D13613

llvm-svn: 251048
2015-10-22 19:57:19 +00:00
Alexey Samsonov 8daaf8b09b [ASan] Minor fixes to dynamic allocas handling:
* Don't instrument promotable dynamic allocas:
  We already have a test that checks that promotable dynamic allocas are
  ignored, as well as static promotable allocas. Make sure this test will
  still pass if/when we enable dynamic alloca instrumentation by default.

* Handle lifetime intrinsics before handling dynamic allocas:
  lifetime intrinsics may refer to dynamic allocas, so we need to emit
  instrumentation before these dynamic allocas would be replaced.

Differential Revision: http://reviews.llvm.org/D12704

llvm-svn: 251045
2015-10-22 19:51:59 +00:00
Davide Italiano be8c33e8da [ExecutionEngine] Garbage collect some dead (and unsafe) code.
llvm-svn: 251042
2015-10-22 18:46:27 +00:00
Rafael Espindola fc063e8fec Avoid storing a second copy of each string in StringTableBuilder.
This was only use in the extremely uncommon case of @@@ symbols on ELF.

llvm-svn: 251039
2015-10-22 18:32:06 +00:00
Matthias Braun d276de6db1 AArch64: Disable the latency heuristic
It turned out not to improve any of our benchmarks but occasionally led
to increased register pressure and spilling.

Only enabling for the Cyclone CPU as the results on the cortex CPUs
give mixed results.

Differential Revision: http://reviews.llvm.org/D13708

llvm-svn: 251038
2015-10-22 18:07:38 +00:00
Matthias Braun 61f4d6439c MachineScheduler: Add a way to disable the 'ReduceLatency' heuristic
llvm-svn: 251037
2015-10-22 18:07:31 +00:00
Eric Christopher 227d71bba6 Remove the last traces of X86CompilationCallback as it is completely
unused.

llvm-svn: 251035
2015-10-22 17:55:35 +00:00
Craig Topper 8fe40e0ed5 Change makeLibCall to take an ArrayRef<SDValue> instead of pointer and size. This removes the need to pass a hardcoded size in many places. NFC
llvm-svn: 251032
2015-10-22 17:05:00 +00:00
Zachary Turner c55a5041e3 Fix broken build under MSVC.
llvm-svn: 251030
2015-10-22 16:42:31 +00:00
Craig Topper 42526d3372 Use ArrayRef instead of pointer and size. NFC
llvm-svn: 251029
2015-10-22 16:35:56 +00:00
Zia Ansari 8f509a7044 [X86] - Catch extra combine opportunities for redundant imuls.
When we fold "mul ((add x, c1), c1)" -> "add ((mul x, c2), c1*c2)", we bail if (add x, c1) has multiple
users which would result in an extra add instruction.
In such cases, this patch adds a check to see if we can eliminate a multiply instruction in exchange for the extra add.

I also added the capability of doing the existing optimization with non-splatted vectors (splatted also works).

Differential Revision: http://reviews.llvm.org/D13740

llvm-svn: 251028
2015-10-22 16:14:45 +00:00
Bill Schmidt de1dc9c98f [PPC] Fix PR24686 by failing assembly for an invalid relocation
PR24686 identifies a problem where a relocation expression is invalid
when not all of the symbols in the expression can be locally
resolved.  This causes the compiler to request a PC-relative half16ds
relocation, which is nonsensical for PowerPC.  This patch recognizes
this situation and ensures we fail the assembly cleanly.

Test case provided by Anton Blanchard.

llvm-svn: 251027
2015-10-22 15:53:44 +00:00
Rafael Espindola e015f66a73 Avoid hash lookups when finalizing StringTableBuilder. NFC.
llvm-svn: 251024
2015-10-22 15:26:35 +00:00
Rafael Espindola 0169a45e04 Use array_pod_sort. NFC.
llvm-svn: 251023
2015-10-22 15:15:44 +00:00
Asaf Badouh 7c52245660 [X86][AVX512] extend vcvtph2ps to support xmm/ymm and sae versions
Differential Revision: http://reviews.llvm.org/D13945

llvm-svn: 251018
2015-10-22 14:01:16 +00:00
James Molloy 5b2a732fac [GlobalsAA] Loosen an overly conservative bailout
Instead of bailing out when we see loads, analyze them. If we can prove that the loaded-from address must escape, then we can conclude that a load from that address must escape too and therefore cannot alias a non-addr-taken global.

When checking if a Value can alias a non-addr-taken global, if the Value is a LoadInst of a non-global, recurse instead of bailing.

If we can follow a trail of loads up to some base that is captured, we know by inference that all the loads we followed are also captured.

llvm-svn: 251017
2015-10-22 13:44:26 +00:00
James Molloy 5a4d8cd519 [BasicAA] Non-equal indices in a GEP of a SequentialType don't overlap
If the final indices of two GEPs can be proven to not be equal, and
the GEP is of a SequentialType (not a StructType), then the two GEPs
do not alias.

llvm-svn: 251016
2015-10-22 13:28:18 +00:00
James Molloy 1d88d6f289 [ValueTracking] Add a new predicate: isKnownNonEqual()
isKnownNonEqual(A, B) returns true if it can be determined that A != B.

At the moment it only knows two facts, that a non-wrapping add of nonzero to a value cannot be that value:

A + B != A [where B != 0, addition is nsw or nuw]

and that contradictory known bits imply two values are not equal.

This patch also hooks this up to InstSimplify; InstSimplify had a peephole for the first fact but not the second so this teaches InstSimplify a new trick too (alas no measured performance impact!)

llvm-svn: 251012
2015-10-22 13:18:42 +00:00
Pawel Bylica 64d08ff034 Use range-based for loop in sys::path::append(). NFC.
llvm-svn: 250999
2015-10-22 08:12:15 +00:00
Elena Demikhovsky 5c97dfdc9c AVX-512: Fixed a bug in select_cc for i1 type
Fixed faiure:
LLVM ERROR: Cannot select: t33: i1 = select_cc t25, Constant:i32<0>, t45, t42, seteq:ch

added a test

Differential Revision: http://reviews.llvm.org/D13943

llvm-svn: 250996
2015-10-22 07:10:29 +00:00
Elena Demikhovsky 7ad0d563a5 Partially reverted changes from r250686
Clang runtime failure was reported.
   Assertion failed: (isExtended() && "Type is not extended!"), function getTypeForEVT
I'll need to add a proper handling for PointerType in masked load/store intrinsics.

llvm-svn: 250995
2015-10-22 06:20:29 +00:00
Sanjoy Das 6ed053051d [IR] Add a `makeNoWrapRegion` method to `ConstantRange`
Summary: This will be used in a future change to ScalarEvolution.

Reviewers: hfinkel, reames, nlewycky

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13612

llvm-svn: 250975
2015-10-22 03:12:57 +00:00
Sanjoy Das 98a341bc0c [OperandBundles] Make function attributes conservatively correct
Summary:
This makes attribute accessors on `CallInst` and `InvokeInst` do the
(conservatively) right thing.  This essentially involves, in some
cases, *not* falling back querying the attributes on the called
`llvm::Function` when operand bundles are present.

Attributes locally present on the `CallInst` or `InvokeInst` will still
override operand bundle semantics.  The LangRef has been amended to
reflect this.  Note: this change does not do anything prevent
`-function-attrs` from inferring `CallSite` local attributes after
inspecting the called function -- that will be done as a separate
change.

I've used `-adce` and `-early-cse` to test these changes.  There is
nothing special about these passes (and they did not require any
changes) except that they seemed be the easiest way to write the tests.

This change does not add deal with `argmemonly`.  That's a later change
because alias analysis requires a related fix before `argmemonly` can be
tested.

Reviewers: reames, chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13961

llvm-svn: 250973
2015-10-22 03:12:22 +00:00
JF Bastien f2364bf129 WebAssembly: fix more syntax
br_if shouldn't start with a dot.
div and rem went from prefix u/s to suffix.

llvm-svn: 250972
2015-10-22 02:32:50 +00:00
Pete Cooper b70b956c80 Add missing load/store flags to thumb2 instructions.
These were the cause of a verifier error when building 7zip with
-verify-machineinstrs.  Running 'make check' with the verifier
triggered the same error on the test here so i've updated the test
to run the verifier on one of its runs instead of adding a new one.

While looking at this code, there was a stale comment that these
instructions were only used for disassembly.  This probably used to
be the case, but they are now used in the 'ARM load / store optimization pass' too.

This reapplies r242300 which was reverted in r242428 due to bot failures.

Ultimately those failures were spurious and completely unrelated to this commit.  I reverted this
at the time because it was thought to be at fault.

llvm-svn: 250969
2015-10-22 01:48:57 +00:00
David Majnemer a8f17871e4 [WinEH] Remove extraneous call to emitEHRegistrationOffsetLabel
It's a relic from the earlier implementation, let's remove it.

llvm-svn: 250964
2015-10-21 23:20:39 +00:00
Matt Arsenault 391be09ef3 AMDGPU: Fix adding redundant m0 uses
BuildMI already adds these since they are defined correctly now.

llvm-svn: 250961
2015-10-21 22:37:51 +00:00
Matt Arsenault e8c0891e42 AMDGPU: Fix verifier error in SIFoldOperands
There may be other use operands that also need their kill flags cleared.

This happens in a few tests when SIFoldOperands is moved after
PeepholeOptimizer.

PeepholeOptimizer rewrites cases that look like:
%vreg0 = ...
%vreg1 = COPY %vreg0
use %vreg1<kill>
%vreg2 = COPY %vreg0
use %vreg2<kill>

to use the earlier source to
%vreg0 = ...
use %vreg0
use %vreg0

Currently SIFoldOperands sees the copied registers, so there is
only one use. So far I haven't managed to come up with a test
that currently has multiple uses of a foldable VGPR -> VGPR copy.

llvm-svn: 250960
2015-10-21 22:37:50 +00:00
Matt Arsenault b6fd98c7d9 AMDGPU: Split DiagnosticInfoUnsupported into its own file
llvm-svn: 250959
2015-10-21 22:37:46 +00:00
Matt Arsenault 6005fcbe12 AMDGPU: Simplify VOP3 operand legalization.
This was checking for a variety of situations that should
never happen. This saves a tiny bit of compile time.

We should not be selecting instructions with invalid operands in the
first place. Most of the time for registers copys are inserted
to the correct operand register class.

For VOP3, since all operand types are supported and literal
constants never are, we just need to verify the constant bus
requirements (all immediates should be legal inline ones).

The only possibly tricky case to maybe worry about is if when
legalizing operands in moveToVALU with s_add_i32 and similar
instructions. If the original s_add_i32 had a literal constant
and we need to replace it with v_add_i32_e64 we would have an
unsupported literal operand.  However, I don't think we should worry
about that because SIFoldOperands should handle folding literal
constant operands into the SALU instructions based on the uses.
At SIFoldOperands time, the legality and profitability of
operand types is a bit different.

llvm-svn: 250951
2015-10-21 21:51:02 +00:00
Matt Arsenault e223cebd10 AMDGPU: Fix not checking implicit operands in verifyInstruction
When verifying constant bus restrictions, this wasn't catching
uses in implicit operands.

llvm-svn: 250948
2015-10-21 21:15:01 +00:00
Matt Arsenault 45cbfa5949 Use numeric_limits instead of LLONG_MAX
This is a build fix for configurations where LLONG_MAX is
not defined in system headers.

llvm-svn: 250946
2015-10-21 21:10:12 +00:00
Matt Arsenault 29f9663f97 LegalizeDAG: Implement promote for build_vector
This will be used in future commits for AMDGPU to promote
operations on i64 vectors into operations on 32-bit vector
components.

This will be used / tested in future AMDGPU commits.

llvm-svn: 250945
2015-10-21 21:10:10 +00:00
Vedant Kumar 029c35186e [Verifier] Minor comment update, NFC
llvm-svn: 250943
2015-10-21 20:33:31 +00:00
Keno Fischer ddad187ce7 [RuntimeDyld] Ignore ST_FILE symbols when constructing GlobalSymbolTable
Summary: ELF's STT_File symbols may overlap with regular globals in
other files, so we should ignore them here in order to avoid having
bogus entries in the symbol table that confuse us when resolving relocations.

Reviewers: lhames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13888

llvm-svn: 250942
2015-10-21 20:22:04 +00:00
Joerg Sonnenberger 7212809abc Drop assert that a call with struct return goes to a function with sret
attribute. Clang incorrectly misses it on __muldc3 and friends and the
type system doesn't include it properly either.

llvm-svn: 250938
2015-10-21 20:05:01 +00:00
Teresa Johnson c8a8a5e2ae Silence Visual C++ warning in function summary parsing code (NFC)
llvm-svn: 250929
2015-10-21 19:25:14 +00:00
Sanjay Patel efab8b0d08 [x86] move recursive add match for LEA to helper function; NFCI
llvm-svn: 250926
2015-10-21 18:56:06 +00:00
David Majnemer dc3b67b4ca [SimplifyCFG] Don't use-after-free an SSA value
SimplifyTerminatorOnSelect didn't consider the possibility that the
condition might be related to one of PHI nodes.

This fixes PR25267.

llvm-svn: 250922
2015-10-21 18:22:24 +00:00
Craig Topper 896c267544 [X86] Add AMD mwaitx, monitorx, and clzero instructions to the assembly parser and disassembler.
llvm-svn: 250911
2015-10-21 17:26:45 +00:00
Kevin Enderby da9dd05011 Backing out commit r250906 as it broke lld.
llvm-svn: 250908
2015-10-21 17:13:20 +00:00
Kevin Enderby e3bf4fd546 This removes the eating of the error in Archive::Child::getSize() when the characters
in the size field in the archive header for the member is not a number.  To do this we
have all of the needed methods return ErrorOr to push them up until we get out of lib.
Then the tools and can handle the error in whatever way is appropriate for that tool.

So the solution is to plumb all the ErrorOr stuff through everything that touches archives.
This include its iterators as one can create an Archive object but the first or any other
Child object may fail to be created due to a bad size field in its header.

Thanks to Lang Hames on the changes making child_iterator contain an
ErrorOr<Child> instead of a Child and the needed changes to ErrorOr.h to add
operator overloading for * and -> .

We don’t want to use llvm_unreachable() as it calls abort() and is produces a “crash”
and using report_fatal_error() to move the error checking will cause the program to
stop, neither of which are really correct in library code. There are still some uses of
these that should be cleaned up in this library code for other than the size field.

Also corrected the code where the size gets us to the “at the end of the archive”
which is OK but past the end of the archive will return object_error::parse_failed now.

The test cases use archives with text files so one can see the non-digit character,
in this case a ‘%’, in the size field.

llvm-svn: 250906
2015-10-21 16:59:24 +00:00
Craig Topper 8ea2390c35 [Option] Use an ArrayRef to store the Option Infos in OptTable. NFC
llvm-svn: 250901
2015-10-21 16:30:42 +00:00
Daniel Sanders d6cf3e05ef [mips][mips16] Re-work the inline assembly stubs to work with IAS. NFC.
Summary:
Previously, we were inserting an InlineAsm statement for each line of the
inline assembly. This works for GAS but it triggers prologue/epilogue
emission when IAS is in use. This caused:
    .set noreorder
    .cpload $25
to be emitted as:
    .set push
    .set reorder
    .set noreorder
    .set pop
    .set push
    .set reorder
    .cpload $25
    .set pop
which led to assembler errors and caused the test to fail.

The whitespace-after-comma changes included in this patch are necessary to
match the output when IAS is in use.

Reviewers: vkalintiris

Subscribers: rkotler, llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D13653

llvm-svn: 250895
2015-10-21 12:44:14 +00:00
Chandler Carruth 2be10754a9 [AA] Enhance the new AliasAnalysis infrastructure with an optional
"external" AA wrapper pass.

This is a generic hook that can be used to thread custom code into the
primary AAResultsWrapperPass for the legacy pass manager in order to
allow it to merge external AA results into the AA results it is
building. It does this by threading in a raw callback and so it is
*very* powerful and should serve almost any use case I have come up with
for extending the set of alias analyses used. The only thing not well
supported here is using a *different order* of alias analyses. That form
of extension *is* supportable with the new pass manager, and I can make
the callback structure here more elaborate to support it in the legacy
pass manager if this is a critical use case that people are already
depending on, but the only use cases I have heard of thus far should be
reasonably satisfied by this simpler extension mechanism.

It is hard to test this using normal facilities (the built-in AAs don't
use this for obvious reasons) so I've written a fairly extensive set of
custom passes in the alias analysis unit test that should be an
excellent test case because it models the out-of-tree users: it adds
a totally custom AA to the system. This should also serve as
a reasonably good example and guide for out-of-tree users to follow in
order to rig up their existing alias analyses.

No support in opt for commandline control is provided here however. I'm
really unhappy with the kind of contortions that would be required to
support that. It would fully re-introduce the analysis group
self-recursion kind of patterns. =/

I've heard from out-of-tree users that this will unblock their use cases
with extending AAs on top of the new infrastructure and let us retain
the new analysis-group-free-world.

Differential Revision: http://reviews.llvm.org/D13418

llvm-svn: 250894
2015-10-21 12:15:19 +00:00
Elena Demikhovsky 3ad76a1acd Masked Load/Store optimization for scalar code
When we have to convert the masked.load, masked.store to scalar code, we generate a chain of conditional basic blocks.
I added optimization for constant mask vector.

Differential Revision: http://reviews.llvm.org/D13855

llvm-svn: 250893
2015-10-21 11:50:54 +00:00
Daniel Sanders 0f596814e9 [mips][msa] Remove copy_u.d and move copy_u.w to MSA64.
Summary:
The forwards compatibility strategy employed by MIPS is to consider registers
to be infinitely sign-extended. Then on ISA's with a wider register, the result
of existing instructions are sign-extended to register width and zero-extended
counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this
strategy and we have therefore corrected the MSA specs to fix this.

We still keep track of sign/zero-extension during legalization but we now
match copy_s.[wd] where required.

No change required to clang since __builtin_msa_copy_u_[wd] will map to
copy_s.[wd] where appropriate for the target.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13472

llvm-svn: 250887
2015-10-21 09:58:54 +00:00
Jonas Paulsson 17ad04535f Let MachineVerifier be aware of mem-to-mem instructions.
A mem-to-mem instruction (that both loads and stores), which store to an
FI, cannot pass the verifier since it thinks it is loading from the FI.

For the mem-to-mem instruction, do a looser check in visitMachineOperand()
and only check liveness at the reg-slot while analyzing a frame index operand.

Needed to make CodeGen/SystemZ/xor-01.ll pass with -verify-machineinstrs,
which now runs with this flag.

Reviewed by Evan Cheng and Quentin Colombet.

llvm-svn: 250885
2015-10-21 07:39:47 +00:00
Mehdi Amini 4215236621 Do not use `dyn_cast<X>` after `isa<X>` (NFC)
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 250883
2015-10-21 06:11:01 +00:00
Krzysztof Parzyszek fdb7b693a7 Tail duplication can mix incompatible registers in phi nodes
Do not tail duplicate blocks where the successor has a phi node,
and the corresponding value in that phi node uses a subregister.

http://reviews.llvm.org/D13922

llvm-svn: 250877
2015-10-21 02:40:06 +00:00
JF Bastien 1a59c6b2c9 WebAssembly: support imports
C/C++ code can declare an extern function, which will show up as an import in WebAssembly's output. It's expected that the linker will resolve these, and mark unresolved imports as call_import (I have a patch which does this in wasmate).

llvm-svn: 250875
2015-10-21 02:23:09 +00:00
Dehao Chen 100424124b Tolerate negative offset when matching sample profile.
In some cases (as illustrated in the unittest), lineno can be less than the heade_lineno because the function body are included from some other files. In this case, offset will be negative. This patch makes clang still able to match the profile to IR in this situation.

http://reviews.llvm.org/D13914

llvm-svn: 250873
2015-10-21 01:22:27 +00:00
Krzysztof Parzyszek ced9941cd4 [Hexagon] Bit-based instruction simplification
Analyze bit patterns of operands and values of instructions to perform
various simplifications, dead/redundant code elimination, etc.

llvm-svn: 250868
2015-10-20 22:57:13 +00:00
Krzysztof Parzyszek 26b2c9080f [Hexagon] Fix isNVStorable flag in .td files
An upper half and a double word cannot be used as value sources in a
new-value store.

llvm-svn: 250867
2015-10-20 22:40:57 +00:00
Igor Laevsky 68688df94c [MemorySanitizer] NFC. Do not use GET_INTRINSIC_MODREF_BEHAVIOR table.
It is now possible to infer intrinsic modref behaviour purely from intrinsic attributes.
This change will allow to completely remove GET_INTRINSIC_MODREF_BEHAVIOR table.

Differential Revision: http://reviews.llvm.org/D13907

llvm-svn: 250860
2015-10-20 21:33:30 +00:00
Krzysztof Parzyszek 79512b88b0 [Hexagon] Capture aggregate variables by reference, not value
llvm-svn: 250851
2015-10-20 19:33:46 +00:00
Krzysztof Parzyszek e4cff4058c [Hexagon] Do not fall-through if there is no CFG edge
llvm-svn: 250850
2015-10-20 19:30:21 +00:00
Krzysztof Parzyszek bfe8e92fd1 [Hexagon] Use symbolic name for subregister instead of hardcoded number
llvm-svn: 250849
2015-10-20 19:26:36 +00:00
Krzysztof Parzyszek 0257905f27 [Hexagon] Change Based->Base in getBasedWithImmOffset
llvm-svn: 250848
2015-10-20 19:21:05 +00:00
Krzysztof Parzyszek 05da79d5ac [Hexagon] Remove the remnants of isConstExtProfitable
llvm-svn: 250845
2015-10-20 19:04:53 +00:00
Artyom Skrobov c736863a85 Two switch blocks in VectorLegalizer::LegalizeOp already have a
default: llvm_unreachable("This action is not supported yet!");

-- so I'm adding one to the third switch block, too.

This is a follow-up fix for http://reviews.llvm.org/D13862

llvm-svn: 250830
2015-10-20 15:06:37 +00:00
Jonas Paulsson 4b29f6f7f7 [SystemZ] Use LivePhysRegs helper class in SystemZShortenInst.cpp.
Don't use home brewed liveness tracking code for phys regs, since
this class does the job.

Reviewed by Ulrich Weigand.

llvm-svn: 250829
2015-10-20 15:05:58 +00:00
Artyom Skrobov 7fd67e25aa Adding support for TargetLoweringBase::LibCall
Summary:
TargetLoweringBase::Expand is defined as "Try to expand this to other ops,
otherwise use a libcall." For ISD::UDIV and ISD::SDIV, the choice between
the two possibilities was defined in a rather convoluted way:

- if DIVREM is legal, expand to DIVREM
- if DIVREM has a custom lowering, expand to DIVREM
- if DIVREM libcall is defined and a remainder from the same division is
  computed elsewhere, expand to a DIVREM libcall
- else, expand to a DIV libcall

This had the undesirable effect that if both DIV and DIVREM are implemented
as libcalls, then ISD::UDIV and ISD::SDIV are expanded to the heavier DIVREM
libcall, even when the remainder isn't used.

The new code adds a new LegalizeAction, TargetLoweringBase::LibCall, so that
backends can directly control whether they prefer an expansion or a conversion
to a libcall. This makes the generic lowering code even more generic,
allowing its reuse in a wider range of target-specific configurations.

The useful effect is that ARM backend will now generate a call
to __aeabi_{i,u}div rather than __aeabi_{i,u}divmod in cases where
it doesn't need the remainder. There's no functional change outside
the ARM backend.

Reviewers: t.p.northover, rengolin

Subscribers: t.p.northover, llvm-commits, aemerson

Differential Revision: http://reviews.llvm.org/D13862

llvm-svn: 250826
2015-10-20 13:14:52 +00:00
Artyom Skrobov b844fa7fc0 Combining DIV+REM->DIVREM doesn't belong in LegalizeDAG; move it over into DAGCombiner.
Summary:
In addition to moving the code over, this patch amends the DIV,REM -> DIVREM
combining to run on all affected nodes at once: if the nodes are converted
to DIVREM one at a time, then the resulting DIVREM may get legalized by the
backend into something target-specific that we won't be able to recognize
and correlate with the remaining nodes.

The motivation is to "prepare terrain" for D13862: when we set DIV and REM
to be legalized to libcalls, instead of the DIVREM, we otherwise lose the
ability to combine them together. To prevent this, we need to take the
DIV,REM -> DIVREM combining out of the lowering stage.

Reviewers: RKSimon, eli.friedman, rengolin

Subscribers: john.brawn, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D13733

llvm-svn: 250825
2015-10-20 13:06:02 +00:00
Igor Breger 21296d230a AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions.
Differential Revision: http://reviews.llvm.org/D13884

llvm-svn: 250819
2015-10-20 11:56:42 +00:00
Keno Fischer a010cfa592 Fix missing INITIALIZE_PASS_DEPENDENCY for AddressSanitizer
Summary: In r231241, TargetLibraryInfoWrapperPass was added to
`getAnalysisUsage` for `AddressSanitizer`, but the corresponding
`INITIALIZE_PASS_DEPENDENCY` was not added.

Reviewers: dvyukov, chandlerc, kcc

Subscribers: kcc, llvm-commits

Differential Revision: http://reviews.llvm.org/D13629

llvm-svn: 250813
2015-10-20 10:13:55 +00:00
Matt Arsenault 3add6439d0 AMDGPU: Add MachineInstr overloads for instruction format tests
llvm-svn: 250797
2015-10-20 04:35:43 +00:00
Matt Arsenault 8f18917a90 AMDGPU: Stop reserving v[254:255]
This wasn't doing anything useful. They weren't explicitly used
anywhere, and the RegScavenger ignores reserved registers.

This for some reason caused a random scheduling change in the test.
Getting the check lines to pass is too frustrating, and there's probably
not too much value in checking the vector case's operands N times.

llvm-svn: 250794
2015-10-20 03:59:58 +00:00
JF Bastien c8f89e86d5 WebAssembly: fix call/return syntax.
They are now typeless, unlike other operations.

llvm-svn: 250793
2015-10-20 01:26:54 +00:00
Duncan P. N. Exon Smith c4829deae8 MSP430: Remove implicit ilist iterator conversions, NFC
llvm-svn: 250792
2015-10-20 01:18:39 +00:00
Duncan P. N. Exon Smith ac331fbdb6 AsmParser: Remove implicit ilist iterator conversions, NFC
llvm-svn: 250791
2015-10-20 01:12:49 +00:00
Duncan P. N. Exon Smith a2c90e4743 SystemZ: Remove implicit ilist iterator conversion, NFC
llvm-svn: 250790
2015-10-20 01:12:46 +00:00
Duncan P. N. Exon Smith 0ce253d3a9 XCore: Remove implicit ilist iterator conversions, NFC
llvm-svn: 250788
2015-10-20 01:07:42 +00:00
Duncan P. N. Exon Smith ac65b4c422 PowerPC: Remove implicit ilist iterator conversions, NFC
llvm-svn: 250787
2015-10-20 01:07:37 +00:00
Sanjoy Das 3020b1bc8c [RS4GC] Remove a redundant linear search, NFCI
Since LiveVariables is uniqued (we just created it from a `DenseSet`),
`FindIndex(LiveVariables, LiveVariables[i])` is always `i`.

llvm-svn: 250786
2015-10-20 01:06:31 +00:00
Sanjoy Das b1942f14cd [RS4GC] Clean up `find_index`; NFC
- Bring it up to the LLVM Coding Style
 - Sink it inside `CreateGCRelocates`, which is its only user

llvm-svn: 250785
2015-10-20 01:06:28 +00:00
Sanjoy Das 7ad67640e9 [RS4GC] Re-purpose `normalizeForInvokeSafepoint`; NFC.
`normalizeForInvokeSafepoint` in RewriteStatepointsForGC.cpp, as it is
written today, deals with `gc.relocate` and `gc.result` uses of a
statepoint equally well.  This change documents this fact and adds a
test case.

There is no functional change here -- only documentation of existing
functionality.

llvm-svn: 250784
2015-10-20 01:06:24 +00:00
Sanjoy Das ff3dba736a [RS4GC] Minor cleanup to `normalizeForInvokeSafepoint`; NFC
llvm-svn: 250783
2015-10-20 01:06:17 +00:00
Duncan P. N. Exon Smith c3f7988472 Sparc: Remove implicit ilist iterator conversions, NFC
llvm-svn: 250781
2015-10-20 00:59:43 +00:00
Duncan P. N. Exon Smith 61149b86c3 NVPTX: Remove implicit ilist iterator conversions, NFC
llvm-svn: 250779
2015-10-20 00:54:09 +00:00
Duncan P. N. Exon Smith a72c6e25ec Hexagon: Remove implicit ilist iterator conversions, NFC
There are two things out of the ordinary in this commit.  First, I made
a loop obviously "infinite" in HexagonInstrInfo.cpp.  After checking if
an instruction was at the beginning of a basic block (in which case,
`break`), the loop decremented and checked the iterator for `nullptr` as
the loop condition.  This has never been possible (the prev pointers are
always been circular, so even with the weird ilist/iplist
implementation, this isn't been possible), so I removed the condition.

Second, in HexagonAsmPrinter.cpp there was another case of comparing a
`MachineBasicBlock::instr_iterator` against `MachineBasicBlock::end()`
(which returns `MachineBasicBlock::iterator`).  While not incorrect,
it's fragile.  I switched this to `::instr_end()`.

All that said, no functionality change intended here.

llvm-svn: 250778
2015-10-20 00:46:39 +00:00
JF Bastien 3b0177c542 WebAssembly: fix syntax for br_if.
llvm-svn: 250777
2015-10-20 00:37:42 +00:00
Duncan P. N. Exon Smith a25ad0685a AsmPrinter: Remove implicit ilist iterator conversion, NFC
llvm-svn: 250776
2015-10-20 00:36:08 +00:00
Duncan P. N. Exon Smith 7869148c47 Mips: Remove implicit ilist iterator conversions, NFC
llvm-svn: 250769
2015-10-20 00:15:20 +00:00
Duncan P. N. Exon Smith 19d951874a CppBackend: Remove implicit ilist iterator conversions, NFC
Mostly just converted to range-based for loops.  May have converted a
couple of extra loops as a drive-by (not sure).

llvm-svn: 250766
2015-10-20 00:06:41 +00:00
Duncan P. N. Exon Smith d95fa4ccf1 BPF: Remove implicit ilist iterator conversion, NFC
llvm-svn: 250765
2015-10-20 00:02:50 +00:00
Duncan P. N. Exon Smith 9f9559e807 ARM: Remove implicit ilist iterator conversions, NFC
llvm-svn: 250759
2015-10-19 23:25:57 +00:00
Duncan P. N. Exon Smith 1e59a66c69 ObjCARC: Remove implicit ilist iterator conversions, NFC
llvm-svn: 250756
2015-10-19 23:20:14 +00:00
Cong Hou 7745dbc5c4 Enhance loop rotation with existence of profile data in MachineBlockPlacement pass.
Currently, in MachineBlockPlacement pass the loop is rotated to let the best exit to be the last BB in the loop chain, to maximize the fall-through from the loop to outside. With profile data, we can determine the cost in terms of missed fall through opportunities when rotating a loop chain and select the best rotation. Basically, there are three kinds of cost to consider for each rotation:

1. The possibly missed fall through edge (if it exists) from BB out of the loop to the loop header.
2. The possibly missed fall through edges (if they exist) from the loop exits to BB out of the loop.
3. The missed fall through edge (if it exists) from the last BB to the first BB in the loop chain.

Therefore, the cost for a given rotation is the sum of costs listed above. We select the best rotation with the smallest cost. This is only for PGO mode when we have more precise edge frequencies.

Differential revision: http://reviews.llvm.org/D10717

llvm-svn: 250754
2015-10-19 23:16:40 +00:00
Duncan P. N. Exon Smith 9934b26b0f Linker: Remove implicit ilist iterator conversion, NFC
llvm-svn: 250748
2015-10-19 22:23:36 +00:00
David Blaikie 437aafdab2 Fix -Wdeprecated regarding ORC copying ValueMaterializers
As usual, this is a polymorphic hierarchy without polymorphic ownership,
so simply make the dtor protected non-virtual, protected default copy
ctor/assign, and make derived classes final. The derived classes will
pick up correct default public copy ops (and dtor) implicitly.

(wish I could add -Wdeprecated to the build, but last time I tried it
triggered on some system headers I still need to look into/figure out)

llvm-svn: 250747
2015-10-19 22:15:55 +00:00
Michael Liao c65d386b81 [InstCombine] Optimize icmp of inc/dec at RHS
Allow LLVM to optimize the sequence like the following:

  %inc = add nsw i32 %i, 1
  %cmp = icmp slt %n, %inc

into:

  %cmp = icmp sle i32 %n, %i

The case is not handled previously due to the complexity of compuation of %n.
Hence, LLVM cannot swap operands of icmp accordingly.

llvm-svn: 250746
2015-10-19 22:08:14 +00:00
Duncan P. N. Exon Smith 6b92a14a28 Vectorize: Remove implicit ilist iterator conversions, NFC
Besides the usual, I finally added an overload to
`BasicBlock::splitBasicBlock()` that accepts an `Instruction*` instead
of `BasicBlock::iterator`.  Someone can go back and remove this overload
later (after updating the callers I'm going to skip going forward), but
the most common call seems to be
`BB->splitBasicBlock(BB->getTerminator(), ...)` and I'm not sure it's
better to add `->getIterator()` to every one than have the overload.
It's pretty hard to get the usage wrong.

llvm-svn: 250745
2015-10-19 22:06:09 +00:00
Sanjay Patel 69a50a1e17 [CGP] transform select instructions into branches and sink expensive operands
This was originally checked in at r250527, but reverted at r250570 because of PR25222.
There were at least 2 problems: 
1. The cost check was checking for an instruction with an exact cost of TCC_Expensive;
that should have been >=.
2. The cause of the clang stage 1 failures was illegally sinking 'call' instructions;
we can't sink instructions that may have side effects / are not safe to execute speculatively.

Fixed those conditions in sinkSelectOperand() and added test cases.

Original commit message:
This is a follow-up to the discussion in D12882.

Ideally, we would like SimplifyCFG to be able to form select instructions even when the operands
are expensive (as defined by the TTI cost model) because that may expose further optimizations.
However, we would then like a later pass like CodeGenPrepare to undo that transformation if the
target would likely benefit from not speculatively executing an expensive op (this patch).

Once we have this safety mechanism in place, we can adjust SimplifyCFG to restore its
select-formation behavior that changed with r248439.

Differential Revision: http://reviews.llvm.org/D13297

llvm-svn: 250743
2015-10-19 21:59:12 +00:00
Duncan P. N. Exon Smith d77de6495e X86: Remove implicit ilist iterator conversions, NFC
llvm-svn: 250741
2015-10-19 21:48:29 +00:00
Lang Hames f1381cb8d0 [RuntimeDyld][COFF] Fix some endianness issues, re-enable the regression test.
llvm-svn: 250733
2015-10-19 20:37:52 +00:00
Owen Anderson faf5187ee0 Restore the original behavior of SelectionDAG::getTargetIndex().
It looks like an extra negation snuck in as apart of restoring it.

llvm-svn: 250726
2015-10-19 19:27:40 +00:00
Krzysztof Parzyszek 055c5fd74e [Hexagon] Remove unnecessary argument sign extends
llvm-svn: 250724
2015-10-19 19:10:48 +00:00
Teresa Johnson 3da931f87a Pass FunctionInfoIndex by reference to WriteFunctionSummaryToFile (NFC)
Implemented suggestion by dblakie in review for r250704.

llvm-svn: 250723
2015-10-19 19:06:06 +00:00
Benjamin Kramer 755e502952 Add missing override noticed by Clang's -Winconsistent-missing-override.
llvm-svn: 250720
2015-10-19 18:41:23 +00:00
Jun Bum Lim d3548303ec [AArch64]Merge halfword loads into a 32-bit load
Convert two halfword loads into a single 32-bit word load with bitfield extract
instructions. For example :
  ldrh w0, [x2]
  ldrh w1, [x2, #2]
becomes
  ldr w0, [x2]
  ubfx w1, w0, #16, #16
  and  w0, w0, #ffff

llvm-svn: 250719
2015-10-19 18:34:53 +00:00
Krzysztof Parzyszek 23920ec95d [Hexagon] Fix debug information for local objects
- Isolate the check for the existence of a stack frame into hasFP.
- Implement getFrameIndexReference for DWARF address computation.
- Use getFrameIndexReference for offset computation in eliminateFrameIndex.
- Preserve debug information for dynamically allocated stack objects.
- Prefer FP to access local objects at -O0.
- Add experimental code to skip allocframe when not strictly necessary
  (disabled by default).

llvm-svn: 250718
2015-10-19 18:30:27 +00:00
Benjamin Kramer 2002aadaad Put back SelectionDAG::getTargetIndex.
While technically this is untested dead code, it has out-of-tree users.
This reverts a part of r250434.

llvm-svn: 250717
2015-10-19 18:26:16 +00:00
Krzysztof Parzyszek db8677067c [Hexagon] Delay emission of CFI instructions
Emit the CFI instructions after all code transformation have been done.
This will avoid any interference between CFI instructions and packetization.

llvm-svn: 250714
2015-10-19 17:46:01 +00:00
Matthias Braun e734195ce3 Revert "RegisterPressure: allocatable physreg uses are always kills"
This reverts commit r250596.

Reverted for now as the commit triggers assert in the AMDGPU target
pending investigation.

llvm-svn: 250713
2015-10-19 17:44:22 +00:00
Lang Hames 98c2ac13d3 [Orc] Add support for emitting indirect stubs directly into the JIT target's
memory, rather than representing the stubs in IR. Update the CompileOnDemand
layer to use this functionality.

Directly emitting stubs is much cheaper than building them in IR and codegen'ing
them (see below). It also plays well with remote JITing - stubs can be emitted
directly in the target process, rather than having to send them over the wire.

The downsides are:

(1) Care must be taken when resolving symbols, as stub symbols are held in a
    separate symbol table. This is only a problem for layer writers and other
    people using this API directly. The CompileOnDemand layer hides this detail.

(2) Aliases of function stubs can't be symbolic any more (since there's no
    symbol definition in IR), but must be converted into a constant pointer
    expression. This means that modules containing aliases of stubs cannot be
    cached. In practice this is unlikely to be a problem: There's no benefit to
    caching such a module anyway.

On balance I think the extra performance is more than worth the trade-offs: In a
simple stress test with 10000 dummy functions requiring stubs and a single
executed "hello world" main function, directly emitting stubs reduced user time
for JITing / executing by over 90% (1.5s for IR stubs vs 0.1s for direct
emission).

llvm-svn: 250712
2015-10-19 17:43:51 +00:00
Benjamin Kramer 335332329b Remove CRLF newlines. NFC.
llvm-svn: 250698
2015-10-19 13:05:25 +00:00
Asiri Rathnayake 1040a53be3 Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions
The mapping of these two intrinsics in ARMInstrInfo.td had a small
omission which lead to their operands not being validated/transformed
before being lowered into usat and ssat instructions. This can cause
incorrect instructions to be emitted.

I've also added tests for the remaining two saturating arithmatic
intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing
codegen tests.

llvm-svn: 250697
2015-10-19 11:44:24 +00:00
James Molloy 17379c4ea1 [GlobalsAA] Fix a really horrible iterator invalidation bug
We were keeping a reference to an object in a DenseMap then mutating it. At the end of the function we were attempting to clone that reference into other keys in the DenseMap, but DenseMap may well decide to resize its hashtable which would invalidate the reference!

It took an extremely complex testcase to catch this - many thanks to Zhendong Su for catching it in PR25225.

This fixes PR25225.

llvm-svn: 250692
2015-10-19 08:54:59 +00:00
Elena Demikhovsky 20662e39f1 Removed parameter "Consecutive" from isLegalMaskedLoad() / isLegalMaskedStore().
Originally I planned to use the same interface for masked gather/scatter and set isConsecutive to "false" in this case.

Now I'm implementing masked gather/scatter and see that the interface is inconvenient. I want to add interfaces isLegalMaskedGather() / isLegalMaskedScatter() instead of using the "Consecutive" parameter in the existing interfaces.

Differential Revision: http://reviews.llvm.org/D13850

llvm-svn: 250686
2015-10-19 07:43:38 +00:00
Zlatko Buljan 5292083584 [mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions
Differential Revision: http://reviews.llvm.org/D13130

llvm-svn: 250685
2015-10-19 07:16:26 +00:00
Zlatko Buljan d0a7d6e4ee [mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions
Differential Revision: http://reviews.llvm.org/D13721

llvm-svn: 250683
2015-10-19 06:34:44 +00:00
Xinliang David Li aa0592cc70 [PGO] Eliminate prof data register calls on FreeBSD platform
This is a follow up patch of r250199 after verifying the start/stop
section symbols work as spected on FreeBSD.

llvm-svn: 250679
2015-10-19 04:17:10 +00:00
Jakub Staszak f12821a43c Preserve CFG in MergedLoadStoreMotion. This fixes PR24426.
llvm-svn: 250660
2015-10-18 19:34:10 +00:00
Simon Pilgrim 04d52d26f6 Use SDValue bool check. NFCI.
llvm-svn: 250653
2015-10-18 12:33:54 +00:00
Simon Pilgrim c2c154e078 Move one-use variable inside test. NFC.
llvm-svn: 250651
2015-10-18 11:47:23 +00:00
Asaf Badouh 696e8e0bb7 [X86][AVX512DQ] add scalar fpclass
Differential Revision: http://reviews.llvm.org/D13769

llvm-svn: 250650
2015-10-18 11:04:38 +00:00
Igor Breger cbb9550537 AVX512: Lowering i8/i16 vector CTLZ using the dword LZCNT vector instruction
Differential Revision: http://reviews.llvm.org/D13632

llvm-svn: 250649
2015-10-18 09:56:39 +00:00
Craig Topper 92cfdd70f8 [Sparc] Use MCPhysReg instead of unsigned to size static arrays of registers. Should reduce the table size.
llvm-svn: 250644
2015-10-18 05:29:05 +00:00