f2619ee3ff
Fill delay slot with useful instructions. Modified from Sparc's version of delay
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slot filler.
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140825
2011-09-29 23:52:13 +00:00
69bc3de4fc
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
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llvm-svn: 140824
2011-09-29 23:50:42 +00:00
a1127b2fa2
Support creating a constant pool value for a machine basic block.
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This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.
llvm-svn: 140823
2011-09-29 23:48:44 +00:00
a3e7ffdae8
Fold two identical set lookups into one. No functionality change.
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llvm-svn: 140821
2011-09-29 23:40:12 +00:00
4ac148dcbc
When eliminating unnecessary retain+autorelease on return values,
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handle the case where the retain is in a different basic block.
rdar://10210274.
llvm-svn: 140815
2011-09-29 22:27:34 +00:00
2053a5dd64
Don't eliminate objc_retainBlock calls on stack objects if the
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objc_retainBlock call is potentially responsible for copying
the block to the heap to extend its lifetime. rdar://10209613.
llvm-svn: 140814
2011-09-29 22:25:23 +00:00
36036412e2
Mips64 arithmetic and logical instructions with two source registers.
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llvm-svn: 140806
2011-09-29 20:37:56 +00:00
95031ed837
Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy.
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llvm-svn: 140803
2011-09-29 20:21:17 +00:00
a9e8a2504c
Cosmetic changes, as per Nick's review.
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llvm-svn: 140785
2011-09-29 16:46:47 +00:00
cac86805bf
Place this bracket according to the LLVM style.
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llvm-svn: 140784
2011-09-29 16:01:46 +00:00
abcc57669d
PTX: Fix broken shared library build
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llvm-svn: 140783
2011-09-29 14:25:48 +00:00
dd1904e7a6
Expand the x86 V_SET0* pseudos right after register allocation.
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This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.
llvm-svn: 140776
2011-09-29 05:10:54 +00:00
15b3c9c684
Target/ARM: Unbreak! CMake! Build!
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llvm-svn: 140774
2011-09-29 03:32:49 +00:00
bf64024a39
Delete NEONMoveFix, now unused.
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llvm-svn: 140773
2011-09-29 02:56:45 +00:00
f7ad189033
Use ExecutionDepsFix instead of NEONMoveFix.
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This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
llvm-svn: 140772
2011-09-29 02:48:41 +00:00
168dfffdb8
typo + pasto
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llvm-svn: 140769
2011-09-29 01:53:08 +00:00
463b05a2d0
Remove NumImplicitOps which is now unused.
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llvm-svn: 140767
2011-09-29 01:47:36 +00:00
bc6de90a5f
LSR: rewrite inner loops only.
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Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.
llvm-svn: 140762
2011-09-29 01:33:38 +00:00
a0d5f268a9
Move to ISelLowering.
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llvm-svn: 140754
2011-09-29 01:13:55 +00:00
fd47d8af8b
PTX: Add new patterns for bitconvert and any_extend
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llvm-svn: 140753
2011-09-29 01:13:12 +00:00
d299dccf91
Use the local we already set up.
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llvm-svn: 140745
2011-09-29 00:50:59 +00:00
2318d1e0e9
Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.
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The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.
This also fixes a bug when adding operands after an implicit operand has
been added manually. The NumImplicitOps count wasn't kept up to date.
MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added. It is possible to change an MI opcode and add additional
explicit operands. They will be inserted before any existing implicit
operands.
The only exception is inline asm instructions where operands are never
reordered. This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.
llvm-svn: 140744
2011-09-29 00:40:51 +00:00
6728958279
Revert r140731, "Define classes for unary and binary FP instructions and use them to define"
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It broke the unit tests. Please reapply with tests fixed.
llvm-svn: 140735
2011-09-28 23:59:28 +00:00
8156376aa9
Tighten a ARM dag combine condition to avoid an identity transformation, which
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ends up introducing a cycle in the DAG.
rdar://10196296
llvm-svn: 140733
2011-09-28 23:16:31 +00:00
5a1b4a80c3
Define classes for unary and binary FP instructions and use them to define
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multiclasses.
llvm-svn: 140731
2011-09-28 21:58:01 +00:00
899da52d60
Have the SjLjEHPrepare pass do some more heavy lifting.
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Upon further review, most of the EH code should remain written at the IR
level. The part which breaks SSA form is the dispatch table, so that part will
be moved to the back-end.
llvm-svn: 140730
2011-09-28 21:56:53 +00:00
2fb357a5b0
PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them.
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llvm-svn: 140723
2011-09-28 21:00:25 +00:00
800619f2bb
Object: Add isSection{Data,BSS}.
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llvm-svn: 140721
2011-09-28 20:57:30 +00:00
315b9573c6
Perform the lowering only if there are invokes.
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llvm-svn: 140719
2011-09-28 20:29:45 +00:00
dfe5acd34e
Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.
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llvm-svn: 140718
2011-09-28 20:29:28 +00:00
933d51682f
PTX: Fix alignment logic
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llvm-svn: 140709
2011-09-28 18:24:58 +00:00
6f37b4a5a5
Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.
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llvm-svn: 140705
2011-09-28 18:11:19 +00:00
edc172d4cc
Remove definitions of branch-on-FP-likely instructions. They are deprecated.
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llvm-svn: 140704
2011-09-28 17:56:55 +00:00
c117967b19
Mips64 predicate definitions. Patch by Liu.
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llvm-svn: 140703
2011-09-28 17:50:27 +00:00
ef8e4efff8
indvars: generalize SCEV getPreStartForSignExtend.
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Handle general Add expressions to avoid leaving around redundant
32-bit IVs.
llvm-svn: 140701
2011-09-28 17:02:54 +00:00
f3d1d4eb4b
PTX: MC-ize the PTX backend (patch 2 of N)
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Get rid of some of the no-longer-needed parts of PTXAsmPrinter.
llvm-svn: 140698
2011-09-28 14:32:06 +00:00
5e18b14ee2
PTX: MC-ize the PTX back-end (patch 1 of N)
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Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.
llvm-svn: 140697
2011-09-28 14:32:04 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
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Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
2e67937f76
A typeid of zero means a cleanup, not a catch. This case occurs
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when there is both a catch and a cleanup. Correct the comment.
llvm-svn: 140686
2011-09-28 09:13:02 +00:00
8747e3e7ea
PTX: Simplify code. No functionality change.
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llvm-svn: 140680
2011-09-28 04:32:36 +00:00
5d7a73fa8c
PTX: Pass param name strings per const reference.
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The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++)
llvm-svn: 140679
2011-09-28 04:08:02 +00:00
baf3941fde
Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.
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llvm-svn: 140678
2011-09-28 03:52:41 +00:00
225e8481b0
Bitcast the alloca to an i8* to match the intrinsic's signature.
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llvm-svn: 140677
2011-09-28 03:47:11 +00:00
66b110f571
Create and use an llvm.eh.sjlj.functioncontext intrinsic.
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This intrinsic is used to pass the index of the function context to the back-end
for further processing. The back-end is in charge of filling in the rest of the
entries.
llvm-svn: 140676
2011-09-28 03:36:43 +00:00
2e76ca9d9a
In the new EH model, setup the function context and the call site info.
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The DWARF exception pass uses the call site information, which is set up here. A
pre-RA pass is too late for it to use this information. So create and setup the
function context here, and then insert the call site values here (and map the
call sites for the DWARF EH pass). This is simpler than the original pass, and
doesn't make the CFG lose its SSA-ness.
It's a win-win-win-win-lose-win-win situation.
llvm-svn: 140675
2011-09-28 03:14:05 +00:00
e6138e3ad1
Don't conditionalize execution of the SjLj EH prepare pass.
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We may need an SjLj EH preparation pass for some call site information, at least
in the short term.
llvm-svn: 140674
2011-09-28 03:07:34 +00:00
e0e30532a5
indvars should hoist [sz]ext because licm is not rerun.
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llvm-svn: 140670
2011-09-28 01:35:36 +00:00
5f476dc3ef
PR10628: Fix getModRefInfo so it queries the underlying alias() implementation correctly while checking nocapture calls.
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llvm-svn: 140666
2011-09-28 00:34:27 +00:00
bd5109f14d
Rename class and clean up source.
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No functional change intended.
llvm-svn: 140664
2011-09-28 00:01:56 +00:00
934b7d7645
Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.
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I'll clean up the source in the next commit.
llvm-svn: 140663
2011-09-28 00:01:54 +00:00
Akira Hatanaka