Commit Graph

162882 Commits

Author SHA1 Message Date
Roman Lebedev 9792838905 [SelectionDAG][NFC] haveNoCommonBitsSet(): add FIXME notes
As suggested in https://reviews.llvm.org/D45631#1068338

llvm-svn: 330102
2018-04-15 18:59:38 +00:00
Roman Lebedev 620b3da38f [InstCombine] Simplify 'add' to 'or' if no common bits are set.
Summary:
In order to get the whole fold as specified in [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]],
let's first handle the simple straight-forward things.
Let's start with the `and` -> `or` simplification.

The one obvious thing missing here: the constant mask is not handled.
I have an idea how to handle it, but it will require some thinking,
and is not strictly required here, so i've left that for later.

https://rise4fun.com/Alive/Pkmg

Reviewers: spatel, craig.topper, eli.friedman, jingyue

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45631

llvm-svn: 330101
2018-04-15 18:59:33 +00:00
Roman Lebedev 25cbb62d18 [NFC] ConstantOffsetExtractor::CanTraceInto(): add FIXME: no tests
As suggested in https://reviews.llvm.org/D45631#1068338,
looking at haveNoCommonBitsSet() users, and *trying* to
show the change effect elsewhere.

llvm-svn: 330100
2018-04-15 18:59:27 +00:00
Andrea Di Biagio b9acf13907 [MC] Moved all the remaining logic that computed instruction latency and reciprocal throughput from TargetSchedModel to MCSchedModel.
TargetSchedModel now always delegates to MCSchedModel the computation of
instruction latency and reciprocal throughput.
No functional change intended.

llvm-svn: 330099
2018-04-15 17:32:17 +00:00
Sanjay Patel 6c3af659a2 [DAGCombiner, PowerPC] allow X - (fpext(-Y) --> X + fpext(Y) with multiple uses
This is a transform that I limited in instcombine in rL329821 because it was 
creating more instructions in IR when the cast has multiple uses.

But if the cast is free, then we can do the transform regardless of other
uses because it improves the potential throughput of the calculation by
removing a dependency on the fneg.

Differential Revision: https://reviews.llvm.org/D45598

llvm-svn: 330098
2018-04-15 16:43:48 +00:00
Sanjay Patel 34ea6cdfab [InstCombine] simplify more code for distributive property; NFCI
Also, fix capitalization to current style. Follow-up to:
rL330096

llvm-svn: 330097
2018-04-15 16:20:58 +00:00
Sanjay Patel f1aa0d7af2 [InstCombine] simplify code for distributive property; NFCI
llvm-svn: 330096
2018-04-15 15:39:57 +00:00
Jonas Devlieghere 6be1f01935 [Support] Extend WithColor helpers
Although printing warnings and errors to stderr is by far the most
common case, this patch makes it possible to specify any stream.

llvm-svn: 330094
2018-04-15 08:44:15 +00:00
Weiming Zhao 7c16977a8f NFC: Move ObjectMemoryBuffer to support
Summary:
Since the class is used by both MCJIT and LTO, it makes more sense to move it to Support lib.
This is a follow up patch to r329929 and https://reviews.llvm.org/D45244

Reviewers: bkramer, dblaikie

Reviewed By: bkramer

Subscribers: mehdi_amini, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D45606

llvm-svn: 330093
2018-04-15 05:17:14 +00:00
Jonas Devlieghere 84e99265d6 [DebugInfo] Use WithColor to print errors/warnings
Use the convenience methods from WithColor to consistently print errors
and warnings in libDebugInfo.

llvm-svn: 330092
2018-04-14 22:07:23 +00:00
Jonas Devlieghere 3072b130b2 [Support] Add convenience functions to WithColor. NFC.
Create convenience functions for printing error, warning and note to
stdout. Previously we had similar functions being used in dsymutil, but
given that this pattern is so common it makes sense to make it available
globally.

llvm-svn: 330091
2018-04-14 21:36:42 +00:00
Artur Gainullin f08da81de0 [X86] Tests for unsigned saturation downconvert detection.
One more test for smax(smin(x, C2), C1) pattern.

llvm-svn: 330090
2018-04-14 20:10:17 +00:00
Warren Ristow 8b2f27ce3a [InstCombine] Enable Add/Sub simplifications with only 'reassoc' FMF
These simplifications were previously enabled only with isFast(), but that
is more restrictive than required. Since r317488, FMF has 'reassoc' to
control these cases at a finer level.

llvm-svn: 330089
2018-04-14 19:18:28 +00:00
Artur Gainullin 2120d3eace [X86] Tests for unsigned saturation downconvert detection.
llvm-svn: 330088
2018-04-14 19:09:02 +00:00
Sanjay Patel 713f09d014 [InstCombine] add shift+logic tests (PR37098); NFC
It debateable whether instcombine should be in the business of
reassociation, but it is currently. 

These tests and PR37098 demonstrate a missing ability to do a 
simple reassociation that allows eliminating shifts. 

If we decide that functionality belongs somewhere else, then we 
should still have some tests to show that we've intentionally 
limited instcombine to *not* include this ability.

llvm-svn: 330086
2018-04-14 13:39:02 +00:00
Simon Pilgrim b8adf558f8 [X86][MMX] Set PAVG/PHADD/PMIN/PMAX/PSIGN instructions to use same scheduler classes as SSE/AVX
llvm-svn: 330085
2018-04-14 13:06:38 +00:00
Hiroshi Inoue ae17900997 [NFC] fix trivial typos in document and comments
"not not" -> "not" etc

llvm-svn: 330083
2018-04-14 08:59:00 +00:00
Tony Tye b6efb90717 [AMDGPU] Add gfx902 product names
Differential Revision: https://reviews.llvm.org/D45609

llvm-svn: 330081
2018-04-14 01:58:10 +00:00
Heejin Ahn 92401cc1cf [WebAssembly] Fix a bug in MachineBasicBlock::findDebugLoc() call
Summary:
InsertPos is within the bacic block `Header`, so `findDebugLoc()` should
be called on not `MBB` but `Header` instead.

Reviewers: yurydelendik

Subscribers: jfb, dschuff, aprantl, sbc100, jgravelle-google, sunfish, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D45648

llvm-svn: 330079
2018-04-14 00:12:12 +00:00
Craig Topper 95f421cfbf [X86] Add the bizarro movsww and movzww mnemonics for the disassembler.
The destination size of the movzx/movsx instruction is controlled by the normal operand size mechanisms. Only the input type is fixed.

This means that a 0x66 prefix on the encoding for zext/sext 16->32 should really produce a 16->16 instruction. Functionally this is equivalent to a GR16->GR16 move since bits 16 and above will be preserved. So nothing is actually extended.

llvm-svn: 330078
2018-04-13 23:57:54 +00:00
Tim Northover 271d3d2771 MachO: trap unreachable instructions
Debugability is more important than saving 4 bytes to let us to fall
through to nonense.

llvm-svn: 330073
2018-04-13 22:25:20 +00:00
Roman Lebedev 8db3e115e7 [InstCombine][NFC] masked-merge: add 'and' tests, too.
(and plain 'or', for completeness sake.)

After submitting D45631, i have realized that it will *already*
affect 'and' pattern, and it was obvious that there were no
good test patterns to show that.

Since the masked-merge.ll is getting kinda big,
unify naming schemes a bit, and split into 'xor'/'and'/'or'
testfiles, with the only difference being the last operation.

llvm-svn: 330072
2018-04-13 21:57:01 +00:00
Roman Tereshin dab10b5468 [DebugInfo][OPT] NFC follow-up on "Fixing a couple of DI duplication bugs of CloneModule"
llvm-svn: 330070
2018-04-13 21:23:11 +00:00
Roman Tereshin d769eb36ab [DebugInfo][OPT] Fixing a couple of DI duplication bugs of CloneModule
As demonstrated by the regression tests added in this patch, the
following cases are valid cases:

1. A Function with no DISubprogram attached, but various debug info
  related to its instructions, coming, for instance, from an inlined
  function, also defined somewhere else in the same module;
2. ... or coming exclusively from the functions inlined and eliminated
  from the module entirely.

The ValueMap shared between CloneFunctionInto calls within CloneModule
needs to contain identity mappings for all of the DISubprogram's to
prevent them from being duplicated by MapMetadata / RemapInstruction
calls, this is achieved via DebugInfoFinder collecting all the
DISubprogram's. However, CloneFunctionInto was missing calls into
DebugInfoFinder for functions w/o DISubprogram's attached, but still
referring DISubprogram's from within (case 1). This patch fixes that.

The fix above, however, exposes another issue: if a module contains a
DISubprogram referenced only indirectly from other debug info
metadata, but not attached to any Function defined within the module
(case 2), cloning such a module causes a DICompileUnit duplication: it
will be moved in indirecty via a DISubprogram by DebugInfoFinder first
(because of the first bug fix described above), without being
self-mapped within the shared ValueMap, and then will be copied during
named metadata cloning. So this patch makes sure DebugInfoFinder
visits DICompileUnit's referenced from DISubprogram's as it goes w/o
re-processing llvm.dbg.cu list over and over again for every function
cloned, and makes sure that CloneFunctionInto self-maps
DICompileUnit's referenced from the entire function, not just its own
DISubprogram attached that may also be missing.

The most convenient way of tesing CloneModule I found is to rely on
CloneModule call from `opt -run-twice`, instead of writing tedious
unit tests. That feature has a couple of properties that makes it hard
to use for this purpose though:

1. CloneModule doesn't copy source filename, making `opt -run-twice`
  report it as a difference.
2. `opt -run-twice` does the second run on the original module, not
  its clone, making the result of cloning completely invisible in opt's
  actual output with and without `-run-twice` both, which directly
  contradicts `opt -run-twice`s own error message.

This patch fixes this as well.

Reviewed By: aprantl

Reviewers: loladiro, GorNishanov, espindola, echristo, dexonsmith

Subscribers: vsk, debug-info, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D45593

llvm-svn: 330069
2018-04-13 21:22:24 +00:00
Krzysztof Parzyszek 4bdf1aa416 [Hexagon] Initial instruction cost model for auto-vectorization
llvm-svn: 330065
2018-04-13 20:46:50 +00:00
Peter Collingbourne ab40e44ba1 Revert r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses."
Caused a hang and eventually an assertion failure in LTO builds
of 7zip-benchmark on aarch64 iOS targets.
http://green.lab.llvm.org/green/job/lnt-ctmark-aarch64-O3-flto/2024/

llvm-svn: 330063
2018-04-13 20:21:00 +00:00
Krzysztof Parzyszek dfed941eec [LV] Introduce TTI::getMinimumVF
The function getMinimumVF(ElemWidth) will return the minimum VF for
a vector with elements of size ElemWidth bits. This value will only
apply to targets for which TTI::shouldMaximizeVectorBandwidth returns
true. The value of 0 indicates that there is no minimum VF.

Differential Revision: https://reviews.llvm.org/D45271

llvm-svn: 330062
2018-04-13 20:16:32 +00:00
Mandeep Singh Grang 0f035ebed2 [DebugInfo] Change std::sort to llvm::sort in response to r327219
r327219 added wrappers to std::sort which randomly shuffle the container before
sorting.  This will help in uncovering non-determinism caused due to undefined
sorting order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of
std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to
llvm::sort.  Refer the comments section in D44363 for a list of all the
required patches.

llvm-svn: 330061
2018-04-13 19:50:51 +00:00
Stefan Pintilie 118b8675c5 [Power9] Add the TLS store instructions to the Power 9 model
The Power 9 scheduler model should now include the TLS instructions.
We can now, once again, mark the model as complete.
From now on, if instructions are added to Power 9 but are not
added to the model the build should produce an error. Hopefully
that will alert the developer who is adding new instructions
that they should also be added to the scheulder model.

llvm-svn: 330060
2018-04-13 19:49:58 +00:00
Mandeep Singh Grang 636d94db3b [Transforms] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: kcc, pcc, danielcdh, jmolloy, sanjoy, dberlin, ruiu

Reviewed By: ruiu

Subscribers: ruiu, llvm-commits

Differential Revision: https://reviews.llvm.org/D45142

llvm-svn: 330059
2018-04-13 19:47:57 +00:00
Mandeep Singh Grang db456efc8e [MC] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: grosbach, void, ruiu

Reviewed By: ruiu

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45138

llvm-svn: 330058
2018-04-13 19:47:01 +00:00
Mandeep Singh Grang 8547f913fc [ProfileData] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: bogner, vsk, eraman, ruiu

Reviewed By: ruiu

Subscribers: ruiu, llvm-commits

Differential Revision: https://reviews.llvm.org/D45139

llvm-svn: 330057
2018-04-13 19:46:36 +00:00
Simon Pilgrim 34b397a318 [CostModel][X86] Add some specific cpu targets to the cost models
We're mostly testing with generic isa attributes, but PR36550 will require testing of specific target's scheduler models as well.

llvm-svn: 330056
2018-04-13 19:30:15 +00:00
Simon Pilgrim 3ede11b58c [CostModel][X86] Split fma arith costs tests from other fp tests
Was proving cumbersome to test with/without fma

llvm-svn: 330054
2018-04-13 19:12:32 +00:00
Mandeep Singh Grang 5416af7af6 [LTO] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer D44363 for a list of all the required patches.

Reviewers: pcc, mehdi_amini, ruiu

Reviewed By: ruiu

Subscribers: ruiu, inglorion, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D45137

llvm-svn: 330053
2018-04-13 19:12:20 +00:00
Simon Pilgrim 237730a196 [CostModel][X86] Regenerate latency/codesize cost tests
llvm-svn: 330052
2018-04-13 18:56:58 +00:00
Simon Pilgrim 0c07ccc4e3 [CostModel][X86] Regenerate cast conversion cost tests
llvm-svn: 330051
2018-04-13 18:56:05 +00:00
Simon Pilgrim e30db80d30 [CostModel][X86] Regenerate masked intrinsic cost tests
llvm-svn: 330050
2018-04-13 18:54:16 +00:00
Rui Ueyama 197194b6c9 Define InitLLVM to do common initialization all at once.
We have a few functions that virtually all command wants to run on
process startup/shutdown. This patch adds InitLLVM class to do that
all at once, so that we don't need to copy-n-paste boilerplate code
to each llvm command's main() function.

Differential Revision: https://reviews.llvm.org/D45602

llvm-svn: 330046
2018-04-13 18:26:06 +00:00
Andrey Konovalov 1ba9d9c6ca hwasan: add -fsanitize=kernel-hwaddress flag
This patch adds -fsanitize=kernel-hwaddress flag, that essentially enables
-hwasan-kernel=1 -hwasan-recover=1 -hwasan-match-all-tag=0xff.

Differential Revision: https://reviews.llvm.org/D45046

llvm-svn: 330044
2018-04-13 18:05:21 +00:00
Roman Lebedev fe6a0b9a65 [InstCombine][NFC] masked-merge: commutativity tests: ensure the ordering.
This was intended since initially, but i did not really think
about it, and did not know how to force that. Now that the
xor->or fold is working (patch upcoming), this came up
to improve the test coverage.

A followup for rL330003, rL330007
https://bugs.llvm.org/show_bug.cgi?id=6773

llvm-svn: 330039
2018-04-13 17:15:55 +00:00
Sean Fertile eaa1607b48 Add PPC64_GLINK dynamic tag.
Add support for the PPC64_GLINK dynamic tag which is used in the ElfV2 abi.

Differential Revision: https://reviews.llvm.org/D45574

llvm-svn: 330038
2018-04-13 16:42:48 +00:00
Simon Dardis 9ec9f444cc [mips] Materialize constants for multiplication
Previously, the MIPS backend would alwyas break down constant multiplications
into a series of shifts, adds, and subs. This patch changes that so the cost of
doing so is estimated.

The cost is estimated against worst case constant materialization and retrieving
the results from the HI/LO registers.

For cases where the value type of the multiplication is not legal, the cost of
legalization is estimated and is accounted for before performing the
optimization of breaking down the constant

This resolves PR36884.

Thanks to npl for reporting the issue!

Reviewers: abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D45316

llvm-svn: 330037
2018-04-13 16:09:07 +00:00
Simon Pilgrim 0e74e50401 [X86] Remove remaining itinerary support from instructions and target (PR37093)
llvm-svn: 330035
2018-04-13 15:37:56 +00:00
Sjoerd Meijer 834f7dc7ab [ARM] FP16 vmaxnm/vminnm scalar instructions
This adds code generation support for the FP16 vmaxnm/vminnm scalar
instructions.

Differential Revision: https://reviews.llvm.org/D44675

llvm-svn: 330034
2018-04-13 15:34:26 +00:00
Clement Courbet 8ec0477136 Revert r330027: "[llvm-exegesis] re-enable failing tests after r330026."
The tests are still failing on some bots.

llvm-svn: 330033
2018-04-13 15:19:16 +00:00
Andrea Di Biagio c752616f30 [llvm-mca] Ensure that instructions with a schedule read-advance are always issued in the right order.
Normally, the Scheduler prioritizes older instructions over younger instructions
during the instruction issue stage. In one particular case where a dependent
instruction had a schedule read-advance associated to one of the input operands,
this rule was not correctly applied.

This patch fixes the issue and adds a test to verify that we don't regress that
particular case.

llvm-svn: 330032
2018-04-13 15:19:07 +00:00
Yan Luo 545a0c2fb0 [ARC] Add LImm support for J/JL
llvm-svn: 330031
2018-04-13 15:10:34 +00:00
Simon Pilgrim a3a9d81231 [X86] Generalize X86FixupLEAs to work with TargetSchedModel
Similar to rL329834, don't rely on itinerary scheduler model to determine latencies for LEA thresholds, use the generic TargetSchedModel::computeInstrLatency call.

llvm-svn: 330030
2018-04-13 15:09:39 +00:00
Mircea Trofin 5b63803d1f [profile] Fix binary format reader error propagation.
Summary:
This was originally part of rL328132, and led to the discovery
of the issues addressed in rL328987. Re-landing.

Reviewers: xur, davidxl, bkramer

Reviewed By: bkramer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45545

llvm-svn: 330029
2018-04-13 15:04:36 +00:00