Commit Graph

96490 Commits

Author SHA1 Message Date
Robert Lytton 9715375c25 XCore target: fix bug in XCoreLowerThreadLocal.cpp
When a ConstantExpr which uses a thread local is part of a PHI node
instruction, the insruction that replaces the ConstantExpr must
be inserted in the predecessor block, in front of the terminator instruction.
If the predecessor block has multiple successors, the edge is first split.

llvm-svn: 192432
2013-10-11 10:26:48 +00:00
Robert Lytton 3139db02c8 XCore target: add XCoreTargetLowering::isZExtFree()
llvm-svn: 192431
2013-10-11 10:26:29 +00:00
Daniel Sanders d7103f3187 [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics)
llvm-svn: 192430
2013-10-11 10:14:25 +00:00
Daniel Sanders 015972bd95 [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics)
llvm-svn: 192429
2013-10-11 10:00:06 +00:00
Craig Topper 81034928c6 Remove another unnecessary filter from the disassembler.
llvm-svn: 192425
2013-10-11 06:59:57 +00:00
NAKAMURA Takumi d5d16d57eb LiveRangeCalc.h: Update a description corresponding to r192396. [-Wdocumentation]
llvm-svn: 192421
2013-10-11 04:52:03 +00:00
Kevin Qin a89e7a0e1c Implement aarch64 neon instruction set AdvSIMD (copy).
llvm-svn: 192410
2013-10-11 02:33:55 +00:00
Matt Arsenault 1408b60291 Fix typo
llvm-svn: 192406
2013-10-10 23:05:37 +00:00
Matthias Braun b98a950cc6 Tests: Do not unnecessarily depend on kill comments
llvm-svn: 192404
2013-10-10 22:37:49 +00:00
Matthias Braun 72d3607d3c Tests: Use CHECK-LABEL where possible
llvm-svn: 192403
2013-10-10 22:37:47 +00:00
Matthias Braun f6fe6bfffe Print register in LiveInterval::print()
llvm-svn: 192398
2013-10-10 21:29:05 +00:00
Matthias Braun 34e1be9451 Represent RegUnit liveness with LiveRange instance
Previously LiveInterval has been used, but having a spill weight and
register number is unnecessary for a register unit.

llvm-svn: 192397
2013-10-10 21:29:02 +00:00
Matthias Braun 2d5c32b3b5 Work on LiveRange instead of LiveInterval where possible
Also change some pointer arguments to references at some places where
0-pointers are not allowed.

llvm-svn: 192396
2013-10-10 21:28:57 +00:00
Matthias Braun 364e6e9072 Change MachineVerifier to work on LiveRange + LiveInterval
llvm-svn: 192395
2013-10-10 21:28:54 +00:00
Matthias Braun 88dd0abd2d Pass LiveQueryResult by value
This makes the API a bit more natural to use and makes it easier to make
LiveRanges implementation details private.

llvm-svn: 192394
2013-10-10 21:28:52 +00:00
Matthias Braun d7df935bbc Refactor LiveInterval: introduce new LiveRange class
LiveRange just manages a list of segments and a list of value numbers
now as LiveInterval did previously, but without having details like spill
weight or a fixed register number.
LiveInterval is now a subclass of LiveRange and simply adds the spill weight
and the register number.

llvm-svn: 192393
2013-10-10 21:28:47 +00:00
Matthias Braun 13ddb7cd65 Rename LiveRange to LiveInterval::Segment
The Segment struct contains a single interval; multiple instances of this struct
are used to construct a live range, but the struct is not a live range by
itself.

llvm-svn: 192392
2013-10-10 21:28:43 +00:00
Matthias Braun 1965bfa4c7 Rename parameter: defined regs are not incoming.
llvm-svn: 192391
2013-10-10 21:28:38 +00:00
Sriram Murali 34e37f0cc7 test commit
- fix comments on vector type legalization

llvm-svn: 192389
2013-10-10 20:24:53 +00:00
Matt Arsenault a98c3b1816 Use getPointerSizeInBits() rather than 8 * getPointerSize()
llvm-svn: 192386
2013-10-10 19:09:05 +00:00
Matt Arsenault 668e38a40b Fix grammar / missing words
llvm-svn: 192380
2013-10-10 18:47:35 +00:00
Manman Ren c50fa1114b Debug Info: In DIBuilder, the context field of subprogram is updated to use
DIScopeRef.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 192378
2013-10-10 18:40:01 +00:00
Manman Ren 9b971f9590 Add comments to debug info testing case.
llvm-svn: 192376
2013-10-10 18:13:17 +00:00
Matt Arsenault 204cfa6e43 R600: Fix trunc i64 to i32 on SI
llvm-svn: 192375
2013-10-10 18:04:16 +00:00
Hans Wennborg 4fa1eb0d0d Provide msbuild integration for vs2013.
Patch by Josh Samuel!

llvm-svn: 192371
2013-10-10 17:32:01 +00:00
Hans Wennborg d2aa909462 Fix msbuild integration install script.
We previously failed to check whether the SUCCESS variable was set,
and would thus always exit with a failure if vs2012 didn't exist.

llvm-svn: 192370
2013-10-10 17:31:54 +00:00
Tom Stellard 93fabcebf1 R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP*
The function is used by the machine verifier and checks that VOP*
instructions have legal operands.

llvm-svn: 192367
2013-10-10 17:11:55 +00:00
Tom Stellard 70f13dba15 R600/SI: Use -verify-machineinstrs for most tests
We can't enable the verifier for tests with SI_IF and SI_ELSE, because
these instructions are always followed by a COPY which copies their
result to the next basic block.  This violates the machine verifier's
rule that non-terminators can not folow terminators.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 192366
2013-10-10 17:11:46 +00:00
Tom Stellard 682bfbc43d R600/SI: Define a separate MIMG instruction for each possible output value type
During instruction selection, we rewrite the destination register
class for MIMG instructions based on their writemasks.  This creates
machine verifier errors since the new register class does not match
the register class in the MIMG instruction definition.

We can avoid this by defining different MIMG instructions for each
possible destination type and then switching to the correct instruction
when we change the register class.

llvm-svn: 192365
2013-10-10 17:11:24 +00:00
Tom Stellard 1b99ed8290 R600/SI: Mark the EXEC register as reserved
This prevents the machine verifier from complaining about uses of
an undefined physical register.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 192364
2013-10-10 17:11:19 +00:00
Tom Stellard ed0ceec1c1 R600: Use StructurizeCFGPass for non SI targets
StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of
shader from shadertoy (which exhibits complex control flow constructs) to works
correctly with respect to CFG handling (and allow us to detect potential bug in
other part of the backend).

We provide a cmd line argument to disable the pass for debug purpose.

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 192363
2013-10-10 17:11:12 +00:00
Hao Liu 99eac7ee44 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192361
2013-10-10 17:00:52 +00:00
Rafael Espindola 9558af461d Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)."
This reverts commit r192352. It broke the build.

llvm-svn: 192354
2013-10-10 15:15:17 +00:00
Hao Liu 9123ad8ab9 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192352
2013-10-10 15:01:24 +00:00
Benjamin Kramer b3b79a4345 ARM: Put isV8EligibleForIT into the llvm namespace. While there make it inline.
llvm-svn: 192350
2013-10-10 14:35:45 +00:00
Benjamin Kramer 20a6a436ae Disable function padding to get this test to pass on atom.
llvm-svn: 192348
2013-10-10 12:46:23 +00:00
Tim Northover 569f69dace ARM: correct liveness flags during ARMLoadStoreOpt
When we had a sequence like:

    s1 = VLDRS [r0, 1], Q0<imp-def>
    s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
    s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
    s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>

we were gathering the {s0, s1} loads below the s3 load. This is fine,
but confused the verifier since now the s3 load had Q0<imp-use> with
no definition above it.

This should mark such uses <undef> as well. The liveness structure at
the beginning and end of the block is unaffected, and the true sN
definitions should prevent any dodgy reorderings being introduced
elsewhere.

rdar://problem/15124449

llvm-svn: 192344
2013-10-10 09:28:20 +00:00
Craig Topper 5fb5bd3373 Allow non-AVX form of pmovmskb to take a GR64 operand.
llvm-svn: 192341
2013-10-10 05:33:31 +00:00
Craig Topper 3ada6deaac Remove duplicate instructions.
llvm-svn: 192340
2013-10-10 05:01:22 +00:00
Craig Topper e1ceeb40c1 Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.
llvm-svn: 192339
2013-10-10 04:26:52 +00:00
Akira Hatanaka 4a3836bed4 [mips] Do not generate INS/EXT nodes if target does not have support for
ins/ext.

llvm-svn: 192330
2013-10-09 23:36:17 +00:00
Rui Ueyama 82166eef16 Revert "llvm-c: Make target initializer functions external functions in lib."
This reverts commit r192316. The original change introduced circular
dependencies between libTarget and backends. That would broke a build unless
link everything into one big binary.

llvm-svn: 192329
2013-10-09 23:15:49 +00:00
Manman Ren 88b0f948f5 Debug Info: In DIBuilder, the context and type fields of template_type and
template_value are updated to use DIRef.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 192320
2013-10-09 19:46:28 +00:00
Anders Waldenborg d39827d4a4 llvm-c: Make target initializer functions external functions in lib.
Making them proper functions defined in the (shared)lib instead of
static inlines defined in the header files makes it possible to
actually distribute a binary compiled against the shared library
without having to worry about getting undefined symbol errors when
calling e.g LLVMInitializeAllTargetInfos because the shared library on
the other system was compiled with different targets.

Differential Revision: http://llvm-reviews.chandlerc.com/D1714

llvm-svn: 192316
2013-10-09 19:02:09 +00:00
Manman Ren b3dc3afd22 Debug Info: In DIBuilder, the context field of a forward decl is updated
to use DIScopeRef.

llvm-svn: 192309
2013-10-09 18:10:55 +00:00
Bill Wendling a40c5263ed Add missing releases.
llvm-svn: 192304
2013-10-09 17:37:04 +00:00
Benjamin Kramer 4188293c72 Flip the ownership of MCStreamer and MCTargetStreamer.
MCStreamer now owns the target streamer. This prevents leaking the target
streamer.

llvm-svn: 192303
2013-10-09 17:23:41 +00:00
Shuxin Yang 1cab418ce2 Fix a bug in Dead Argument Elimination.
If a function seen at compile time is not necessarily the one linked to
the binary being built, it is illegal to change the actual arguments
passing to it. 

  e.g. 
   --------------------------
   void foo(int lol) {
     // foo() has linkage satisifying isWeakForLinker()
     // "lol" is not used at all.
   }

   void bar(int lo2) {
      // xform to foo(undef) is illegal, as compiler dose not know which
      // instance of foo() will be linked to the the binary being built.
      foo(lol2); 
   }
  -----------------------------

  Such functions can be captured by isWeakForLinker(). NOTE that
mayBeOverridden() is insufficient for this purpose as it dosen't include
linkage types like AvailableExternallyLinkage and LinkOnceODRLinkage.
Take link_odr* as an example, it indicates a set of *EQUIVALENT* globals
that can be merged at link-time. However, the semantic of 
*EQUIVALENT*-functions includes parameters. Changing parameters breaks
the assumption.

  Thank John McCall for help, especially for the explanation of subtle
difference between linkage types.

  rdar://11546243

llvm-svn: 192302
2013-10-09 17:21:44 +00:00
Rafael Espindola caa435664a Add a GlobalAlias::isValidLinkage to reduce code duplication.
Thanks to Reid Kleckner for the suggestion.

llvm-svn: 192298
2013-10-09 16:07:32 +00:00
Venkatraman Govindaraju 8812485d41 [Sparc] Disable tail call optimization for sparc64.
This patch fixes PR17506.

llvm-svn: 192294
2013-10-09 12:50:39 +00:00