6238c1d102
Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it
...
llvm-svn: 109039
2010-07-21 21:37:59 +00:00
784e062b2a
Fix a couple issues with Win64 ABI
...
1) all registers were spilled as xmm, regardless of actual size
2) win64 abi doesn't do the varargs-size-in-%al thing
Still to look into:
xmm6-15 are marked as clobbered by call instructions on win64 even though they aren't.
llvm-svn: 109035
2010-07-21 20:49:52 +00:00
19b3830142
Avoid AVX instructions to be selected instead of its SSE form
...
llvm-svn: 109032
2010-07-21 20:38:42 +00:00
4277e14dc4
Fix calling convention on ARM if vfp2+ is enabled.
...
llvm-svn: 109009
2010-07-21 11:38:30 +00:00
d27913e516
Pulling out previous patch, must've run the tests in
...
the wrong directory.
llvm-svn: 109005
2010-07-21 09:23:56 +00:00
b2d1067024
Lower MEMBARRIER on x86 and support processors without SSE2.
...
Fixes a pile of libgomp failures in the llvm-gcc testsuite due
to the libcall not existing.
llvm-svn: 109004
2010-07-21 09:05:23 +00:00
cdbec62510
Add AVX only vzeroall and vzeroupper instructions
...
llvm-svn: 109002
2010-07-21 08:56:24 +00:00
a77f3d3b37
Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
...
llvm-svn: 108991
2010-07-21 06:09:07 +00:00
3499934da6
Add new AVX vpermilps, vpermilpd and vperm2f128 instructions
...
llvm-svn: 108984
2010-07-21 03:07:42 +00:00
3ceaf7a0a2
Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it
...
llvm-svn: 108983
2010-07-21 02:46:58 +00:00
e706501975
Add new AVX vextractf128 instructions
...
llvm-svn: 108964
2010-07-20 23:19:02 +00:00
41ff5d4d91
make asmprinter optional, even though passing in null will cause things to explode right now.
...
llvm-svn: 108955
2010-07-20 22:45:33 +00:00
b4dc58975b
continue pushing dependencies around.
...
llvm-svn: 108952
2010-07-20 22:35:40 +00:00
2366d95af9
reduce X86MCInstLower dependencies on asmprinter.
...
llvm-svn: 108950
2010-07-20 22:30:53 +00:00
7fbdd7c852
pass around MF, not MMI.
...
llvm-svn: 108949
2010-07-20 22:26:07 +00:00
d3f3a89425
cleanups.
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llvm-svn: 108947
2010-07-20 22:23:57 +00:00
5ca516b87c
move two asmprinter methods into the asmprinter .cpp file.
...
llvm-svn: 108945
2010-07-20 22:18:19 +00:00
cbe9856fce
prune #includes a little.
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llvm-svn: 108929
2010-07-20 21:17:29 +00:00
3b505848fd
Add new AVX instruction vinsertf128
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llvm-svn: 108892
2010-07-20 19:44:51 +00:00
3680f70c9d
Using BIC for immediates needs an extra bump for its complexity to get
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instruction selection to prefer it when possible. rdar://7903972
llvm-svn: 108844
2010-07-20 16:07:04 +00:00
9c7708cc1b
Removed un-used code.
...
llvm-svn: 108841
2010-07-20 14:51:32 +00:00
160695fecb
Fix PR7174, a couple o Mips fixes:
...
- Fix a typo for PIC check during jmp table lowering
- Also fix the "first jump table basic block is not
considered only reachable by fall through" problem, use this
ad-hoc solution until I come up with something better.
Patch by stetorvs@gmail.com
llvm-svn: 108820
2010-07-20 08:37:04 +00:00
ea7863647b
Fix Mips PR7473. Patch by stetorvs@gmail.com
...
llvm-svn: 108816
2010-07-20 07:58:51 +00:00
4adaccf0bf
Constify some arguments.
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llvm-svn: 108812
2010-07-20 06:52:21 +00:00
14c5fd437c
Add AVX vbroadcast new instruction
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llvm-svn: 108788
2010-07-20 00:11:13 +00:00
0aff8033c6
Update CMake files.
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llvm-svn: 108787
2010-07-20 00:08:13 +00:00
b792b463af
sink the arm implementations of ASmPrinter and MCInstLower
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out of the AsmPrinter directory into libarm. Now the
ARM InstPrinters depend jsut on the MC stuff, not on vmcore
or codegen.
llvm-svn: 108783
2010-07-19 23:44:46 +00:00
64fffadad3
fix a layering problem by moving the x86 implementation
...
of AsmPrinter and InstLowering into libx86 and out of the
asmprinter subdirectory. Now X86/AsmPrinter just depends on
MC stuff, not all of codegen and LLVM IR.
llvm-svn: 108782
2010-07-19 23:41:57 +00:00
9de0ca73d4
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
...
llvm-svn: 108769
2010-07-19 23:32:44 +00:00
10f99a3490
ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
...
llvm-svn: 108761
2010-07-19 22:15:08 +00:00
9db7d0addd
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same
...
instruction, we only want to allow the one for the current subtarget.
- This also fixes suffix matching for jmp instructions, because it eliminates
the ambiguity between 'jmpl' and 'jmpq'.
llvm-svn: 108746
2010-07-19 20:44:16 +00:00
8d3ba7349c
Since ARM emits inline jump tables as part of the ConstantIsland pass,
...
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR6581.
llvm-svn: 108730
2010-07-19 17:20:38 +00:00
d9ad52adff
revert so I can get the right PR# in the log message.
...
llvm-svn: 108727
2010-07-19 17:19:40 +00:00
c685756cfb
Since ARM emits inline jump tables as part of the ConstantIsland pass,
...
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR7499.
llvm-svn: 108722
2010-07-19 17:18:28 +00:00
9aefb8ee4c
X86-64: Mark WINCALL and more tail call instructions as code gen only.
...
llvm-svn: 108685
2010-07-19 07:21:07 +00:00
2e9f58517d
X86: Mark some tail call pseduo instruction as code gen only.
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llvm-svn: 108684
2010-07-19 07:21:04 +00:00
1cd02510d3
X86: Mark In32/64BitMode on LEAVE[64] and SYSEXIT[64].
...
llvm-svn: 108683
2010-07-19 07:21:01 +00:00
b82cd9319b
MC/X86: We now match instructions like "incl %eax" correctly for the arch we are
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assembling; remove crufty custom cleanup code.
llvm-svn: 108681
2010-07-19 06:14:54 +00:00
150d948d3a
X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real.
...
llvm-svn: 108680
2010-07-19 06:14:49 +00:00
961543377d
X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode.
...
llvm-svn: 108679
2010-07-19 06:14:44 +00:00
eefe8616be
TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> attributes as part of the matcher.
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- Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.
llvm-svn: 108677
2010-07-19 05:44:09 +00:00
419197cc4d
Target: Give the TargetAsmParser access to the TargetMachine.
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- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.
llvm-svn: 108664
2010-07-19 00:33:49 +00:00
5218343970
the stackifier is global!
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llvm-svn: 108626
2010-07-17 17:42:04 +00:00
8f440bb9b0
doxygenify some comments.
...
llvm-svn: 108625
2010-07-17 17:40:51 +00:00
b97e2bbe32
Add combiner patterns to more effectively utilize the BFI (bitfield insert)
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instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.
llvm-svn: 108608
2010-07-17 03:30:54 +00:00
6e3b5fa91c
add BFI to getTargetNodeName()
...
llvm-svn: 108603
2010-07-17 01:50:57 +00:00
adc81f8ee8
Fix logic think-o
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llvm-svn: 108601
2010-07-17 01:22:19 +00:00
83f250f005
Remove unnecessary check that was subsumed into canRealignStack.
...
llvm-svn: 108588
2010-07-17 00:33:04 +00:00
24e3aa011a
Make more explicit and add some currently disabled error messages for
...
stack realignment on ARM.
Also check for function attributes as we do on X86 as well as
make explicit that we're checking can as well as needs in this function.
llvm-svn: 108582
2010-07-17 00:27:24 +00:00
c0be37287c
Make comment a bit more clear as well as return statement since
...
needsStackRealignment is currently checking the can conditions as well.
llvm-svn: 108581
2010-07-17 00:25:41 +00:00
11013eda5a
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
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and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.
llvm-svn: 108570
2010-07-16 23:05:05 +00:00
8289f78569
Remove the isMoveInstr() hook.
...
llvm-svn: 108567
2010-07-16 22:35:46 +00:00
8e767bde16
Avoid isMoveInstr when printing XCore pseudo-moves.
...
llvm-svn: 108566
2010-07-16 22:35:37 +00:00
2c130b8ead
Use MI.isCopy.
...
llvm-svn: 108565
2010-07-16 22:35:34 +00:00
54bcf5049e
Use a small local function for a single remaining late isMoveInstr call in
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Thumb2ITBlockPass.
llvm-svn: 108564
2010-07-16 22:35:32 +00:00
499f797cdd
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
...
thus is a much more meaningful name.
llvm-svn: 108563
2010-07-16 22:20:36 +00:00
8d51149102
Keep valgrind quiet.
...
The isLive() method can read uninitialized memory, but it still gives correct
results.
llvm-svn: 108561
2010-07-16 22:00:33 +00:00
44629eb81b
Emit COPY instead of FMR/FMSD instructions for floating point conversion on
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PowerPC.
llvm-svn: 108555
2010-07-16 21:03:52 +00:00
ba9b25a6ba
Add missing attributes to cpp backend.
...
llvm-svn: 108547
2010-07-16 18:47:20 +00:00
da3e05db70
Accept registers with P modifier. PR 5314.
...
llvm-svn: 108545
2010-07-16 18:35:46 +00:00
6353e534ec
Teach PPCInstrInfo::storeRegToStackSlot and loadRegFromStackSlot to add memory
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operands.
Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't
since missing memoperands should not affect correctness.
llvm-svn: 108540
2010-07-16 18:22:00 +00:00
c30b4ddc58
Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill
...
pass that inserted it.
It is no longer necessary to limit the live ranges of FP registers to a single
basic block.
llvm-svn: 108536
2010-07-16 17:41:44 +00:00
f0af236874
Search for a free FP register instead of just assuming FP7 is not in use.
...
llvm-svn: 108535
2010-07-16 17:41:40 +00:00
0e5fb020a0
Allow x87 FP registers to be alive globally in a function.
...
FP_REG_KILL instructions are still inserted, but can be disabled by passing
-live-x87 to llc. The X87FPRegKillInserterPass is going to be removed shortly.
CFG edges are partioned into bundles where the x87 stack must be allocated
identically. Code is insertad at the end of each basic block that shuffles the
live FP registers to match the outgoing bundles expectations.
This fix is in preparation for some upcoming register allocator improvements
that may extend the live range of registers beyond a basic block, similar to
LICM. It also provides a nice runtime speedup if you are building with
-mfpmath=387.
llvm-svn: 108529
2010-07-16 16:38:12 +00:00
55f0c6b9fc
Split -enable-finite-only-fp-math to two options:
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-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.
llvm-svn: 108465
2010-07-15 22:07:12 +00:00
620693806a
fix the encoding of MMX_MOVFR642Qrr, it starts with 0xF2 not 0xF3,
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this fixes rdar://8192860. Unfortunately it can only be triggered
with llc because llvm-mc matches another (correctly encoded) version
of this, so no testcase.
llvm-svn: 108454
2010-07-15 20:13:34 +00:00
e4be4308a9
Random note about bswap.
...
llvm-svn: 108396
2010-07-15 02:20:38 +00:00
8b1bb8cfbd
Last COPY conversion.
...
llvm-svn: 108387
2010-07-14 23:58:21 +00:00
0b9aafddc5
Remove restriction on NEON alignment values. Some of the NEON ld/st
...
instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.
llvm-svn: 108386
2010-07-14 23:54:43 +00:00
9b449d5a92
Use TargetOpcode::COPY instead of X86-native register copy instructions when
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lowering atomics. This will allow those copies to still be coalesced after
TII::isMoveInstr is removed.
llvm-svn: 108385
2010-07-14 23:50:27 +00:00
769aedd523
fix indentation
...
llvm-svn: 108368
2010-07-14 23:04:59 +00:00
92d8998348
Don't pass StringRef by reference.
...
llvm-svn: 108366
2010-07-14 22:38:02 +00:00
254858031a
Merge lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h,
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patch by Michael Spencer!
llvm-svn: 108342
2010-07-14 18:14:33 +00:00
a90af1ba38
Improve 64-subtraction of immediates when parts of the immediate can fit
...
in the literal field of an instruction. E.g.,
long long foo(long long a) {
return a - 734439407618LL;
}
rdar://7038284
llvm-svn: 108339
2010-07-14 17:45:16 +00:00
1aef53403f
Add missing address register update to t2LDM_RET instruction.
...
Patch by Brian Lucas. PR7636.
llvm-svn: 108332
2010-07-14 16:02:13 +00:00
c4d70125ee
A couple potential optimizations inspired by comment 4 in PR6773.
...
llvm-svn: 108328
2010-07-14 06:58:26 +00:00
a8e8874552
Fix for PR7193 was overly conservative. The only case where sibcall callee
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address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.
This fixes PR7610.
llvm-svn: 108327
2010-07-14 06:44:01 +00:00
bad47f62f6
Add support for NEON VMVN immediate instructions.
...
llvm-svn: 108324
2010-07-14 06:31:50 +00:00
bd54a53628
The bits in the cmode field of 32-bit VMOV immediate instructions all depend
...
of the value of the immediate.
llvm-svn: 108323
2010-07-14 06:30:44 +00:00
164a0775bb
fix a bug found by a warning I added to clang this morning.
...
llvm-svn: 108309
2010-07-14 01:57:17 +00:00
103a0dcfe1
Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
...
Radar 7373643.
llvm-svn: 108303
2010-07-14 01:22:12 +00:00
1f471435f8
Don't propagate debug locations to instructions for materializing
...
constants, since they may not be emited near the other instructions
which get the same line, and this confuses debug info.
llvm-svn: 108302
2010-07-14 01:07:44 +00:00
6c6c14a55c
Add AVX 256-bit compare instructions and a bunch of testcases
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llvm-svn: 108286
2010-07-13 22:06:38 +00:00
a3f1901531
Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
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NEON VMOV-immediate instructions. This simplifies some things.
llvm-svn: 108275
2010-07-13 21:16:48 +00:00
fd8bfcd6e1
AVX 256-bit conversion instructions
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Add the x86 VEX_L form to handle special cases where VEX_L must be set.
llvm-svn: 108274
2010-07-13 21:07:28 +00:00
76a6b663a3
Added a check that pusha cannot be encoded in 64-bit mode.
...
llvm-svn: 108265
2010-07-13 20:05:41 +00:00
0cc4ad983d
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
...
llvm-svn: 108258
2010-07-13 19:27:42 +00:00
58066e337d
Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).
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llvm-svn: 108256
2010-07-13 19:21:50 +00:00
f43961007c
-enable-unsafe-fp-math should not imply -enable-finite-only-fp-math.
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llvm-svn: 108254
2010-07-13 18:46:14 +00:00
03e7e68caa
rotate CallInst operands
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with this commit the callee moves to the end of
the operand array (from the start) and the call
arguments now start at index 0 (formerly 1)
this ordering is now consistent with InvokeInst
this commit only flips the switch,
functionally it is equivalent to
r101465
I intend to commit several cleanups after a few
days of soak period
llvm-svn: 108240
2010-07-13 15:31:36 +00:00
c1c6f4796e
Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to
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avoid replicated code.
llvm-svn: 108227
2010-07-13 04:44:34 +00:00
55595fb291
my work on adding segment registers to LEA missed the
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disassembler. Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.
llvm-svn: 108226
2010-07-13 04:23:55 +00:00
dff283e146
Add AVX 256-bit packed logical forms
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llvm-svn: 108224
2010-07-13 02:38:35 +00:00
36b32aeaa5
Add AVX 256-bit unop arithmetic instructions
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llvm-svn: 108223
2010-07-13 01:53:31 +00:00
77a3c4462f
Since AVX is a superset of all SSE versions, only use HasAVX for AVX instructions
...
llvm-svn: 108222
2010-07-13 00:38:47 +00:00
03264efe30
Move some SIMD fragment code into X86InstrFragmentsSIMD so that the
...
utility classes can be used from multiple files. This will aid
transitioning to a new refactored x86 SIMD specification.
llvm-svn: 108213
2010-07-12 23:41:28 +00:00
8e67a0482e
Add AVX 256 binary arithmetic instructions
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llvm-svn: 108207
2010-07-12 23:04:15 +00:00
91806311c9
More refactoring of basic SSE arith instructions. Open room for 256-bit instructions
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llvm-svn: 108204
2010-07-12 22:41:32 +00:00
51e6d9bbf6
Apply the SSE dependence idiom for SSE unary operations to
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SD instructions too, in addition to SS instructions. And
add a comment about it.
llvm-svn: 108191
2010-07-12 20:46:04 +00:00
8a2bdc8231
Remove some code that doesn't appear to do anything. All the ARM call
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instructions already have implicit defs of LR. The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.
llvm-svn: 108186
2010-07-12 20:22:45 +00:00
Bruno Cardoso Lopes