Commit Graph

382477 Commits

Author SHA1 Message Date
Fangrui Song 5af991d464 [tsan] Fix aarch64-*-linux after D86377
All check-tsan tests fail on aarch64-*-linux because HeapMemEnd() > ShadowBeg()
for the following code path:
```
 #if defined(__aarch64__) && !HAS_48_BIT_ADDRESS_SPACE
   ProtectRange(HeapMemEnd(), ShadowBeg());
```

Restore the behavior before D86377 for aarch64-*-linux.
2021-03-10 22:16:04 -08:00
Leonard Chan baf637dcde Rename top-level LICENSE.txt files to LICENSE.TXT
This makes all the license filenames uniform across subprojects.

Differential Revision: https://reviews.llvm.org/D98380
2021-03-10 21:26:24 -08:00
Craig Topper 47c7a6cfed [RISCV] Merge fixed-vectors-int-splat-rv32.ll and fixed-vectors-int-splat-rv64.ll.
The vXi64 test cases no longer crash on rv32.
2021-03-10 20:15:26 -08:00
Matthias Springer c40e0d7609 [mlir][AVX512] Implement sparse vector dot product integration test.
This test operates on two hardware-vector-sized vectors and utilizes vp2intersect and mask.compress.

PHAB_REVIEW=D98099
2021-03-11 13:00:17 +09:00
Craig Topper 9773cad519 [RISCV] Add additional checking to tablgen RISCVVEmitter requested in D95016.
This errors, but doesn't give source location. We'd need to pass
the Record through several layers to get to the location.

Reviewed By: jrtc27

Differential Revision: https://reviews.llvm.org/D98379
2021-03-10 19:46:25 -08:00
Craig Topper 85ae96d8b2 [RISCV] Add v2i64 _vi_ and _iv_ test cases to fixed-vectors-int.ll since we no longer crash.
I think we were missing some build_vector or other support and
skipped these test cases. They work now but don't generate
optimal code.
2021-03-10 19:19:47 -08:00
David Blaikie 9c3eb45713 Revert "WIP"
Accidental commit.

This reverts commit 60238f29bf.
2021-03-10 19:17:14 -08:00
David Blaikie 60238f29bf WIP 2021-03-10 19:13:22 -08:00
Juneyoung Lee 720a828045 Resolve unused variable warning (NFC) 2021-03-11 12:03:03 +09:00
Nico Weber cb17f060e2 [gn build] (manually) Port d6a0560bf2 2021-03-10 21:56:59 -05:00
Zakk Chen d6a0560bf2 [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.
Demonstrate how to generate vadd/vfadd intrinsic functions

1. add -gen-riscv-vector-builtins for clang builtins.
2. add -gen-riscv-vector-builtin-codegen for clang codegen.
3. add -gen-riscv-vector-header for riscv_vector.h. It also generates
ifdef directives with extension checking, base on D94403.
4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h.
Generate overloading version Header for generic api.
https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface
5. update tblgen doc for riscv related options.

riscv_vector.td also defines some unused type transformers for vadd,
because I think it could demonstrate how tranfer type work and we need
them for the whole intrinsic functions implementation in the future.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos

Differential Revision: https://reviews.llvm.org/D95016
2021-03-10 18:43:43 -08:00
Vy Nguyen 64d2c326b7 [llvm] Fix thinko in getVendorSignature(), where expected values of ECX and EDX were flipped for the AMD case.
Follow up to D97504

Differential Revision: https://reviews.llvm.org/D98322
2021-03-10 21:39:19 -05:00
Juneyoung Lee 8652c3e1a3 [InstSimplify] Pass SimplifyQuery to computePointerICmp (NFC) 2021-03-11 11:13:46 +09:00
Ruiling Song 66340846b3 [AMDGPU] Always create Stack Object for reserved VGPR
As we may overwrite inactive lanes of a caller-save-vgpr, we should
always save/restore the reserved vgpr for sgpr spill.

Reviewed by: arsenm

Differential Revision: https://reviews.llvm.org/D98319
2021-03-11 10:06:07 +08:00
George Balatsouras 9e82027db8 [dfsan] Update atomics.ll test
Remove hard-coded shadow width references and remove irrelevant instructions.

Reviewed By: stephan.yichao.zhao

Differential Revision: https://reviews.llvm.org/D98376
2021-03-10 17:55:50 -08:00
Ruiling Song 8b7d3bed0f [ValueMapper] Add debug output for metadata remapping
This is useful for debugging which pointers are updated during remapping
process.

Differential Revision: https://reviews.llvm.org/D95775
2021-03-11 09:54:55 +08:00
Daniel Sanders 134a179dee [mir] Change 'undef' for MMO base addresses to 'unknown-address'
Differential Revision: https://reviews.llvm.org/D98100
2021-03-10 16:46:44 -08:00
River Riddle 4e02eb8014 [mlir] Optimize the implementation of RegionDCE
The current implementation has some inefficiencies that become noticeable when running on large modules. This revision optimizes the code, and updates some out-dated idioms with newer utilities. The main components of this optimization include:

* Add an overload of Block::eraseArguments that allows for O(N) erasure of disjoint arguments.
* Don't process entry block arguments given that we don't erase them at this point.
* Don't track individual operation results, given that we don't erase them. We can just track the parent operation.

Differential Revision: https://reviews.llvm.org/D98309
2021-03-10 16:39:50 -08:00
Leonard Chan 70af0bf6fe [clang][Driver] Expose -fexperimental-relative-c++-abi-vtables flag
Initially, this flag was meant to only be used through cc1 and not directly
through the clang driver. However, we accidentally ended up using this flag
as a driver flag already for selecting multilibs within the fuchsia toolchain.
We're currently in an awkward state where it's only accepted as a driver flag
when targeting Fuchsia, and all other instances it can only be added via
-Xclang. Since we're ready to use this in Fuchsia, we can just expose this to
the driver for simplicity.

Differential Revision: https://reviews.llvm.org/D98375
2021-03-10 16:28:40 -08:00
LLVM GN Syncbot af4ae18319 [gn build] Port 4f16e177e1 2021-03-10 23:36:48 +00:00
Stephen Kelly 14050ddc40 Revert "[AST] Add generator for source location introspection"
This reverts commit d627a27d26.

This fails to link on Windows somehow.
2021-03-10 23:36:06 +00:00
Stephen Kelly 774b707564 Revert "Workaround a -Wmisleading-indentation warning"
This reverts commit 5c22e2bec0.
2021-03-10 23:35:41 +00:00
Reid Kleckner b69db4a7ab Re-land "[PDB] Defer relocating .debug$S until commit time and parallelize it"
This reverts commit bacf9cf2c5 and
reinstates commit 1a9bd5b813.

Reverting this commit did not appear to make the problem go away, so we
can go ahead and reland it.
2021-03-10 15:14:09 -08:00
Stephen Kelly 5c22e2bec0 Workaround a -Wmisleading-indentation warning
Because the generated code is not formatted, it can cause warnings.
2021-03-10 23:12:31 +00:00
Giorgis Georgakoudis ecf68972fd Revert "Replace func name with regex in update_cc_test_checks"
This reverts commit bf58d6a1f9.

Breaks tests, fix
2021-03-10 15:05:35 -08:00
zoecarver a89ac0dd18 Update __is_unsigned builtin to match the Standard.
Updates __is_unsigned to have the same behavior as the standard
specifies. This is in line with 511dbd8, which applied the same change
to __is_signed.

Refs D67897.

Differential Revision: https://reviews.llvm.org/D98104
2021-03-10 15:00:26 -08:00
Emilio Cota c0891706bc [mlir] Add polynomial approximation for math::Log2
```
name                     old cpu/op  new cpu/op  delta
BM_mlir_Log2_f32/10       134ns ±15%    45ns ± 4%  -66.39%  (p=0.000 n=20+17)
BM_mlir_Log2_f32/100     1.03µs ±16%  0.12µs ±10%  -88.78%  (p=0.000 n=20+18)
BM_mlir_Log2_f32/1k      10.3µs ±16%   0.7µs ± 5%  -93.24%  (p=0.000 n=20+17)
BM_mlir_Log2_f32/10k      104µs ±15%     7µs ±14%  -93.25%  (p=0.000 n=20+20)
BM_eigen_s_Log2_f32/10   95.3ns ±17%  90.9ns ± 6%     ~     (p=0.228 n=20+18)
BM_eigen_s_Log2_f32/100   907ns ± 3%   911ns ± 6%     ~     (p=0.539 n=16+20)
BM_eigen_s_Log2_f32/1k   9.88µs ± 4%  9.85µs ± 3%     ~     (p=0.790 n=16+17)
BM_eigen_s_Log2_f32/10k   105µs ±10%   110µs ±16%     ~     (p=0.459 n=16+20)
BM_eigen_v_Log2_f32/10   32.5ns ±31%  33.9ns ±14%   +4.31%  (p=0.028 n=17+20)
BM_eigen_v_Log2_f32/100   176ns ± 8%   180ns ± 7%   +2.19%  (p=0.045 n=16+17)
BM_eigen_v_Log2_f32/1k   1.44µs ± 4%  1.50µs ± 9%   +3.91%  (p=0.001 n=16+17)
BM_eigen_v_Log2_f32/10k  14.5µs ±10%  15.0µs ± 8%   +3.92%  (p=0.002 n=16+19)
```

Reviewed By: ezhulenev

Differential Revision: https://reviews.llvm.org/D98282
2021-03-10 14:49:22 -08:00
Dave Lee 683e89722a Revert "[cmake] Enable -Werror=return-type"
This reverts commit ce94a16165.
2021-03-10 14:47:08 -08:00
Stephen Kelly d627a27d26 [AST] Add generator for source location introspection
Generate a json file containing descriptions of AST classes and their
public accessors which return SourceLocation or SourceRange.

Use the JSON file to generate a C++ API and implementation for accessing
the source locations and method names for accessing them for a given AST
node.

This new API can be used to implement 'srcloc' output in clang-query:

  http://ce.steveire.com/z/m_kTIo

In this first version of this feature, only the accessors for Stmt
classes are generated, not Decls, TypeLocs etc.  Those can be added
after this change is reviewed, as this change is mostly about
infrastructure of these code generators.

Differential Revision: https://reviews.llvm.org/D93164
2021-03-10 22:38:39 +00:00
Jan Kratochvil 08d33aa680 [nfc] [lldb] Remove variable ranges_base in DWARFUnit::AddUnitDIE 2021-03-10 23:36:07 +01:00
Aditya Kumar 6976255faf Add noreturn attribute to non-returning functions
Differential Revision: https://reviews.llvm.org/D97308
2021-03-10 14:35:50 -08:00
Wael Yehia be646e3148 llvm-lto: default Relocation Model should be selected by the TargetMachine.
Right now, the createTargetMachine function in LTOBackend.cpp (used by llvm-lto, and other components) selects the default Relocation Model when none is specified in the module.
Other components (such as opt and llc) that construct a TargetMachine delegate the decision on the default value to the polymorphic TargetMachine's constructor.

This commit aligns llvm-lto with other components.

Reviewed By: daltenty, fhahn

Differential Revision: https://reviews.llvm.org/D97507
2021-03-10 17:31:26 -05:00
David Green 1a808286ef [AArch64] Extend vecreduce -> udot handling to mla reductions
We previously have lowering for:
  vecreduce.add(zext(X)) to vecreduce.add(UDOT(zero, X, one))
This extends that to also handle:
  vecreduce.add(mul(zext(X), zext(Y)) to vecreduce.add(UDOT(zero, X, Y))
It extends the existing code to optionally handle a mul with equal
extends.

Differential Revision: https://reviews.llvm.org/D97280
2021-03-10 22:25:12 +00:00
kuterd d75c9e61a5 [Attributor] Attributor call site specific AAValueConstantRange
This patch makes uses of the context bridges introduced in D83299 to make
AAValueConstantRange call site specific.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D83744
2021-03-11 01:19:44 +03:00
Dave Lee daf3699869 [lldb] Ignore linkage diagnostic for LLDBSwigPythonBreakpointCallbackFunction (NFC)
Ignore `-Wreturn-type-c-linkage` diagnostics for `LLDBSwigPythonBreakpointCallbackFunction`.

The function is defined in `python-wrapper.swig` which uses `extern "C" { ... }` blocks.
The declaration of this function in `ScriptInterpreterPython.cpp` already uses these
same pragmas to silence the warning there.

This prevents `-Werror` builds from failing.

Differential Revision: https://reviews.llvm.org/D98368
2021-03-10 14:15:54 -08:00
Vedant Kumar ac29c35207 [lldb/Platform] Skip very slow xcrun queries for simulator platforms, NFC
GetXcodeSDK() consistently takes over 1 second to complete if the
queried SDK is missing, because `xcrun` doesn't cache negative lookups.

Because there are multiple simulator platforms, this can add 4+ seconds
to `lldb -b some_object_file.o`.

To work around this, skip the call to GetXcodeSDK() when setting up
simulator platforms if the specified arch doesn't have what looks like a
simulator triple.

Some other ways to fix this:
- Fix caching in xcrun (rdar://74882205)
- Test for arch compat before calling SomePlatform::CreateInstance() (much
  larger change)

Differential Revision: https://reviews.llvm.org/D98272
2021-03-10 13:57:10 -08:00
Arnamoy Bhattacharyya 361e9bf97e [flang][driver] Formatting OpenMP sema check as per clang-format 2021-03-10 16:54:07 -05:00
Quentin Colombet 49942c6d4a [NFC] Fix a compiler warning
Fix a warning caused by -Wrange-loop-analysis

Patch by Xiaoqing Wu <xiaoqing_wu@apple.com>

Differential Revision: https://reviews.llvm.org/D98297
2021-03-10 13:28:53 -08:00
David Green a02f506876 [AArch64] Extend vecreduce -> udot handling to v8i8
https://reviews.llvm.org/D88577 added v16i8 vecreduce to udot/sdot
lowering. This extends that to v8i8 too, generalizing the pattern to
handle the extra types.

Differential Revision: https://reviews.llvm.org/D97279
2021-03-10 21:03:15 +00:00
Mauri Mustonen 0de8aeae72
[VPlan] Support to widen select intructions in VPlan native path
Add support to widen select instructions in VPlan native path by using a correct recipe when such instructions are encountered. This is already used by inner loop vectorizer.

Previously select instructions get handled by the wrong recipe and resulted in unreachable instruction errors like this one: https://bugs.llvm.org/show_bug.cgi?id=48139.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D97136
2021-03-10 20:59:53 +00:00
Giorgis Georgakoudis bf58d6a1f9 Replace func name with regex in update_cc_test_checks
The patch adds an argument to update_cc_test_checks for replacing a function name matching a regex. This functionality is needed to match generated function signatures that include file hashes. Example:

The function signature for the following function:

`__omp_offloading_50_b84c41e__Z9ftemplateIiET_i_l30_worker`

with `--replace-function-regex "__omp_offloading_[0-9]+_[a-z0-9]+_(.*)"` will become:

`CHECK-LABEL: @{{__omp_offloading_[0-9]+_[a-z0-9]+__Z9ftemplateIiET_i_l30_worker}}(`

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D97107
2021-03-10 12:57:35 -08:00
Christian Sigg 6a291ed0f0 [mlir] Remove unnecessary copying of pass options
I missed a comment in D98279 that you don't need to copy pass options.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D98366
2021-03-10 21:55:28 +01:00
Alexey Lapshin 4f16e177e1 [llvm-objcopy][NFC] replace class Buffer/MemBuffer/FileBuffer with streams.
During D88827 it was requested to remove the local implementation
of Memory/File Buffers:

// TODO: refactor the buffer classes in LLVM to enable us to use them here
// directly.

This patch uses raw_ostream instead of Buffers. Generally, using streams
could allow us to reduce memory usages. No need to load all data into the
memory - the data could be streamed through a smaller buffer.
Thus, this patch uses raw_ostream as an interface for output data:

Error executeObjcopyOnBinary(CopyConfig &Config,
                             object::Binary &In,
                             raw_ostream &Out);

Note 1. This patch does not change the implementation of Writers
so that data would be directly stored into raw_ostream.
This is assumed to be done later.

Note 2. It would be better if Writers would be implemented in a such way
that data could be streamed without seeking/updating. If that would be
inconvenient then raw_ostream could be replaced with raw_pwrite_stream
to have a possibility to seek back and update file headers.
This is assumed to be done later if necessary.

Note 3. Current FileOutputBuffer allows using a memory-mapped file.
The raw_fd_ostream (which could be used if data should be stored in the file)
does not allow us to use a memory-mapped file. Memory map functionality
could be implemented for raw_fd_ostream:

It is possible to add resize() method into raw_ostream.

class raw_ostream {
  void resize(uint64_t size);
}

That method, implemented for raw_fd_ostream, could create a memory-mapped file.
The streamed data would be written into that memory file then.
Thus we would be able to use memory-mapped files with raw_fd_ostream.
This is assumed to be done later if necessary.

Differential Revision: https://reviews.llvm.org/D91028
2021-03-10 23:50:04 +03:00
Weiwei Li 619c1505f9 [mlir][spirv] Define spv.Image Operation
co-authered-by: Alan Liu <alanliu.yf@gmail.com>

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D98270
2021-03-10 15:48:04 -05:00
Stanislav Mekhanoshin 9931b1f7a4 [AMDGPU] Disable SCC bit on fp atomics
Differential Revision: https://reviews.llvm.org/D98221
2021-03-10 12:36:09 -08:00
Stanislav Mekhanoshin 574a9dabc6 [AMDGPU] Always expand system scope fp atomics on gfx90a
FP atomics in system scope cannot be used and shall always
be expanded in a CAS loop.

Differential Revision: https://reviews.llvm.org/D98085
2021-03-10 12:35:23 -08:00
Giorgis Georgakoudis a2abe2259c Run non-filechecked commands in update_cc_test_checks.py
Some tests in clang require running non-filechecked commands to generate the actual filecheck input. For example, tests for openmp offloading require generating the host bc without any checking, before running the clang command to actually generate the filechecked IR of the target device. This patch enables `update_cc_test_checks.py` to run non-filechecked run lines in-place.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D97068
2021-03-10 12:25:35 -08:00
George Balatsouras 05c2c8aaa8 [dfsan] Update fast16labels.ll test
Remove hard-coded shadow width references. Separate CHECK lines that only apply to fast16 mode.

Reviewed By: stephan.yichao.zhao

Differential Revision: https://reviews.llvm.org/D98308
2021-03-10 12:13:11 -08:00
Matteo Favaro 989051d5f8 [DSE] Extending isOverwrite to support offsetted fully overlapping stores
The isOverwrite function is making sure to identify if two stores
are fully overlapping and ideally we would like to identify all the
instances of OW_Complete as they'll yield possibly killable stores.
The current implementation is incapable of spotting instances where
the earlier store is offsetted compared to the later store, but
still fully overlapped. The limitation seems to lie on the
computation of the base pointers with the
GetPointerBaseWithConstantOffset API that often yields different
base pointers even if the stores are guaranteed to partially overlap
(e.g. the alias analysis is returning AliasResult::PartialAlias).

The patch relies on the offsets computed and cached by BatchAAResults
(available after D93529) to determine if the offsetted overlapping
is OW_Complete.

Differential Revision: https://reviews.llvm.org/D97676
2021-03-10 21:09:33 +01:00
Greg McGary 98fe9e41f7 [lld-macho][NFC] add const to pointer/reference induction variables of range-based for loops
Pointer and reference induction variables of range-based for loops are often const, and code authors often lax about qualifying them.

Differential Revision: https://reviews.llvm.org/D98317
2021-03-10 12:07:31 -08:00