Commit Graph

2655 Commits

Author SHA1 Message Date
Eric Christopher bebb8c5f86 Hack around extracts that aren't easy to process.
llvm-svn: 109043
2010-07-21 22:07:19 +00:00
Bob Wilson ebcaddee44 Add support for a new Apple-style build target, EmbeddedSim, that builds
llvmCore for the iOS Simulator.

llvm-svn: 108922
2010-07-20 20:44:02 +00:00
Chris Lattner 394f1c2a27 remove option from tablegen for building static header.
llvm-svn: 108893
2010-07-20 19:45:21 +00:00
Bruno Cardoso Lopes 9de0ca73d4 Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
llvm-svn: 108769
2010-07-19 23:32:44 +00:00
Bob Wilson a7d44a1ab6 Save a copy of the unstripped libLTO.dylib in $SYM_DIR. Clean up the code
for dealing with libLTO.dylib to put it all in one place and to allow
use of DISABLE_USR_LINKS.

llvm-svn: 108753
2010-07-19 21:33:07 +00:00
Mikhail Glushenkov 1432699cb2 Remove code duplication.
llvm-svn: 108718
2010-07-19 17:17:22 +00:00
Mikhail Glushenkov 4fc84a0dcd Better error reporting for switch_list.
llvm-svn: 108714
2010-07-19 17:17:10 +00:00
Daniel Dunbar eefe8616be TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> attributes as part of the matcher.
- Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.

llvm-svn: 108677
2010-07-19 05:44:09 +00:00
Mikhail Glushenkov 303838d69f llvmc: Add a new option type (switch_list).
llvm-svn: 108673
2010-07-19 03:16:25 +00:00
Bill Wendling 004d772558 Update comment.
llvm-svn: 108571
2010-07-16 23:10:00 +00:00
Bill Wendling 499f797cdd Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.

llvm-svn: 108563
2010-07-16 22:20:36 +00:00
Bob Wilson 5d2c1218f1 Remove the entire docs directory from Apple-style builds.
This fixes a "usr_junk" verification failure when installing into /usr.

llvm-svn: 108384
2010-07-14 23:49:18 +00:00
Bob Wilson 6f4f3612cc Try to get embedded build of llvmCore to pass verification.
Simplify some things in the process.

llvm-svn: 108382
2010-07-14 23:41:58 +00:00
Jakob Stoklund Olesen f059642c50 Silence a warning.
llvm-svn: 108169
2010-07-12 18:17:47 +00:00
Duncan Sands 41b4a6b36a Convert some tab stops into spaces.
llvm-svn: 108130
2010-07-12 08:16:59 +00:00
Jakob Stoklund Olesen 4a52e2f6a7 Replace copyRegToReg with COPY in FastISelEmitter.
llvm-svn: 108071
2010-07-11 03:53:50 +00:00
Dan Gohman d7b5ce3312 Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.

llvm-svn: 108039
2010-07-10 09:00:22 +00:00
Bruno Cardoso Lopes 792e906bef Start the support for AVX instructions with 256-bit %ymm registers. A couple of
notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.

llvm-svn: 107996
2010-07-09 18:27:43 +00:00
Bob Wilson 6586e9b203 --- Reverse-merging r107947 into '.':
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 107987
2010-07-09 16:37:18 +00:00
Dan Gohman cc40c76382 These changes should have accompanied r107943.
llvm-svn: 107947
2010-07-09 00:59:16 +00:00
Dale Johannesen e2289285ae Changes to ARM tail calls, mostly cosmetic.
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851
2010-07-08 01:18:23 +00:00
Dan Gohman e75704369d Revert 107840 107839 107813 107804 107800 107797 107791.
Debug info intrinsics win for now.

llvm-svn: 107850
2010-07-08 01:00:56 +00:00
Chris Lattner ac5881295c Implement the major chunk of PR7195: support for 'callw'
in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825
2010-07-07 22:27:31 +00:00
Dan Gohman ffe64b1ee5 Give FunctionLoweringInfo an MBB member, avoiding the need to pass it
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.

llvm-svn: 107791
2010-07-07 16:47:08 +00:00
Duncan Sands 408bb192de Rename "Release" builds as "Release+Asserts"; rename "Release-Asserts"
builds to "Release".  The default build is unchanged (optimization on,
assertions on), however it is now called Release+Asserts.  The intent
is that future LLVM releases released via llvm.org will be Release builds
in the new sense, i.e. will have assertions disabled (currently they have
assertions enabled, for a more than 20% slowdown).  This will bring them
in line with MacOS releases, which ship with assertions disabled.  It also
means that "Release" now means the same things in make and cmake builds:
cmake already disables assertions for "Release" builds AFAICS.

llvm-svn: 107758
2010-07-07 07:48:00 +00:00
Jakob Stoklund Olesen 676a15bdf5 Add a new target independent COPY instruction and code to lower it.
The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.

COPY is lowered to native register copies by LowerSubregs.

llvm-svn: 107529
2010-07-02 22:29:50 +00:00
Jakob Stoklund Olesen 3b1657b777 Clean up TargetOpcodes.h a bit, and limit the number of places where the full
list of predefined instructions appear. Add some consistency checks.

Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it
is hardly worth the effort.

llvm-svn: 107520
2010-07-02 21:44:22 +00:00
Bill Wendling 7839c493e8 Use -l option to remove symbols from i386.
llvm-svn: 107212
2010-06-29 22:17:37 +00:00
Bill Wendling 9a925bec36 Strip resulting binaries.
llvm-svn: 107112
2010-06-29 01:08:57 +00:00
Duncan Sands cfdaac1cb0 Remove unused variables.
llvm-svn: 106834
2010-06-25 09:35:33 +00:00
Bob Wilson 99f28dad6e Change array references to match my previous change to use the public type
names for the array fields.

llvm-svn: 106803
2010-06-24 22:21:19 +00:00
Bob Wilson e26d710335 Fix up some comments.
llvm-svn: 106795
2010-06-24 22:04:30 +00:00
Bob Wilson 3808684055 Use the struct tags mandated by ARM's ABI. Also use the public type names for
the array fields in these structs.

llvm-svn: 106794
2010-06-24 22:03:41 +00:00
Nico Weber 337e8db712 Add support for the x86 instructions "pusha" and "popa".
llvm-svn: 106671
2010-06-23 20:00:58 +00:00
Bruno Cardoso Lopes 30a28d6588 Fix a tblgen bug.
Given the pattern below as an example:
list<dag> Pattern = [(set RC:$dst, (v4f32 (shufp:src3 RC:$src1,
                            (mem_frag addr:$src2))))];

The right reference resolving should lead to:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp:src3 VR128:$src1,
                            (mem_frag addr:$src2))))];
But was yielding:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp VR128:$src1,
                            (mem_frag addr:$src2))))];

Fix this by passing the right name when creating a new DagInit node.

llvm-svn: 106670
2010-06-23 19:50:39 +00:00
Nick Lewycky 99d71d1e7a Don't link against libm and libpthread which don't exist in BeOS/Haiku. Also,
Haiku like Linux provides <regex.h>, so use it. Patch by Paul Davey!

llvm-svn: 106620
2010-06-23 06:48:34 +00:00
Bill Wendling 8d87a1f30a Generate DWARF information during Apple-style build. They'll be stripped out
later on. But we need them saved in the symbols directory.

llvm-svn: 106604
2010-06-22 23:44:15 +00:00
Bruno Cardoso Lopes dc883cf45a Fix a subtle multiclass bug: when using class inheritance on
a toplevel 'defm', make sure to properly resolve references.

llvm-svn: 106570
2010-06-22 20:30:50 +00:00
Eric Christopher 75d4ecb9c3 Remove isTwoAddress from llvm.
llvm-svn: 106470
2010-06-21 20:35:09 +00:00
Nate Begeman 4713628816 Add support for returning multiple vectors via sret, which is how the ARM target expects the intrinsics to work.
llvm-svn: 106406
2010-06-20 21:09:52 +00:00
Dale Johannesen a06c2f79fc An attempt to fix the problem Anton reported with
ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.

llvm-svn: 106309
2010-06-18 20:44:28 +00:00
Bruno Cardoso Lopes 23f8321cbc Teach tablegen how to inherit from classes in 'defm' definitions.
The rule is simple: only inherit from a class list if they come
in the end, after the last multiclass.

llvm-svn: 106305
2010-06-18 19:53:41 +00:00
Dan Gohman 882bb2984e Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.

llvm-svn: 106296
2010-06-18 18:13:55 +00:00
Bruno Cardoso Lopes deb2002cee In case Rec is a definition and not a class, do the proper comparison!
llvm-svn: 106246
2010-06-17 23:00:16 +00:00
Nate Begeman 256b5a2bff Modify tablegen to support generating all NEON code used by clang at once.
llvm-svn: 106207
2010-06-17 04:15:13 +00:00
Bruno Cardoso Lopes 7f4235d1ba Fix the handling of !if result, avoiding null results for non 'int'.
llvm-svn: 106201
2010-06-17 01:50:39 +00:00
Bruno Cardoso Lopes 4d1d798736 For a tablegen expression such as !if(a,b,c), let 'a'
be evaluated for 'bit' operators

llvm-svn: 106185
2010-06-17 00:31:36 +00:00
Alexis Hunt 0f184c0328 Fix the typo in my previous one-line commit.
llvm-svn: 106179
2010-06-17 00:10:16 +00:00
Alexis Hunt 873f7aff62 Make sure CMake can build the files added by my previous commit.
llvm-svn: 106178
2010-06-16 23:52:37 +00:00
Alexis Hunt 842eb0905e Add preliminary clang attribute generation support.
The attribute class generation support is still somewhat limited.
See the accompanying clang commit for more details.

llvm-svn: 106174
2010-06-16 23:45:50 +00:00