llvm-project

Commit Graph

Author	SHA1	Message	Date
James Y Knight	7c905063c5	Make utils/update_llc_test_checks.py note that the assertions are autogenerated. Also update existing test cases which appear to be generated by it and weren't modified (other than addition of the header) by rerunning it. llvm-svn: 253917	2015-11-23 21:33:58 +00:00
Simon Pilgrim	e88dc04c48	[X86][XOP] Add support for the matching of the VPCMOV bit select instruction XOP has the VPCMOV instruction that performs the common vector bit select operation OR( AND( SRC1, SRC3 ), AND( SRC2, ~SRC3 ) ) This patch adds tablegen pattern matching for this instruction. Differential Revision: http://reviews.llvm.org/D8841 llvm-svn: 251975	2015-11-03 20:27:01 +00:00

Author

SHA1

Message

Date

James Y Knight

7c905063c5

Make utils/update_llc_test_checks.py note that the assertions are

autogenerated.

Also update existing test cases which appear to be generated by it and
weren't modified (other than addition of the header) by rerunning it.

llvm-svn: 253917

2015-11-23 21:33:58 +00:00

Simon Pilgrim

e88dc04c48

[X86][XOP] Add support for the matching of the VPCMOV bit select instruction

XOP has the VPCMOV instruction that performs the common vector bit select operation OR( AND( SRC1, SRC3 ), AND( SRC2, ~SRC3 ) )

This patch adds tablegen pattern matching for this instruction.

Differential Revision: http://reviews.llvm.org/D8841

llvm-svn: 251975

2015-11-03 20:27:01 +00:00

2 Commits