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10 Commits

Author SHA1 Message Date
Craig Topper 504fba5c8a [AVX512] Lower v8i64 and v16i32 to pshufd when possible. 
llvm-svn: 272473
 2016-06-11 13:43:21 +00:00
Simon Pilgrim 643734c565 [X86][AVX512] Added avx512 VPSLLDQ/VPSRLDQ instruction comments 
llvm-svn: 272319
 2016-06-09 22:03:15 +00:00
Simon Pilgrim 0ab9d3026a [X86][AVX512] Added support for lowering 512-bit vector shuffles to bit/byte shifts 
512-bit VPSLLDQ/VPSRLDQ can only be used for avx512bw targets so lowerVectorShuffleAsShift had to be adjusted to include the subtarget

llvm-svn: 272300
 2016-06-09 20:13:58 +00:00
Craig Topper 7a2993093e [X86] Bring consistent naming to the SSE/AVX and AVX512 PALIGNR instructions. Then add shuffle decode printing for the EVEX forms which is made easier by having the naming structure more similar to other instructions. 
llvm-svn: 272249
 2016-06-09 07:06:38 +00:00
Craig Topper 143446d5c1 [AVX512] Add PALIGNR shuffle lowering for v32i16 and v16i32. 
llvm-svn: 271870
 2016-06-06 05:39:10 +00:00
Michael Kuperstein 738ae45ce8 [DAG] Improve legalization of INSERT_SUBVECTOR 
When the index is known to be constant 0, insert directly into the the low half,
instead of spilling, performing the insert in-memory, and reloading.

Differential Revision: http://reviews.llvm.org/D20763

llvm-svn: 271428
 2016-06-01 20:49:35 +00:00
Sanjay Patel 97c2c108fd [x86] avoid printing unnecessary sign bits of hex immediates in asm comments (PR20347) 
It would be better to check the valid/expected size of the immediate operand, but this is
generally better than what we print right now.

Differential Revision: http://reviews.llvm.org/D20385

llvm-svn: 271114
 2016-05-28 14:58:37 +00:00
Michael Kuperstein a75c77b127 [X86] Detect SAD patterns and emit psadbw instructions. 
This recommits r267649 with a fix for PR27539.

Differential Revision: http://reviews.llvm.org/D20598

llvm-svn: 271033
 2016-05-27 18:53:22 +00:00
Nico Weber e69b9548b8 Revert r267649, it caused PR27539. 
llvm-svn: 267723
 2016-04-27 15:16:54 +00:00
Cong Hou 6f879d9eb1 Detects the SAD pattern on X86 so that much better code will be emitted once the pattern is matched. 
Differential revision: http://reviews.llvm.org/D14840

llvm-svn: 267649
 2016-04-27 01:29:18 +00:00