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61 Commits

Author SHA1 Message Date
Zlatko Buljan 252cca555f [mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV and WRDSP instructions 
Differential Revision: http://reviews.llvm.org/D14429

llvm-svn: 255991
 2015-12-18 08:59:37 +00:00
Hrvoje Varga 672b0f5582 [mips][microMIPS] Implement PREPEND, RADDU.W.QB, RDDSP, REPL.PH, REPL.QB, REPLV.PH, REPLV.QB and MTHLIP instructions 
Differential Revision: http://reviews.llvm.org/D14527

llvm-svn: 254496
 2015-12-02 09:31:24 +00:00
Hrvoje Varga c03957f049 [mips][microMIPS] Implement LBUX, LHX, LWX, MAQ_S[A].W.PHL, MAQ_S[A].W.PHR, MFHI, MFLO, MTHI and MTLO instructions 
Differential Revision: http://reviews.llvm.org/D14436

llvm-svn: 254297
 2015-11-30 12:58:39 +00:00
Zlatko Buljan 56f3b0e410 [mips][microMIPS] Implement PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W, PRECRQ.QB.PH, PRECRQU_S.QB.PH and PRECRQ_RS.PH.W instructions 
Differential Revision: http://reviews.llvm.org/D14605

llvm-svn: 254291
 2015-11-30 08:37:38 +00:00
Daniel Sanders daa4b6fbd9 [mips][ias] Range check uimm5 operands and fix several bugs this revealed. 
Summary:
The bugs were:
* append, prepend, and balign were not tested
* balign takes a uimm2 not a uimm5.
* drotr32 was correctly implemented with a uimm5 but the tests expected
  '52' to be valid.
* li/la were implemented with a uimm5 instead of simm32. simm32 isn't
  completely correct either but I'll fix that when I get to simm32.

A notable omission are some of the shift instructions. Several of these
have been implemented using a single uimm6 instruction (rather than two
uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated
in the uimm6 patch.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D14712

llvm-svn: 254164
 2015-11-26 16:35:41 +00:00
Hrvoje Varga b65518c15c [mips][microMIPS] Implement MUL[_S].PH, MULEQ_S.W.PHL, MULEQ_S.W.PHR, MULEU_S.PH.QBL, MULEU_S.PH.QBR, MULQ_RS.PH, MULQ_RS.W, MULQ_S.PH and MULQ_S.W instructions 
Differential Revision: http://reviews.llvm.org/D14280

llvm-svn: 253651
 2015-11-20 07:14:52 +00:00
Hrvoje Varga 78409019d9 [mips][microMIPS] Implement DPS.W.PH, DPSQ_S.W.PH, DPSQ_SA.L.W, DPSQX_S.W.PH, DPSQX_SA.W.PH, DPSU.H.QBL, DPSU.H.QBR and DPSX.W.PH instructions 
Differential Revision: http://reviews.llvm.org/D14058

llvm-svn: 253443
 2015-11-18 07:41:35 +00:00
Zlatko Buljan 72a7f9c1f5 [mips][microMIPS] Implement EXTP, EXTPDP, EXTPDPV, EXTPV, EXTR[_RS].W, EXTR_S.H, EXTRV[_RS].W and EXTRV_S.H instructions 
Differential Revision: http://reviews.llvm.org/D14174

llvm-svn: 253332
 2015-11-17 12:54:15 +00:00
Zlatko Buljan 246b21f66a [mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions 
Differential Revision: http://reviews.llvm.org/D14114

llvm-svn: 253329
 2015-11-17 10:11:22 +00:00
Zlatko Buljan 3e0588d033 [mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions 
Differential Revision: http://reviews.llvm.org/D14279

llvm-svn: 253326
 2015-11-17 09:43:29 +00:00
Zlatko Buljan 32fb5c40d2 [mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions 
Differential Revision: http://reviews.llvm.org/D14010

llvm-svn: 253041
 2015-11-13 13:14:25 +00:00
Zlatko Buljan 2cf61020b8 [mips][microMIPS] Implement SHLL.PH, SHLL_S.PH, SHLL.QB, SHLLV.PH, SHLLV_S.PH, SHLLV.QB, SHLLV_S.W, SHLL_S.W, SHRA.QB and SHRA_R.QB instructions 
Differential Revision: http://reviews.llvm.org/D13929

llvm-svn: 251098
 2015-10-23 06:39:29 +00:00
Daniel Sanders 0f596814e9 [mips][msa] Remove copy_u.d and move copy_u.w to MSA64. 
Summary:
The forwards compatibility strategy employed by MIPS is to consider registers
to be infinitely sign-extended. Then on ISA's with a wider register, the result
of existing instructions are sign-extended to register width and zero-extended
counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this
strategy and we have therefore corrected the MSA specs to fix this.

We still keep track of sign/zero-extension during legalization but we now
match copy_s.[wd] where required.

No change required to clang since __builtin_msa_copy_u_[wd] will map to
copy_s.[wd] where appropriate for the target.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13472

llvm-svn: 250887
 2015-10-21 09:58:54 +00:00
Zlatko Buljan 5292083584 [mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions 
Differential Revision: http://reviews.llvm.org/D13130

llvm-svn: 250685
 2015-10-19 07:16:26 +00:00
Zlatko Buljan d0a7d6e4ee [mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions 
Differential Revision: http://reviews.llvm.org/D13721

llvm-svn: 250683
 2015-10-19 06:34:44 +00:00
Zlatko Buljan 54b1eb4c73 [mips][microMIPS] Implement DPA.W.PH, DPAQ_S.W.PH, DPAQ_SA.L.W, DPAQX_S.W.PH, DPAQX_SA.W.PH, DPAU.H.QBL, DPAU.H.QBR and DPAX.W.PH instructions 
Differential Revision: http://reviews.llvm.org/D13376

llvm-svn: 250382
 2015-10-15 08:59:45 +00:00
Zoran Jovanovic 2e386d3d07 [mips][micromips] Initial support for micrmomips DSP instructions and addu.qb implementation 
Differential Revision: http://reviews.llvm.org/D12798

llvm-svn: 250058
 2015-10-12 16:07:25 +00:00
Akira Hatanaka 06aff571a3 [mips] Define a pseudo instruction which writes to both the lower and higher 
parts of the accumulators and gets expanded post-RA.

llvm-svn: 192667
 2013-10-15 01:48:30 +00:00
Akira Hatanaka ec67c90216 [mips] Use predicates to guard instructions using accumulator registers instead 
of relying on AddedComplexity.

llvm-svn: 192665
 2013-10-15 01:21:37 +00:00
Akira Hatanaka d98c99fd01 [mips] Rename isel nodes. 
llvm-svn: 192663
 2013-10-15 01:12:50 +00:00
Akira Hatanaka 16048332f1 [mips] Fix definition of mfhi and mflo instructions to read from the whole 
accumulator instead of its sub-registers, $hi and $lo. 

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2     // read lower 32-bit result from $lo.
mtlo $4     // write to $lo. the content of $hi becomes unpredictable.
mfhi $3     // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.

llvm-svn: 192119
 2013-10-07 18:49:46 +00:00
Akira Hatanaka 3121353c99 [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit 
into a 5-bit or 6-bit field.

llvm-svn: 190226
 2013-09-07 00:02:02 +00:00
Akira Hatanaka 9bfa2e2e7f [mips] Use ptr_rc to simplify definitions of base+index load/store instructions. 
Also, fix predicates.

llvm-svn: 189432
 2013-08-28 00:55:15 +00:00
Akira Hatanaka 6781fc1648 [mips] Resolve register classes dynamically using ptr_rc to reduce the number of 
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.

llvm-svn: 188830
 2013-08-20 21:08:22 +00:00
Akira Hatanaka feb7ee84c5 [mips] Use register operands instead of register classes in DSP instruction 
definitions.

llvm-svn: 188343
 2013-08-14 01:02:20 +00:00
Akira Hatanaka 654655f1c5 [mips] Rename DSPRegs. 
llvm-svn: 188342
 2013-08-14 00:53:38 +00:00
Akira Hatanaka 8002a3f6d8 [mips] Rename HIRegs and LORegs. 
llvm-svn: 188341
 2013-08-14 00:47:08 +00:00
Akira Hatanaka 00fcf2e169 [mips] Rename accumulator register classes and FP register operands. 
llvm-svn: 188020
 2013-08-08 21:54:26 +00:00
Akira Hatanaka 6bf3c03861 [mips] Mark pseudo instructions as code-gen only. 
llvm-svn: 188017
 2013-08-08 21:44:39 +00:00
Akira Hatanaka 13e6ccf341 [mips] Rename register classes CPURegs and CPU64Regs. 
llvm-svn: 187832
 2013-08-06 23:08:38 +00:00
Akira Hatanaka 34a32c0b87 [mips] Replace usages of register classes with register operands. Also, remove 
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.

llvm-svn: 187821
 2013-08-06 22:20:40 +00:00
Akira Hatanaka e86bd4f652 [mips] Split the DSP control register and define one register for each field of 
its fields.

This removes false dependencies between DSP instructions which access different
fields of the the control register. Implicit register operands are added to
instructions RDDSP and WRDSP after instruction selection, depending on the
value of the mask operand.

llvm-svn: 181041
 2013-05-03 18:37:49 +00:00
Akira Hatanaka 5705f546e5 [mips] Handle reading, writing or copying of ccond field of DSP control 
register.

- Define pseudo instructions which store or load ccond field of the DSP
  control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. 

llvm-svn: 180969
 2013-05-02 23:07:05 +00:00
Akira Hatanaka 4254319ef9 [mips] Fix handling of instructions which copy to/from accumulator registers. 
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.

llvm-svn: 180827
 2013-04-30 23:22:09 +00:00
Akira Hatanaka 68741cc38d [mips] Instruction selection patterns for DSP-ASE vector select and compare 
instructions.

llvm-svn: 180820
 2013-04-30 22:37:26 +00:00
Akira Hatanaka 84d6d9bdaa [mips] Clear isCommutable bit of instructions which are not commutable. 
llvm-svn: 180801
 2013-04-30 20:40:39 +00:00
Akira Hatanaka 0d6964cf4a [mips] In performDSPShiftCombine, check that all elements in the vector are 
shifted by the same amount and the shift amount is smaller than the element
size.

llvm-svn: 180039
 2013-04-22 19:58:23 +00:00
Akira Hatanaka 1ebb2a1c56 [mips] Instruction selection patterns for DSP-ASE vector shifts. 
llvm-svn: 179906
 2013-04-19 23:21:32 +00:00
Akira Hatanaka 59bfaf774b [mips] DSP-ASE move from HI/LO register instructions. 
llvm-svn: 179739
 2013-04-18 00:52:44 +00:00
Akira Hatanaka 2f08822f9d [mips] Reapply r179420 and r179421. 
llvm-svn: 179434
 2013-04-13 00:55:41 +00:00
Akira Hatanaka 8ed2892c1c Revert r179420 and r179421. 
llvm-svn: 179422
 2013-04-12 22:40:07 +00:00
Akira Hatanaka 931ad87f6a [mips] Instruction selection patterns for carry-setting and using add 
instructions.

llvm-svn: 179421
 2013-04-12 22:24:52 +00:00
Akira Hatanaka 8f41dd923e [mips] v4i8 and v2i16 add, sub and mul instruction selection patterns. 
llvm-svn: 179420
 2013-04-12 22:14:24 +00:00
Akira Hatanaka b3c1847b30 [mips] Add patterns for DSP indexed load instructions. 
llvm-svn: 178408
 2013-03-30 02:14:45 +00:00
Akira Hatanaka fb221c197d [mips] Fix DSP instructions to have explicit accumulator register operands. 
Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.

llvm-svn: 178406
 2013-03-30 01:58:00 +00:00
Akira Hatanaka c8d85025a0 [mips] Define pseudo instructions for spilling and copying accumulator 
registers.

llvm-svn: 178390
 2013-03-30 00:54:52 +00:00
Akira Hatanaka b1527b7505 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass 
parameter.

llvm-svn: 170661
 2012-12-20 04:20:09 +00:00
Akira Hatanaka 02ec5516f8 [mips] Move class IsCommutable into MipsInstrInfo.td. 
llvm-svn: 170054
 2012-12-13 00:32:01 +00:00
Akira Hatanaka d66f489640 MIPS DSP: other miscellaneous instructions. 
llvm-svn: 164845
 2012-09-28 20:50:31 +00:00
Akira Hatanaka 334dad6aea MIPS DSP: ADDUH.QB instruction sub-class. 
llvm-svn: 164840
 2012-09-28 20:16:04 +00:00