1d5c2d9227
Add AVX version of a SSE4.1 VPBLENDVB pattern
...
llvm-svn: 139072
2011-09-03 00:47:05 +00:00
212a8c4357
Add AVX versions of SSE4.1 EXTRACTPS patterns
...
llvm-svn: 139071
2011-09-03 00:47:03 +00:00
3d581a36b6
Add AVX versions for SSE4.1 MOVZX* patterns
...
llvm-svn: 139070
2011-09-03 00:47:01 +00:00
6d701fcef0
Add one more AVX pattern for MOVZPQILo2PQI
...
llvm-svn: 139069
2011-09-03 00:46:58 +00:00
9923c51564
Move PUNPCKLQDQ splat pattern close to the instruction definition and
...
duplicate it for AVX mode.
llvm-svn: 139068
2011-09-03 00:46:56 +00:00
96b11f39e2
Add AVX pattern versions for PSHUFB,PSIGN{B,W,D}
...
llvm-svn: 139067
2011-09-03 00:46:54 +00:00
9a0da1e57a
Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicate
...
that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.
llvm-svn: 139066
2011-09-03 00:46:51 +00:00
903952223a
Enforce subtarget checks in a few places to be explicit when the
...
pattern should be matched
llvm-svn: 139065
2011-09-03 00:46:49 +00:00
521b0cfdc6
Tidy up code moving patterns to their appropriate place!
...
llvm-svn: 139064
2011-09-03 00:46:47 +00:00
aad5e50ded
Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use
...
it!
llvm-svn: 139063
2011-09-03 00:46:45 +00:00
d893fc92af
Teach X86FastISel to use AVX versions of instructions when possible
...
llvm-svn: 139062
2011-09-03 00:46:42 +00:00
006c9371a1
Fix 80-column and style
...
llvm-svn: 139061
2011-09-03 00:46:40 +00:00
dbb40015ff
Tidy up some SSE/AVX convert intrinsics. Also add an AVX version of
...
OptForSize pattern
llvm-svn: 139060
2011-09-03 00:46:38 +00:00
40d756eacc
Fix a truly heinous bug in DAGCombine related to AssertZext.
...
If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert. The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users. No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem.
Fixes <rdar://problem/10063365>.
llvm-svn: 139059
2011-09-03 00:26:49 +00:00
5423017526
Revert r129875, XFAILing this test for arm, since the fix was reverted.
...
llvm-svn: 139058
2011-09-03 00:14:24 +00:00
1f72dd40c7
Pseudo CMOV instructions don't clobber EFLAGS.
...
The explanation about a 0 argument being materialized as xor is no
longer valid. Rematerialization will check if EFLAGS is live before
clobbering it.
The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.
This causes one less testb instruction to be generated in the cmov.ll
test case.
llvm-svn: 139057
2011-09-02 23:52:55 +00:00
f08354d183
Check for EFLAGS live-out before clobbering it.
...
It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.
llvm-svn: 139056
2011-09-02 23:52:52 +00:00
d0c8a31c8b
Use existing function.
...
llvm-svn: 139055
2011-09-02 23:52:49 +00:00
f347d1d772
Thumb2 parsing and encoding for CBZ/CBNZ.
...
llvm-svn: 139054
2011-09-02 23:46:10 +00:00
34842ceb97
Thumb2 parsing and encoding for BXJ.
...
llvm-svn: 139053
2011-09-02 23:43:09 +00:00
9e55023ca7
Thumb2 parsing and encoding for BIC.
...
llvm-svn: 139052
2011-09-02 23:37:54 +00:00
93e3fd29b2
Thumb2 parsing and encoding for BFI.
...
llvm-svn: 139051
2011-09-02 23:28:46 +00:00
be31448d99
Thumb2 parsing and encoding for BFC.
...
llvm-svn: 139050
2011-09-02 23:25:46 +00:00
a0d34d3b5e
Thumb2 parsing and encoding of B instruction.
...
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
llvm-svn: 139049
2011-09-02 23:22:08 +00:00
67ba2403e8
Attempt to silence known valgrind errors.
...
llvm-svn: 139048
2011-09-02 22:59:34 +00:00
38019e3188
Remove unused variables.
...
llvm-svn: 139047
2011-09-02 22:41:25 +00:00
4aa2573748
Try to eliminate the use of the 'unwind' instruction.
...
llvm-svn: 139046
2011-09-02 22:41:11 +00:00
f3dd6da7a8
Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
...
llvm-svn: 139044
2011-09-02 22:33:24 +00:00
a216debb37
Thumb2 parsing and encoding for ASR.
...
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
llvm-svn: 139040
2011-09-02 21:28:54 +00:00
912668d998
Better fix for this testcase. Update it to the new EH scheme entirely.
...
llvm-svn: 139039
2011-09-02 21:27:08 +00:00
17706bcffb
Update for new EH stuff. (I'm not sure if this is 100% correct.)
...
llvm-svn: 139038
2011-09-02 21:24:17 +00:00
310a448cfe
Test case update for unroll-scev.
...
llvm-svn: 139037
2011-09-02 21:21:03 +00:00
bbb226a827
Comment and clarifying assert.
...
llvm-svn: 139036
2011-09-02 21:20:46 +00:00
73e6333ce1
No need to get fancy inserting a PHI node when the values are stored in stack
...
slots. This fixes a bug where the number of nodes coming into the PHI node may
not equal the number of predecessors. E.g., two or more landingpad instructions
may require a PHI before reaching the eh.exception and eh.selector instructions.
llvm-svn: 139035
2011-09-02 21:17:08 +00:00
09d153eb12
Make RecordVal Name an Init
...
Store a RecordVal's name as an Init to allow class-qualified Record
members to reference Records that have Init names. We'll use this to
provide more programmability in how we name defs and their associated
members.
llvm-svn: 139031
2011-09-02 20:12:07 +00:00
5b03f72292
Change X86 disassembly to print immediates values as signed by default. Special
...
case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
2011-09-02 20:01:23 +00:00
05dec8b122
Tidy up. Formatting.
...
llvm-svn: 139024
2011-09-02 18:46:15 +00:00
a336e70573
Update comments to reflect reality.
...
llvm-svn: 139023
2011-09-02 18:43:33 +00:00
0a57375a28
Tidy up. 80 columns.
...
llvm-svn: 139022
2011-09-02 18:43:25 +00:00
370e923434
Thumb2 parsing and encoding for AND (register).
...
llvm-svn: 139021
2011-09-02 18:41:35 +00:00
97fe09ad2e
Simplify by using isFullCopy().
...
llvm-svn: 139019
2011-09-02 18:18:29 +00:00
4e1d018935
Revert r138826 until PR10834 can be fixed.
...
llvm-svn: 139018
2011-09-02 18:15:04 +00:00
2761155203
Thumb2 parsing and encoding for ADD (register).
...
llvm-svn: 139017
2011-09-02 18:14:46 +00:00
5c04c62765
Darwin wants ctors/dtors to be ordered the other way round to linux.
...
llvm-svn: 139015
2011-09-02 18:07:19 +00:00
54e09b4799
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
...
llvm-svn: 139014
2011-09-02 18:03:03 +00:00
b861b2b475
Tests for Thumb2 AND (immediate) instruction.
...
llvm-svn: 139013
2011-09-02 17:44:27 +00:00
63a3a0e010
Extra CHECK-NOT to make sure that GVN transform works properly.
...
llvm-svn: 139012
2011-09-02 17:40:39 +00:00
4a31ba3bae
-unroll-scev flag removal
...
llvm-svn: 139010
2011-09-02 17:36:14 +00:00
31b941a60d
Enable SCEV-based unrolling by default.
...
This changes loop unrolling to use the same mechanism for trip count
computation as indvars. This is a stronger check that tends to unroll
more loops. A very common side-effect is that many single iteration
loops will be removed sooner. The real goal was simply to remove
dependence on canonical IVs.
x86 is break even.
ARM performance changes to expect (+ is good):
External/SPEC/CFP2000/183.equake/183.equake +13%
SingleSource/Benchmarks/Dhrystone/fldry +21%
MultiSource/Applications/spiff/spiff +3%
SingleSource/Benchmarks/Stanford/Puzzle -14%
The Puzzle regression is actually an improvement in loop optimization
that defeats GVN: rdar://problem/10065079.
llvm-svn: 139009
2011-09-02 17:26:28 +00:00
c302f5cce7
Add FIXME. Thumb2 ADR encoding choice is non-trivial.
...
llvm-svn: 139008
2011-09-02 17:21:59 +00:00
59a1de1c9d
Return undef value (instead of arbitrary) for wrong or undef index in
...
ConstantVector.
llvm-svn: 139007
2011-09-02 17:01:40 +00:00
057d423e4b
ConstantVector returns arbitrary value for the wrong index.
...
This fixes PR10813.
llvm-svn: 139006
2011-09-02 15:43:43 +00:00
7470fb01d0
Compare type size instead of type _store_ size to make sure that BitCastInst
...
will be valid. This fixes PR10820.
llvm-svn: 139005
2011-09-02 14:57:37 +00:00
f5769c1070
Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.
...
llvm-svn: 139004
2011-09-02 10:05:01 +00:00
94ce535647
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
...
llvm-svn: 138997
2011-09-02 04:17:54 +00:00
5b49bb6bf5
Perform the upgrading of the old EH to the new EH in a more sane manner.
...
Perform the upgrading in steps.
* First, create a map of the invokes to the EH intrinsics.
* Next, take that mapping and determine if the invoke's unwind destination has a
single predecessor. If not, then create a new empty block to hold the new
landingpad instruction.
* Create a landingpad instruction into the uwnind destination. Fill it with the
values from the old selector. Map the old intrinsic calls to the new
landingpad values (there may be multiple landingpad instructions per instrinic
call pairs).
* Go through the old intrinsic calls, create a PHI node when necessary, and then
replace their values with the new values from the landingpad instructions.
* Delete all dead instructions.
* ???
* Profit!
llvm-svn: 138990
2011-09-02 01:30:08 +00:00
723cec7a5f
Update to new EH scheme.
...
llvm-svn: 138989
2011-09-02 01:25:11 +00:00
ed96b58bd2
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
...
llvm-svn: 138982
2011-09-01 23:35:51 +00:00
03aadae01f
Fix 80 columns violations.
...
llvm-svn: 138980
2011-09-01 23:23:50 +00:00
3767be9aee
Revert r131152, r129796, r129761. This code is currently considered
...
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.
llvm-svn: 138977
2011-09-01 23:07:08 +00:00
6397051ece
Don't drop alignment info on local common symbols.
...
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
llvm-svn: 138976
2011-09-01 23:04:27 +00:00
d7776ed030
Null-initialize to shut up -Wuninitialized warnings.
...
llvm-svn: 138974
2011-09-01 22:27:41 +00:00
5ada2a7e27
Fix apparent build error caused by r138948 on certain versions of GCC with -Werror. Sorry for the inconvenience.
...
llvm-svn: 138973
2011-09-01 22:01:14 +00:00
a3ba6d3b80
Reduce indentation. No functionality change.
...
llvm-svn: 138968
2011-09-01 21:29:49 +00:00
bf8280ff27
Change worklist driven deletion to be an iterative process.
...
Duncan noticed this!
llvm-svn: 138967
2011-09-01 21:28:33 +00:00
4028a51c74
Fix test; sorry for any inconvenience.
...
llvm-svn: 138966
2011-09-01 21:25:42 +00:00
71f5c2f158
Fix an issue with the IR sink pass found by inspection. (I'm not sure anyone is actually using this, but might as well fix it since I found the issue.)
...
llvm-svn: 138965
2011-09-01 21:21:24 +00:00
cc6e92892f
Add missing newline.
...
llvm-svn: 138964
2011-09-01 21:20:11 +00:00
2e2d75fb97
Fix the build for us -Werror users.
...
Remove broken emacs mode major notation marking a C++ file as C.
No functionality change.
llvm-svn: 138963
2011-09-01 21:09:04 +00:00
b053ac7e0c
Make isSafeToSpeculativelyExecute() return the right answer for some new instructions. Found by inspection; not sure what practical impact, if any, this has.
...
llvm-svn: 138962
2011-09-01 21:03:03 +00:00
c032617581
XFAIL this test on arm until the backend is fixed.
...
llvm-svn: 138955
2011-09-01 18:40:03 +00:00
0f6ff8cb2b
This test depends on cmov being available.
...
llvm-svn: 138954
2011-09-01 18:40:01 +00:00
5dc87d0f4d
Permit remat of partial register defs when it is safe.
...
An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:
%vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>
The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.
This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.
llvm-svn: 138953
2011-09-01 18:27:51 +00:00
f6d5d60f99
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
...
llvm-svn: 138952
2011-09-01 18:22:13 +00:00
f61d1c072e
Fix vbroadcast matching logic to early unmatch if the node doesn't have
...
only one use. Fix PR10825.
llvm-svn: 138951
2011-09-01 18:15:06 +00:00
db4ce60328
Fix up r137380 based on post-commit review by Jim Grosbach.
...
llvm-svn: 138948
2011-09-01 18:02:14 +00:00
35d240f9e8
t2Bcc is allowed to have a predicate without a preceding IT instruction.
...
llvm-svn: 138946
2011-09-01 17:47:45 +00:00
e417273fce
Revert r138794, "Do not try to rematerialize a value from a partial definition."
...
The problem is fixed for all register allocators by r138944, so this
patch is no longer necessary.
<rdar://problem/10032939>
llvm-svn: 138945
2011-09-01 17:25:18 +00:00
6357fa2f06
Prevent remat of partial register redefinitions.
...
An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.
This was fixed for the inline spiller in r138794. This patch fixes the
problem for all register allocators, and includes a small test case.
<rdar://problem/10032939>
llvm-svn: 138944
2011-09-01 17:18:50 +00:00
90da66bb69
Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. Sorry, I can't come up with a small test case. rdar://10043690
...
llvm-svn: 138934
2011-09-01 01:45:00 +00:00
185d377597
Update to new EH scheme.
...
llvm-svn: 138933
2011-09-01 01:28:25 +00:00
a617c32745
Resubmit with fix. Properly remove the instructions except for landingpad, which should be removed only when its invokes are.
...
llvm-svn: 138932
2011-09-01 01:28:11 +00:00
9f7cf20e60
Submitted this too early.
...
llvm-svn: 138931
2011-09-01 01:18:33 +00:00
2d1f11f743
Don't DCE the landingpad instruction.
...
The landingpad instruction can be removed only when its invokes are removed.
llvm-svn: 138930
2011-09-01 01:16:58 +00:00
d33e3007fa
Update to new EH scheme.
...
llvm-svn: 138928
2011-09-01 01:08:21 +00:00
3b17c1b48d
Update to new EH scheme.
...
llvm-svn: 138927
2011-09-01 01:02:41 +00:00
e88632d667
Update some tests to the new EH scheme.
...
llvm-svn: 138925
2011-09-01 00:58:03 +00:00
832a6a1909
PreRA scheduler should avoid cloning compares.
...
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261
llvm-svn: 138924
2011-09-01 00:54:31 +00:00
b9a899995d
Don't forget to add the landingpad and resume instructions to the InstructionList.
...
This was found via a nightly build of 483.xalancbmk.
llvm-svn: 138923
2011-09-01 00:50:20 +00:00
1d3c137839
Thumb2 assembly parsing and encoding for ADD(immediate).
...
llvm-svn: 138922
2011-09-01 00:28:52 +00:00
17847ae757
Fixup for functions that return a bool.
...
llvm-svn: 138918
2011-08-31 23:49:05 +00:00
080f40a49d
Reenable test.
...
llvm-svn: 138916
2011-08-31 23:08:05 +00:00
54b91028f0
Revert accidental commit
...
llvm-svn: 138915
2011-08-31 23:07:46 +00:00
c472975fd9
Disable this test until Bill fixes it properly.
...
llvm-svn: 138914
2011-08-31 23:03:30 +00:00
e1995f2566
Static relocation model Thumb jump table interworking.
...
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.
llvm-svn: 138912
2011-08-31 22:23:09 +00:00
4af0aa98d5
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
...
llvm-svn: 138910
2011-08-31 22:00:41 +00:00
5624fe0cff
Update to new EH scheme.
...
llvm-svn: 138908
2011-08-31 21:50:07 +00:00
e336599f6d
Update to new EH scheme.
...
llvm-svn: 138906
2011-08-31 21:44:24 +00:00
55fb73a6e0
Remove old declare statements.
...
llvm-svn: 138905
2011-08-31 21:41:20 +00:00
22055c713f
Update more tests to the new EH scheme.
...
llvm-svn: 138904
2011-08-31 21:40:15 +00:00
Bruno Cardoso Lopes