ddc0f8779e
Command line option to enable support for segmented stacks:
...
-segmented-stacks.
Patch by Sanjoy Das!
llvm-svn: 138811
2011-08-30 19:29:02 +00:00
e6fba77971
Follow up to r138791.
...
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
llvm-svn: 138810
2011-08-30 19:09:48 +00:00
d708ec4c6a
When walking backwards to eliminate final stores to allocas at the end of a function, encountering an unrelated store should not cause us to give up like encountering a load does.
...
llvm-svn: 138809
2011-08-30 18:51:55 +00:00
267a6d92fa
Teach macho-dump how to dump linkedit_data load commands.
...
llvm-svn: 138807
2011-08-30 18:33:37 +00:00
71038e7021
Set CR1EQ only when lowering vararg floating arguments (not any vararg
...
arguments as before), unset CR1EQ otherwise.
llvm-svn: 138802
2011-08-30 17:04:16 +00:00
87cec4d172
Fix typos in SPUMCTargetDesc.h
...
Patch supplied by Liu (projlc@gmail.com )
llvm-svn: 138799
2011-08-30 07:27:02 +00:00
02ad655446
Fix typo in BlackfinFrameLowering.h
...
Patch supplied by Liu (projlc@gmail.com )
llvm-svn: 138798
2011-08-30 07:26:11 +00:00
9668f2d775
Fix typo in MSP430MCTargetDesc.h.
...
Patch supplied by Liu (projlc@gmail.com )
llvm-svn: 138797
2011-08-30 07:24:47 +00:00
8c54533f99
Fix typo in MipsMCTargetDesc.h; Patch supplied by Liu (proljc@gmail.com)
...
llvm-svn: 138796
2011-08-30 07:23:29 +00:00
358a5f6a72
Do not try to rematerialize a value from a partial definition.
...
I don't currently have a good testcase for this; will try to get one
tomorrow. <rdar://problem/10032939>
llvm-svn: 138794
2011-08-30 05:36:02 +00:00
e891654a58
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
...
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.
When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube
If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.
subc
|
libcall #2
|
libcall #1
|
sube
However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.
The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.
rdar://10019576
llvm-svn: 138791
2011-08-30 01:34:54 +00:00
6e59d5c916
Revert 138781. It's not playing nicely with the immediate forms for ADC.
...
llvm-svn: 138782
2011-08-29 23:24:15 +00:00
19a75f075d
Thumb2 assembler aliases for ADC/SBC w/o the .w suffix.
...
llvm-svn: 138781
2011-08-29 23:20:54 +00:00
3e0aa03fe9
Add missing encoding information for some of the GPR<->FP register moves.
...
llvm-svn: 138780
2011-08-29 23:15:25 +00:00
ed16ec4248
Thumb2 parsing and encoding for IT blocks.
...
llvm-svn: 138773
2011-08-29 22:24:09 +00:00
850b9a9a84
Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802.
...
llvm-svn: 138768
2011-08-29 21:15:46 +00:00
243274c789
Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite.
...
llvm-svn: 138766
2011-08-29 21:14:19 +00:00
7113f221e2
Fix grammar, noticed by Duncan.
...
llvm-svn: 138764
2011-08-29 21:03:12 +00:00
32ac76616e
Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding.
...
llvm-svn: 138760
2011-08-29 20:42:00 +00:00
4d5c8f894d
addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures.
...
llvm-svn: 138758
2011-08-29 20:16:50 +00:00
5fc81ffbac
Fixes following the CR by Chris and Duncan:
...
Optimize chained bitcasts of the form A->B->A.
Undo r138722 and change isEliminableCastPair to allow this case.
llvm-svn: 138756
2011-08-29 19:58:36 +00:00
967674d26c
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
...
llvm-svn: 138754
2011-08-29 19:36:44 +00:00
ebab735788
Initialize CompactUnwindSection so that other targets won't use an uninitialized value.
...
llvm-svn: 138752
2011-08-29 18:25:59 +00:00
7dfa791f4f
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
...
llvm-svn: 138751
2011-08-29 18:23:02 +00:00
4dd515c04f
Dump with dbgs() instead of printf.
...
llvm-svn: 138749
2011-08-29 18:14:17 +00:00
6bb5b3cfcd
Make GCC happy by adding parens.
...
llvm-svn: 138748
2011-08-29 18:14:15 +00:00
6314343333
Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653.
...
llvm-svn: 138746
2011-08-29 17:59:41 +00:00
50e0170fa5
Move non-intruction patterns to a more appropriate place!
...
llvm-svn: 138744
2011-08-29 17:51:24 +00:00
f02d98d7c0
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
...
llvm-svn: 138739
2011-08-29 17:17:09 +00:00
0896621a50
Reapply r138695. Fix PassManager stack depths.
...
Patch by Xiaoyi Guo!
llvm-svn: 138737
2011-08-29 17:07:00 +00:00
516dbb24b5
Add AMDIL as valid target triple to LLVM.
...
Submitted by: Villmow, Micah <Micah.Villmow@amd.com>
llvm-svn: 138734
2011-08-29 15:44:55 +00:00
7ea09c9462
Remove premature previous commit.
...
llvm-svn: 138725
2011-08-28 14:52:51 +00:00
4d63542b82
Fix PR5329: pay attention to constructor/destructor priority
...
when outputting them. With this, the entire LLVM testsuite
passes when built with dragonegg.
llvm-svn: 138724
2011-08-28 13:17:22 +00:00
f786bae6ac
Encoding of instructions referencing segments has changed. Do what X86MCCodeEmitter does.
...
llvm-svn: 138723
2011-08-28 13:07:57 +00:00
52600ee8c3
Bitcasts are transitive. Bitcast-Bitcast-X becomes Bitcast-X.
...
llvm-svn: 138722
2011-08-28 11:51:08 +00:00
7bfd86d046
Fix integer overflow bug in raw_ostream::write. This showed up as a
...
non-deterministic crash in the test suite. Fixes PR10055!
llvm-svn: 138717
2011-08-28 03:30:02 +00:00
61a1ff543c
Silence GCC warnings and make an array const.
...
llvm-svn: 138706
2011-08-27 17:36:14 +00:00
5ff961c376
Report failure if there are less bytes than requested in a MemoryObject.
...
Before we just left the remaining bytes uninitialized. This is another step in making llvm valgrind-clean again.
llvm-svn: 138705
2011-08-27 07:45:46 +00:00
ba198e661e
Auto upgrade the old EH scheme to use the new one. This is on a trial basis. If
...
things to disasterously over night, this can be reverted.
llvm-svn: 138702
2011-08-27 06:11:03 +00:00
5c29ebae8e
Reverting r138695 to see if it fixes clang self host.
...
llvm-svn: 138701
2011-08-27 06:10:16 +00:00
032c60c1a0
Only delete instructions once.
...
llvm-svn: 138700
2011-08-27 06:10:02 +00:00
4707d37ac9
These splits should be done whether they are critical edges or not.
...
llvm-svn: 138697
2011-08-27 04:40:37 +00:00
b0cd1e65de
Fix PassManager stack depths.
...
Patch by Xiaoyi Guo!
llvm-svn: 138695
2011-08-27 02:11:03 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
...
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
6c70e58041
Correct encoding of BL with immediate offset.
...
llvm-svn: 138673
2011-08-26 22:54:51 +00:00
b9d4e37776
ARM assembly parsing tweak for pldw.
...
llvm-svn: 138669
2011-08-26 22:21:51 +00:00
240d20af79
Spelling fail.
...
llvm-svn: 138667
2011-08-26 21:47:57 +00:00
3d1eac85c3
Thumb2 assembler parsing and encoding of IT instruction.
...
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.
llvm-svn: 138665
2011-08-26 21:43:41 +00:00
71fce2c84d
Update the dominator tree with the correct dominator for the new 'unwind' block.
...
llvm-svn: 138664
2011-08-26 21:36:12 +00:00
5e5704277f
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
...
llvm-svn: 138660
2011-08-26 21:21:21 +00:00
fee8eda35b
Split the landing pad block only if it's a critical edge. Also intelligently
...
split it in the other place where we're splitting critical edges.
llvm-svn: 138658
2011-08-26 21:18:55 +00:00
fd60f60ed1
Fix ARM codegen breakage caused by r138653.
...
llvm-svn: 138657
2011-08-26 21:12:37 +00:00
3cc90fe5a5
Whitespace and 80-col.
...
llvm-svn: 138654
2011-08-26 21:02:40 +00:00
16d33f36d5
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
...
llvm-svn: 138653
2011-08-26 20:43:14 +00:00
eed1e8905a
Don't sink landingpad instructions during ind-var simplification.
...
llvm-svn: 138651
2011-08-26 20:40:15 +00:00
5658b49f64
Update for feedback from Jim.
...
llvm-svn: 138642
2011-08-26 19:39:26 +00:00
aa38dbadca
ARMDisassembler: Always return a size, even when disassembling fails.
...
This should fix PR10772.
llvm-svn: 138636
2011-08-26 18:21:36 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
...
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
db6f646ec3
Don't insert branch hint lables that are never used.
...
llvm-svn: 138630
2011-08-26 10:14:56 +00:00
149695627a
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
...
This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
llvm-svn: 138625
2011-08-26 06:19:51 +00:00
c66d50d1a2
Fix disassembling of VCVTSD2SI
...
llvm-svn: 138623
2011-08-26 04:49:29 +00:00
147d9cde78
LoopInfo::updateUnloop fix, and verify Block->Loop maps.
...
Fixes an oversight, and adds verification to catch it in the unloop.ll tests.
llvm-svn: 138622
2011-08-26 03:06:34 +00:00
452aae6202
Atomic load/store on ARM/Thumb.
...
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
llvm-svn: 138621
2011-08-26 02:59:24 +00:00
0655b78ccc
Address review comments.
...
- Reword comments.
- Allow undefined behavior interfering with undefined behavior.
- Add address space checks.
llvm-svn: 138619
2011-08-26 02:25:55 +00:00
fb212a6309
SimplifyCFG: If we have a PHI node that can evaluate to NULL and do a load or store to the address returned by the PHI node then we can consider this incoming value as dead and remove the edge pointing there, unless there are instructions that can affect control flow executed in between.
...
In theory this could be extended to other instructions, eg. division by zero, but it's likely that it will "miscompile" some code because people depend on div by zero not trapping. NULL pointer dereference usually leads to a crash so we should be on the safe side.
This shrinks the size of a Release clang by 16k on x86_64.
llvm-svn: 138618
2011-08-26 01:22:29 +00:00
8ac2041a19
Look at only the terminators of the basic block. Also, if we're using the new EH
...
scheme, return 'true' so that it doesn't try to run the old EH scheme's fixup on
the new code.
llvm-svn: 138605
2011-08-25 23:48:11 +00:00
45449b1cba
Initial check in that will auto-upgrade the old EH scheme to the new EH scheme.
...
This upgrade suffers from the problems of the old EH scheme - i.e., that the
calls to llvm.eh.exception() and llvm.eh.selector() can wander off and get
lost. It makes a valiant effort to reclaim these little lost lambs.
This is a first draft, so it hasn't yet been hooked up to the parser.
llvm-svn: 138602
2011-08-25 23:22:40 +00:00
ed834810be
Do the same as r138461. Mark VZEROALL as clobbering all YMM registers
...
llvm-svn: 138592
2011-08-25 22:23:58 +00:00
64bfca1b60
Remove stray fullstop.
...
llvm-svn: 138589
2011-08-25 21:46:20 +00:00
8347b86293
Add support for AVX 256-bit version of MOVDDUP!
...
llvm-svn: 138588
2011-08-25 21:40:37 +00:00
388eacee2c
Make isMOVDDUP mask check more strict and update comments!
...
llvm-svn: 138587
2011-08-25 21:40:34 +00:00
5e30972cff
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
...
llvm-svn: 138575
2011-08-25 18:30:18 +00:00
5a122f37fe
Intel family 6 model 44 is Gulftown/Westmere-EP and doesn't have AVX.
...
llvm-svn: 138573
2011-08-25 18:05:56 +00:00
6446bf780a
ARM fix for missing implicit operands on ldmia_ret.
...
rdar://10005094: miscompile of 176.gcc
llvm-svn: 138568
2011-08-25 17:50:53 +00:00
f7ecc16c96
whitespace
...
llvm-svn: 138566
2011-08-25 17:40:54 +00:00
1c171b121a
Explicitly disallow predication in Thumb1 assembly.
...
llvm-svn: 138562
2011-08-25 17:23:55 +00:00
14380ff9a0
Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678.
...
llvm-svn: 138553
2011-08-25 08:11:01 +00:00
e1541838f9
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
...
llvm-svn: 138551
2011-08-25 06:57:46 +00:00
3fb137f7ef
LSR wants to split the landing pad's critical edge. Let it do it, but use the
...
proper function to do it.
llvm-svn: 138550
2011-08-25 05:55:40 +00:00
88e6d5945f
Initialize member variable.
...
llvm-svn: 138548
2011-08-25 04:04:18 +00:00
296256fb32
Add support for 256-bit versions of VSHUFPD and VSHUFPS.
...
llvm-svn: 138546
2011-08-25 02:58:26 +00:00
54366cc332
Add memory version of SHUFPD to mask decoding!
...
llvm-svn: 138545
2011-08-25 02:58:21 +00:00
9dad430486
Hide -global-merge option.
...
llvm-svn: 138540
2011-08-25 01:22:49 +00:00
07efd6f1e0
When inserting new instructions, use getFirstInsertionPt instead of
...
getFirstNonPHI so that it will skip over the landingpad instructions as well.
llvm-svn: 138537
2011-08-25 01:08:34 +00:00
f066b2fe99
Add a command line option to disable global merge pass.
...
llvm-svn: 138536
2011-08-25 01:00:36 +00:00
3ca20e64ac
Remove a out-of-place comment.
...
llvm-svn: 138534
2011-08-25 00:54:42 +00:00
50d74211df
Create a section for non-instructions patterns in the beginning of the
...
file, and move more code around!
llvm-svn: 138521
2011-08-24 23:18:11 +00:00
2fb51d38e6
Move code around!
...
llvm-svn: 138520
2011-08-24 23:18:09 +00:00
fb702fe8d6
Organize UNPCK* patterns, also add remaining for AVX.
...
llvm-svn: 138519
2011-08-24 23:18:06 +00:00
9ade17b7f2
Move remaining MOVDDUP patterns close to MOVDDUP defintion and duplicate
...
the missing ones for AVX.
llvm-svn: 138518
2011-08-24 23:18:04 +00:00
c1e1e7ab97
Organize and tidy up MOVDDUP section. Also update comments!
...
llvm-svn: 138517
2011-08-24 23:18:02 +00:00
813891a215
Move MOVHLPS patterns close to MOVHLPS definition, and duplicate the
...
pattern for 128-bit AVX mode.
llvm-svn: 138516
2011-08-24 23:17:59 +00:00
9566a66a7c
Move all PSHUF* patterns close to the PSHUF* definitions. Also be
...
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!
llvm-svn: 138515
2011-08-24 23:17:57 +00:00
2953d7b320
Move all SHUFP* patterns close to the SHUFP* definitions. Also be
...
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!
llvm-svn: 138514
2011-08-24 23:17:55 +00:00
37612a3de3
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
...
llvm-svn: 138507
2011-08-24 22:40:22 +00:00
9c73a57b20
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually.
...
llvm-svn: 138505
2011-08-24 22:33:28 +00:00
eee864520c
Some autoconf tests use module level inline asm to test compiler's handling of
...
.cfi_startproc. e.g. libffi:
$ cat confopt.c
asm (".cfi_startproc\n\t.cfi_endproc");
int main () { return 0; }
Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.
rdar://10017184
llvm-svn: 138504
2011-08-24 22:31:37 +00:00
21a60b6f90
ARM asm backend initialize isThumbMode based on target triple.
...
llvm-svn: 138501
2011-08-24 22:27:35 +00:00
838ed3af46
Thumb .n mnemonic qualifiers can be ignored for now.
...
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
llvm-svn: 138500
2011-08-24 22:19:48 +00:00
4b701af908
Thumb parsing and encoding for SUB (SP minu immediate).
...
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
llvm-svn: 138494
2011-08-24 21:42:27 +00:00
216cfaa808
Be careful not to walk off the end of the operand info list while updating VFP predicates.
...
llvm-svn: 138492
2011-08-24 21:35:46 +00:00
0a0b3071df
Thumb parsing and encoding support for ADD SP instructions.
...
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
llvm-svn: 138488
2011-08-24 21:22:15 +00:00
38cd821dc4
Fix whitespace.
...
llvm-svn: 138487
2011-08-24 21:17:30 +00:00
86c5cbe613
Skip the landingpad instruction when determining the insertion point.
...
llvm-svn: 138481
2011-08-24 21:06:46 +00:00
342e8df0e0
Basic x86 code generation for atomic load and store instructions.
...
llvm-svn: 138478
2011-08-24 20:50:09 +00:00
0902a68f69
Use getFirstInsertionPt instead of getFirstNonPHI so that it skips to the proper
...
insertion place.
llvm-svn: 138473
2011-08-24 20:28:43 +00:00
365af6f17b
Implement Constant::isAllOnesValue(). Fix ConstantFolding to use the new api.
...
llvm-svn: 138469
2011-08-24 20:18:38 +00:00
af2f827a2c
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
...
rdar://10015134
llvm-svn: 138467
2011-08-24 20:06:14 +00:00
ce02840633
Mark VZEROALL as clobbering all YMM registers
...
llvm-svn: 138461
2011-08-24 18:48:33 +00:00
6ccd79f4d5
Add missing explicit writeback operand to tSTMIA_UPD.
...
rdar://10014745
llvm-svn: 138457
2011-08-24 18:19:42 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
...
These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
d3e65e702f
Fix a crashing bug in SplitBlock when it is called on a block with no
...
dominator information even though dominators were previously computed.
Patch by Nick Sumner.
llvm-svn: 138449
2011-08-24 18:07:01 +00:00
a281f2d07d
Thumb add SP assembly syntax fix.
...
llvm-svn: 138448
2011-08-24 18:04:27 +00:00
1b8457a84c
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
...
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
llvm-svn: 138445
2011-08-24 17:46:13 +00:00
523004145e
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
...
llvm-svn: 138443
2011-08-24 17:21:43 +00:00
dee9e8a37c
Tidy up. Trailing whitespace.
...
llvm-svn: 138437
2011-08-24 16:44:17 +00:00
6e3c83eb1c
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
...
variable sized alloca.
llvm-svn: 138433
2011-08-24 13:32:43 +00:00
de92622aa5
Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.
...
llvm-svn: 138427
2011-08-24 06:14:18 +00:00
f4ee0c0db2
Add the sentinal "no handle" value to the ResumeInst.
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A value of -1 at a call site tells the personality function that this call isn't
handled by the current function. Since the ResumeInsts are converted to calls to
_Unwind_SjLj_Resume, add a (volatile) store of -1 to its 'call site'.
llvm-svn: 138416
2011-08-24 00:00:23 +00:00
2d4f0bea57
Don't replace *all* uses with the new stuff.
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This is not necessarily the first or dominating use of the EH values. The IR
breaks if it's not. So replace the specific value in the instruction with the
new value.
llvm-svn: 138406
2011-08-23 22:55:03 +00:00
01a325a40e
Look at the end of the entry block for an invoke.
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The invoke could be at the end of the entry block. If it's the only one, then we
won't process all of the landingpad instructions correctly. This code is
currently ugly, but should be made much nicer once the new EH switch is thrown.
llvm-svn: 138397
2011-08-23 22:20:16 +00:00
9e9f2ce32d
Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit
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permutations. Also tidy up some patterns and make them close to their
instruction definition!
llvm-svn: 138392
2011-08-23 22:06:37 +00:00
4eb0433672
A landingpad instruction is neither folded nor dead.
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llvm-svn: 138387
2011-08-23 21:33:05 +00:00
51b554247d
Move ARM frame-unwinding EHABI handling a touch earlier.
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It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
llvm-svn: 138386
2011-08-23 21:32:34 +00:00
50b0f6669c
[SU]XT[BH] are only available on ARMv6 and up.
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llvm-svn: 138373
2011-08-23 20:53:08 +00:00
43c322b5b2
Add some useful accessors to c++ api that appear to be missing from the c api
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llvm-svn: 138371
2011-08-23 20:27:46 +00:00
4d6c9d711d
Some refactoring so TargetRegistry.h no longer has to include any files
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from MC.
llvm-svn: 138367
2011-08-23 20:15:21 +00:00
7bc78f692c
Revert "Address Duncan's CR request:"
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This reverts commit 20a05be15ea5271ab6185b83200fa88263362400. (svn rev 138340)
Conflicts:
test/Transforms/InstCombine/bitcast.ll
llvm-svn: 138366
2011-08-23 20:11:10 +00:00
5cc338da67
Thumb parsing and encoding for SVC.
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llvm-svn: 138360
2011-08-23 19:49:10 +00:00
6b477b985b
Fix 80 col violations.
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llvm-svn: 138356
2011-08-23 19:17:21 +00:00
4c8ff77f1b
PerformSubCombine to work on integers larger than i128. Fixes a crasher.
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llvm-svn: 138354
2011-08-23 19:01:24 +00:00
505be75900
Thumb parsing and encoding for tSTRspi.
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llvm-svn: 138348
2011-08-23 18:39:41 +00:00
d80d169a04
Thumb parsing and encoding for STM.
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llvm-svn: 138345
2011-08-23 18:15:37 +00:00
169b2be611
Factor low reg checking into a helper function.
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llvm-svn: 138344
2011-08-23 18:13:04 +00:00
924bcfc92f
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
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llvm-svn: 138341
2011-08-23 17:51:38 +00:00
c78e6607b5
Address Duncan's CR request:
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1. Cleanup the tests in ConstantFolding.cpp
2. Implement isAllOnes for Constant, ConstantFP, ConstantVector
llvm-svn: 138340
2011-08-23 17:48:43 +00:00
9b7bd15d0b
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
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llvm-svn: 138339
2011-08-23 17:45:18 +00:00
e364ad540a
Clean up Thumb load/store multiple definitions.
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There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
llvm-svn: 138338
2011-08-23 17:41:15 +00:00
041dba6dec
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
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llvm-svn: 138337
2011-08-23 17:37:32 +00:00
771ef8c66a
This patch adds support of le32 pseudo-cpu that stands for generic
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32-bit little-endian CPU. Used by PNaCl and Emscripten.
llvm-svn: 138335
2011-08-23 16:59:00 +00:00
6612e35b0d
Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712.
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llvm-svn: 138321
2011-08-23 04:36:33 +00:00
fd6cb64c48
lib/Support/Windows/Windows.h: Update required IE ver. 0x0600 should be enough for Windows XP.
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llvm-svn: 138319
2011-08-23 03:49:11 +00:00
2a3ffb5d97
Introduce a pass to insert vzeroupper instructions to avoid AVX to
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SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.
llvm-svn: 138317
2011-08-23 01:14:17 +00:00
3636be3c8f
Thumb parsing and encoding for SBC.
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llvm-svn: 138311
2011-08-22 23:55:58 +00:00
c3c32d9e09
Thumb parsing and encoding for RSB.
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llvm-svn: 138308
2011-08-22 23:47:13 +00:00
eb1367b2b8
Reject invalid imod values in t2CPS instructions.
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llvm-svn: 138306
2011-08-22 23:44:04 +00:00
f0d2dfde4f
Split the landing pad's edge. Then for all uses of a landingpad instruction's
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value, we insert a load of the exception object and selector object from memory,
which is where it actually resides. If it's used by a PHI node, we follow that
to where it is being used. Eventually, all landingpad instructions should have
no uses. Any PHI nodes that were associated with those landingpads should be
removed.
llvm-svn: 138302
2011-08-22 23:38:40 +00:00
1346d79b4b
t2SMLAD is a four-register instruction, not a three-register one.
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llvm-svn: 138301
2011-08-22 23:31:45 +00:00
f94b7b7d57
Correct operand naming of t2USAT16 to allow proper decoding.
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llvm-svn: 138300
2011-08-22 23:27:47 +00:00
bfeb4f78af
Revert r138278 now that r138289 has fixed the root issue.
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llvm-svn: 138299
2011-08-22 23:25:48 +00:00
5e9989a920
Match operand naming to allow correct decoding of t2LDRSH_POST.
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llvm-svn: 138298
2011-08-22 23:22:05 +00:00
38c59fcb08
Improve error checking for tPUSH and tPOP register lists.
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llvm-svn: 138295
2011-08-22 23:17:34 +00:00
2844a81079
Match operand names to provide correct decoding for Thumb2 SMULL.
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llvm-svn: 138294
2011-08-22 23:16:48 +00:00
a743409ec8
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
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llvm-svn: 138292
2011-08-22 23:10:16 +00:00
b296790bb6
Add NativeClient support to Triple::ParseOS.
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llvm-svn: 138291
2011-08-22 23:08:53 +00:00
6aa2744bed
Follow up to Jim's r138278. This fixes commuteInstruction so it handles two-address instructions correctly. I'll let Jim add a test case. :-)
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llvm-svn: 138289
2011-08-22 23:04:56 +00:00
139acd21e6
Thumb assemmbly parsing diagnostic improvements for LDM.
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llvm-svn: 138287
2011-08-22 23:01:07 +00:00
9dc808e74d
X86: Add some operand types required to identify calls.
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llvm-svn: 138285
2011-08-22 22:55:32 +00:00
ca2ffad8b1
Temporarilly mark tMUL as not commutable.
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It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.
llvm-svn: 138278
2011-08-22 22:00:18 +00:00
061738a680
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
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llvm-svn: 138273
2011-08-22 21:34:00 +00:00
74f090d44c
Add support for breaking 256-bit int VETCC into two 128-bit ones,
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avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.
llvm-svn: 138271
2011-08-22 20:31:04 +00:00
6e62ca940a
Add 128-bit AVX codegen for PCMP* family of integer instructions
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llvm-svn: 138270
2011-08-22 20:31:00 +00:00
df698b032c
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
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llvm-svn: 138269
2011-08-22 20:27:12 +00:00
5765f4c24c
Make DynamicLibrary thread-safe w/r/t call to dlerror() after dlopen(). PR10718
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llvm-svn: 138260
2011-08-22 19:01:52 +00:00
5c932b24be
Tighten up ARM reglist validation a bit.
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llvm-svn: 138258
2011-08-22 18:50:36 +00:00
3aaed0a14c
Some whitespace fixes and #include reordering.
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llvm-svn: 138256
2011-08-22 18:44:49 +00:00
721c3704da
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
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llvm-svn: 138255
2011-08-22 18:42:13 +00:00
97f73cb449
Be less redundant.
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llvm-svn: 138252
2011-08-22 18:26:12 +00:00
ac92e77bb8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
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llvm-svn: 138251
2011-08-22 18:22:06 +00:00
6caa557ae6
Clean up predicates on ARM target instruction aliases.
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llvm-svn: 138249
2011-08-22 18:04:24 +00:00
b49813206b
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
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llvm-svn: 138246
2011-08-22 17:56:58 +00:00
4b8e8ce37f
Add a comment.
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llvm-svn: 138243
2011-08-22 17:29:37 +00:00
56e1cef705
Constant pointers to objects don't need reference counting.
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llvm-svn: 138242
2011-08-22 17:29:11 +00:00
58994ec9b9
PathV2: Handle more reserved filenames on windows.
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Patch by Aaron Ballman!
llvm-svn: 138213
2011-08-20 21:36:38 +00:00
bd16424f91
Fix AsmParser binary precedence for shift operators.
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rdar://9976729
llvm-svn: 138208
2011-08-20 16:24:13 +00:00
ad4a70ad3e
Add constant folding support for bitcasts of splat vectors to integers.
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llvm-svn: 138206
2011-08-20 14:02:29 +00:00
1eae12cc9f
lib/Support/CrashRecoveryContext.cpp: Add Win32 support to CrashRecoveryContext. Thanks to Aaron Ballman!
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llvm-svn: 138199
2011-08-20 06:35:36 +00:00
613655f89c
lib/Support/Windows/Windows.h: Require at least Windows XP(5.1) API. We will not support Windows 2000 any more.
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llvm-svn: 138198
2011-08-20 06:35:31 +00:00
5800a8c3ad
Cast through intptr_t, ISO C++ requires it.
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llvm-svn: 138186
2011-08-20 02:22:42 +00:00
61f92efb5c
Remove the VMOVQQ pseudo instruction.
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llvm-svn: 138177
2011-08-20 00:52:40 +00:00
baf5538da9
Remove VMOVQQQQ pseudo instruction.
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llvm-svn: 138174
2011-08-20 00:40:14 +00:00
59015c8b17
Add <imp-def> operands to QQ and QQQQ stack loads.
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This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.
llvm-svn: 138164
2011-08-20 00:17:45 +00:00
be7625161e
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
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Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
llvm-svn: 138163
2011-08-20 00:17:25 +00:00
38d813087e
If we're splitting the landing pad block and assigning it only one predecessor,
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then don't split it a second time, since that block will be dead.
llvm-svn: 138153
2011-08-19 23:46:30 +00:00
59e27c5f12
Do not use named md nodes to track variables that are completely optimized. This does not scale while doing LTO with debug info. New approach is to include list of variables in the subprogram info directly.
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llvm-svn: 138145
2011-08-19 23:28:12 +00:00
2597722e07
Thumb parsing and encoding support for NOP.
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The irony is not lost that this is not a completely trivial patchset.
llvm-svn: 138143
2011-08-19 23:24:36 +00:00
419fd4f315
Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not
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needed for Mips32.
llvm-svn: 138132
2011-08-19 22:59:00 +00:00
37aa348195
Thumb assembly parsing and encoding for NEG.
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llvm-svn: 138131
2011-08-19 22:51:03 +00:00
68ed46ce9a
Roll back the rest of r126557. It's a hack that will break in some obscure cases.
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llvm-svn: 138130
2011-08-19 22:39:31 +00:00
8022015a16
Fix NEG alias
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llvm-svn: 138125
2011-08-19 22:30:58 +00:00
459422d750
Be more lenient on tied operand matching for MUL.
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llvm-svn: 138124
2011-08-19 22:30:46 +00:00
d126347f32
Re-write part of VEX encoding logic, to be more easy to read! Also fix
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a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
066e9ec1e4
Update tests.
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llvm-svn: 138116
2011-08-19 22:19:48 +00:00
8e048495c8
Thumb assembly parsing and encoding for MUL.
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llvm-svn: 138108
2011-08-19 22:07:46 +00:00
26e19288be
The landingpad instruction isn't dead simply because it's value isn't used.
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llvm-svn: 138102
2011-08-19 21:52:06 +00:00
c1348074ec
Eli points out that this is what report_fatal_error() is for.
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llvm-svn: 138091
2011-08-19 21:45:19 +00:00
f86cd37bef
Thumb assembly parsing and encoding for MOV.
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llvm-svn: 138076
2011-08-19 20:46:54 +00:00
dbb60f960a
Tidy up. Tab character.
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llvm-svn: 138072
2011-08-19 20:30:19 +00:00
3f73184d90
This is not actually unreachable, so don't use llvm_unreachable for it. Since
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the intent seems to be to terminate even in Release builds, just use abort()
directly.
If program flow ever reaches a __builtin_unreachable (which llvm_unreachable is
#define'd to on newer GCCs) then the program is undefined.
llvm-svn: 138068
2011-08-19 20:14:27 +00:00
9c92049069
Tab characters.
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llvm-svn: 138066
2011-08-19 19:41:46 +00:00
Rafael Espindola