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359 Commits

Author SHA1 Message Date
Akira Hatanaka 9586618c58 Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp. 
llvm-svn: 158413
 2012-06-13 19:06:08 +00:00
Akira Hatanaka f0273603f5 Implement fastcc calling convention for MIPS. 
llvm-svn: 158410
 2012-06-13 18:06:00 +00:00
Akira Hatanaka 6734685f21 Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is 
inserted after the shift-left-logical node.

llvm-svn: 157937
 2012-06-04 17:46:29 +00:00
Hans Wennborg 245917b536 MIPS TLS: use the model selected by TargetMachine::getTLSModel(). 
This was mostly done already in r156162, but I missed one place.

llvm-svn: 157929
 2012-06-04 14:02:08 +00:00
Chris Lattner 58268c23ac remove an unused variable. 
llvm-svn: 157872
 2012-06-02 01:03:42 +00:00
Akira Hatanaka 019e592f75 Set operation actions for load/store nodes in the Mips backend. 
llvm-svn: 157866
 2012-06-02 00:04:42 +00:00
Akira Hatanaka 8f1db778a4 Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which 
custom-lower unaligned load and store nodes.

llvm-svn: 157864
 2012-06-02 00:03:49 +00:00
Akira Hatanaka b9ebf8d644 Define Mips specific unaligned load/store nodes. 
llvm-svn: 157863
 2012-06-02 00:03:12 +00:00
Akira Hatanaka 4e76bf8282 Expand unaligned i16 loads/stores for the Mips backend. 
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.

llvm-svn: 157862
 2012-06-02 00:02:45 +00:00
Akira Hatanaka bff8e31d3c Cleanup and factoring of mips16 tablegen classes. Make register classes 
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.

llvm-svn: 157730
 2012-05-31 02:59:44 +00:00
Justin Holewinski aa58397b3c Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall 
to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

llvm-svn: 157479
 2012-05-25 16:35:28 +00:00
Akira Hatanaka f542ebd958 Make the following changes in MipsISelLowering.cpp: 
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.

llvm-svn: 156692
 2012-05-12 03:19:04 +00:00
Akira Hatanaka 0a8ab718cb Expand 64-bit shifts if target ABI is O32. 
llvm-svn: 156457
 2012-05-09 00:55:21 +00:00
Eric Christopher 0d8c15d20f Add support for the 'x' constraint. 
Patch by Jack Carter.

llvm-svn: 156295
 2012-05-07 06:25:19 +00:00
Eric Christopher 9c492e6ebf Add support for the 'l' constraint. 
Patch by Jack Carter.

llvm-svn: 156294
 2012-05-07 06:25:15 +00:00
Eric Christopher e3c494de82 Add support for the 'c' constraint. 
Patch by Jack Carter.

llvm-svn: 156293
 2012-05-07 06:25:10 +00:00
Eric Christopher c18ae4a3b1 Add support for the 'P' constraint. 
Patch by Jack Carter.

llvm-svn: 156292
 2012-05-07 06:25:02 +00:00
Eric Christopher 470578a91b Add support for the 'O' constraint. 
Patch by Jack Carter.

llvm-svn: 156285
 2012-05-07 05:46:48 +00:00
Eric Christopher e07aa430b8 Add support for the 'N' inline asm constraint. 
Patch by Jack Carter.

llvm-svn: 156284
 2012-05-07 05:46:43 +00:00
Eric Christopher 1109b3406d Add support for the 'L' inline asm constraint. 
Patch by Jack Carter.

llvm-svn: 156283
 2012-05-07 05:46:37 +00:00
Eric Christopher 3ff88a05b7 Add support for the inline asm constraint 'K'. 
llvm-svn: 156282
 2012-05-07 05:46:29 +00:00
Eric Christopher 7201e1b4b9 Support the 'J' constraint. 
Patch by Jack Carter.

llvm-svn: 156280
 2012-05-07 03:13:42 +00:00
Eric Christopher 1d6c89eea1 Add support for the 'I' inline asm constraint. Also add tests 
from the previous 2 patches.

Patch by Jack Carter.

llvm-svn: 156279
 2012-05-07 03:13:32 +00:00
Eric Christopher 58daf04681 Allow 64 bit integer values in gpu registers if arch and abi are 64 bit. 
Patch by Jack Carter.

llvm-svn: 156278
 2012-05-07 03:13:22 +00:00
Eric Christopher cfcd77b0bc When using inline asm constraints representing 
non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

llvm-svn: 156277
 2012-05-07 03:13:16 +00:00
Hans Wennborg aea412008e Make ARM and Mips use TargetMachine::getTLSModel() 
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).

llvm-svn: 156162
 2012-05-04 09:40:39 +00:00
NAKAMURA Takumi e30303fa86 llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC. 
Thanks to Andy Gibbs, to report the issue.

llvm-svn: 155287
 2012-04-21 15:31:45 +00:00
Craig Topper c7242e054d Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. 
llvm-svn: 155188
 2012-04-20 07:30:17 +00:00
Akira Hatanaka 47ad674f67 Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user, 
otherwise expand FNEG during legalization.

llvm-svn: 154546
 2012-04-11 22:59:08 +00:00
Akira Hatanaka 7f4c9d1429 Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user. 
Invalid operation is signaled if the operand of these instructions is NaN.

llvm-svn: 154545
 2012-04-11 22:49:04 +00:00
Akira Hatanaka 4f5c8421b3 Fix bugs in lowering of FCOPYSIGN nodes. 
- FCOPYSIGN nodes that have operands of different types were not handled.
- Different code was generated depending on the endianness of the target.

Additionally, code is added that emits INS and EXT instructions, if they are
supported by target (they are R2 instructions).

llvm-svn: 154540
 2012-04-11 22:13:04 +00:00
Akira Hatanaka 121342fcc2 Reapply 154038 without the failing test. 
llvm-svn: 154062
 2012-04-04 22:16:36 +00:00
Owen Anderson 4743c6e159 Revert r154038. It was causing make check failures. 
llvm-svn: 154054
 2012-04-04 21:18:58 +00:00
Akira Hatanaka 9705c865d9 Fix LowerGlobalAddress to produce instructions with the correct relocation 
types for N32 ABI. Add new test case and update existing ones.

llvm-svn: 154038
 2012-04-04 19:02:38 +00:00
Akira Hatanaka 591ecdd7c1 Fix LowerJumpTable to produce instructions with the correct relocation 
types for N32 ABI. Test case will be updated after the patch that fixes
TargetLowering::getPICJumpTableRelocBase is checked in.

llvm-svn: 154036
 2012-04-04 18:31:32 +00:00
Akira Hatanaka b3a2b8c199 Fix LowerConstantPool to produce instructions with the correct relocation 
types for N32 ABI and update test case.

llvm-svn: 154034
 2012-04-04 18:26:12 +00:00
Akira Hatanaka aeff24e424 Fix LowerBlockAddress to produce instructions with the correct relocation 
types for N32 ABI and update test case.

llvm-svn: 154031
 2012-04-04 18:22:53 +00:00
Akira Hatanaka 0603ad8c65 Expand FREM. 
llvm-svn: 153671
 2012-03-29 18:43:11 +00:00
Akira Hatanaka 8a7633c74e Pass the llvm IR pointer value and offset to the constructor of 
MachinePointerInfo when getStore is called to create a node that stores an
argument passed in register to the stack. Without this change, the post RA 
scheduler will fail to discover the dependencies between the stores
instructions and the instructions that load from a structure passed by value. 

The link to the related discussion is here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html

llvm-svn: 153499
 2012-03-27 03:13:56 +00:00
Akira Hatanaka 769f69f9b6 Fix bug in LowerConstantPool. 
llvm-svn: 153498
 2012-03-27 02:55:31 +00:00
Craig Topper b25fda95f6 Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 
llvm-svn: 152997
 2012-03-17 18:46:09 +00:00
Craig Topper bef78fc2ee Convert more static tables of registers used by calling convention to uint16_t to reduce space. 
llvm-svn: 152538
 2012-03-11 07:57:25 +00:00
Akira Hatanaka da00aa80b6 Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set 
operation action of nodes.

llvm-svn: 152452
 2012-03-10 00:03:50 +00:00
Akira Hatanaka b7f78592e2 Lower SETCC nodes during legalization. Previously, it was lowered in DAG combine pass. 
llvm-svn: 152450
 2012-03-09 23:46:03 +00:00
Akira Hatanaka 5e152182a4 Invoke setTargetDAGCombine for SELECT. 
llvm-svn: 152290
 2012-03-08 03:26:37 +00:00
Akira Hatanaka 7dd7c08419 Swap the operands of a select node if the false (the second) operand is 0. 
For example, this pattern 
(select (setcc lhs, rhs, cc), true, 0)
is transformed to this one:
(select (setcc lhs, rhs, inverse(cc)), 0, true)

This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to
replace 0 with $zero.

llvm-svn: 152285
 2012-03-08 02:14:24 +00:00
Akira Hatanaka 956dd2261e Set minimum function alignment to 3 if target is Mips64. 
llvm-svn: 152282
 2012-03-08 01:59:33 +00:00
Akira Hatanaka 5350c24509 Changes for migrating to using register mask operands. 
llvm-svn: 151847
 2012-03-01 22:27:29 +00:00
Akira Hatanaka 6bbe1f0d10 Fix bugs which were introduced when support for base+index floating point loads 
and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.

llvm-svn: 151843
 2012-03-01 22:12:30 +00:00
Evan Cheng 65f9d19c4f Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call. 
llvm-svn: 151645
 2012-02-28 18:51:51 +00:00