965a73a28c
For ARM/Darwin, add a dwarf entry indicating whether a function is arm or thumb
...
rdar://8202967
llvm-svn: 109057
2010-07-21 23:03:52 +00:00
84bdfd80df
Baby steps towards ARM fast-isel.
...
llvm-svn: 109047
2010-07-21 22:26:11 +00:00
4277e14dc4
Fix calling convention on ARM if vfp2+ is enabled.
...
llvm-svn: 109009
2010-07-21 11:38:30 +00:00
a77f3d3b37
Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
...
llvm-svn: 108991
2010-07-21 06:09:07 +00:00
cbe9856fce
prune #includes a little.
...
llvm-svn: 108929
2010-07-20 21:17:29 +00:00
3680f70c9d
Using BIC for immediates needs an extra bump for its complexity to get
...
instruction selection to prefer it when possible. rdar://7903972
llvm-svn: 108844
2010-07-20 16:07:04 +00:00
9c7708cc1b
Removed un-used code.
...
llvm-svn: 108841
2010-07-20 14:51:32 +00:00
4adaccf0bf
Constify some arguments.
...
llvm-svn: 108812
2010-07-20 06:52:21 +00:00
0aff8033c6
Update CMake files.
...
llvm-svn: 108787
2010-07-20 00:08:13 +00:00
b792b463af
sink the arm implementations of ASmPrinter and MCInstLower
...
out of the AsmPrinter directory into libarm. Now the
ARM InstPrinters depend jsut on the MC stuff, not on vmcore
or codegen.
llvm-svn: 108783
2010-07-19 23:44:46 +00:00
10f99a3490
ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
...
llvm-svn: 108761
2010-07-19 22:15:08 +00:00
8d3ba7349c
Since ARM emits inline jump tables as part of the ConstantIsland pass,
...
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR6581.
llvm-svn: 108730
2010-07-19 17:20:38 +00:00
d9ad52adff
revert so I can get the right PR# in the log message.
...
llvm-svn: 108727
2010-07-19 17:19:40 +00:00
c685756cfb
Since ARM emits inline jump tables as part of the ConstantIsland pass,
...
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR7499.
llvm-svn: 108722
2010-07-19 17:18:28 +00:00
419197cc4d
Target: Give the TargetAsmParser access to the TargetMachine.
...
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.
llvm-svn: 108664
2010-07-19 00:33:49 +00:00
b97e2bbe32
Add combiner patterns to more effectively utilize the BFI (bitfield insert)
...
instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.
llvm-svn: 108608
2010-07-17 03:30:54 +00:00
6e3b5fa91c
add BFI to getTargetNodeName()
...
llvm-svn: 108603
2010-07-17 01:50:57 +00:00
adc81f8ee8
Fix logic think-o
...
llvm-svn: 108601
2010-07-17 01:22:19 +00:00
83f250f005
Remove unnecessary check that was subsumed into canRealignStack.
...
llvm-svn: 108588
2010-07-17 00:33:04 +00:00
24e3aa011a
Make more explicit and add some currently disabled error messages for
...
stack realignment on ARM.
Also check for function attributes as we do on X86 as well as
make explicit that we're checking can as well as needs in this function.
llvm-svn: 108582
2010-07-17 00:27:24 +00:00
11013eda5a
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
...
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.
llvm-svn: 108570
2010-07-16 23:05:05 +00:00
8289f78569
Remove the isMoveInstr() hook.
...
llvm-svn: 108567
2010-07-16 22:35:46 +00:00
54bcf5049e
Use a small local function for a single remaining late isMoveInstr call in
...
Thumb2ITBlockPass.
llvm-svn: 108564
2010-07-16 22:35:32 +00:00
499f797cdd
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
...
thus is a much more meaningful name.
llvm-svn: 108563
2010-07-16 22:20:36 +00:00
55f0c6b9fc
Split -enable-finite-only-fp-math to two options:
...
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.
llvm-svn: 108465
2010-07-15 22:07:12 +00:00
e4be4308a9
Random note about bswap.
...
llvm-svn: 108396
2010-07-15 02:20:38 +00:00
0b9aafddc5
Remove restriction on NEON alignment values. Some of the NEON ld/st
...
instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.
llvm-svn: 108386
2010-07-14 23:54:43 +00:00
92d8998348
Don't pass StringRef by reference.
...
llvm-svn: 108366
2010-07-14 22:38:02 +00:00
a90af1ba38
Improve 64-subtraction of immediates when parts of the immediate can fit
...
in the literal field of an instruction. E.g.,
long long foo(long long a) {
return a - 734439407618LL;
}
rdar://7038284
llvm-svn: 108339
2010-07-14 17:45:16 +00:00
1aef53403f
Add missing address register update to t2LDM_RET instruction.
...
Patch by Brian Lucas. PR7636.
llvm-svn: 108332
2010-07-14 16:02:13 +00:00
c4d70125ee
A couple potential optimizations inspired by comment 4 in PR6773.
...
llvm-svn: 108328
2010-07-14 06:58:26 +00:00
bad47f62f6
Add support for NEON VMVN immediate instructions.
...
llvm-svn: 108324
2010-07-14 06:31:50 +00:00
bd54a53628
The bits in the cmode field of 32-bit VMOV immediate instructions all depend
...
of the value of the immediate.
llvm-svn: 108323
2010-07-14 06:30:44 +00:00
103a0dcfe1
Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
...
Radar 7373643.
llvm-svn: 108303
2010-07-14 01:22:12 +00:00
a3f1901531
Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
...
NEON VMOV-immediate instructions. This simplifies some things.
llvm-svn: 108275
2010-07-13 21:16:48 +00:00
0cc4ad983d
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
...
llvm-svn: 108258
2010-07-13 19:27:42 +00:00
58066e337d
Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).
...
llvm-svn: 108256
2010-07-13 19:21:50 +00:00
c1c6f4796e
Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to
...
avoid replicated code.
llvm-svn: 108227
2010-07-13 04:44:34 +00:00
8a2bdc8231
Remove some code that doesn't appear to do anything. All the ARM call
...
instructions already have implicit defs of LR. The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.
llvm-svn: 108186
2010-07-12 20:22:45 +00:00
41b4a6b36a
Convert some tab stops into spaces.
...
llvm-svn: 108130
2010-07-12 08:16:59 +00:00
0961c55161
RISC architectures get their memory operand folding for free.
...
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.
llvm-svn: 108099
2010-07-11 19:19:13 +00:00
1da1cfccb1
Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.
...
llvm-svn: 108094
2010-07-11 16:49:10 +00:00
d7b33002dd
Replace copyRegToReg with copyPhysReg for ARM.
...
llvm-svn: 108078
2010-07-11 06:33:54 +00:00
a76eccf815
Fix va_arg for doubles. With this patch VAARG nodes always contain the
...
correct alignment information, which simplifies ExpandRes_VAARG a bit.
The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:
* The 's' in target data: If this is set to the minimal alignment of any
argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
example.
* The getTransientStackAlignment method. It is possible for an architecture to
have argument less aligned than what we maintain the stack pointer.
llvm-svn: 108072
2010-07-11 04:01:49 +00:00
d162d85688
Add parentheses yet again to satisfy GCC's warnings.
...
llvm-svn: 108043
2010-07-10 12:06:22 +00:00
7a7b55eb67
Automatically fold COPY instructions into stack load/store.
...
llvm-svn: 108012
2010-07-09 20:43:13 +00:00
2a5725b1a3
In the presence of variable sized objects, allocate an emergency spill slot.
...
rdar://8131327
llvm-svn: 108008
2010-07-09 20:27:06 +00:00
88a4e6dc0e
Print "dregpair" NEON operands with a space between them, for readability and
...
consistency with other instructions that have lists of register operands.
llvm-svn: 107944
2010-07-09 00:47:20 +00:00
0f54854a1d
Check for FiniteOnlyFPMath as well.
...
llvm-svn: 107904
2010-07-08 20:12:24 +00:00
181e5af248
The NEONPreAllocPass should never have to assign fixed registers anymore.
...
This pass can go away entirely soon.
llvm-svn: 107892
2010-07-08 17:45:26 +00:00
1eade1a327
For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the
...
words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements
instead.
llvm-svn: 107890
2010-07-08 17:44:00 +00:00
6c25043493
Clean up a comment.
...
llvm-svn: 107882
2010-07-08 16:54:45 +00:00
00264624a9
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
...
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
llvm-svn: 107879
2010-07-08 16:40:22 +00:00
be1f7a931e
r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.
...
llvm-svn: 107856
2010-07-08 06:01:49 +00:00
25f9364cbd
Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
...
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.
e.g.
vldr.32 s0, [r1]
vldr.32 s1, [r0]
vcmpe.f32 s1, s0
vmrs apsr_nzcv, fpscr
beq LBB0_2
=>
ldr r1, [r1]
ldr r0, [r0]
cmp r0, r1
beq LBB0_2
More complicated cases will be implemented in subsequent patches.
llvm-svn: 107852
2010-07-08 02:08:50 +00:00
e2289285ae
Changes to ARM tail calls, mostly cosmetic.
...
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.
llvm-svn: 107851
2010-07-08 01:18:23 +00:00
73ef80f76f
grammar
...
llvm-svn: 107831
2010-07-07 22:53:35 +00:00
40eda1076a
Handle cases where the post-RA scheduler may move instructions between the
...
address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682
llvm-svn: 107830
2010-07-07 22:51:22 +00:00
e4ba2aa0c4
grammar and trailing whitespace
...
llvm-svn: 107811
2010-07-07 21:06:51 +00:00
fe7532a308
Split the SDValue out of OutputArg so that SelectionDAG-independent
...
code can do calling-convention queries. This obviates OutputArgReg.
llvm-svn: 107786
2010-07-07 15:54:55 +00:00
5bc8a79e7f
Also use REG_SEQUENCE for VTBX instructions.
...
llvm-svn: 107743
2010-07-07 00:08:54 +00:00
3198483851
Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where
...
they've been tested to work.
llvm-svn: 107742
2010-07-07 00:07:57 +00:00
dc0a0659be
By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather
...
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.
llvm-svn: 107734
2010-07-06 23:44:52 +00:00
3ed511bc6b
Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
...
allocated to consecutive registers.
llvm-svn: 107730
2010-07-06 23:36:25 +00:00
48deb12593
Track defs for all aliases in NEONMoveFix.
...
This means that an instruction defining an S register will affect the domain of
the parent D register.
llvm-svn: 107725
2010-07-06 23:26:23 +00:00
a3ca21b228
Propagate debug loc.
...
llvm-svn: 107710
2010-07-06 22:08:15 +00:00
4c1ca29039
Represent NEON load/store alignments in bytes, not bits.
...
llvm-svn: 107701
2010-07-06 21:26:18 +00:00
3439629239
Reapply r107655 with fixes; insert the pseudo instruction into
...
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
llvm-svn: 107691
2010-07-06 20:24:04 +00:00
7c510aa7bc
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
...
if profitable.
llvm-svn: 107673
2010-07-06 16:24:34 +00:00
f4f04107ef
Revert r107655.
...
llvm-svn: 107668
2010-07-06 15:49:48 +00:00
12205645a6
Fix a bunch of custom-inserter functions to handle the case where
...
the pseudo instruction is not at the end of the block.
llvm-svn: 107655
2010-07-06 15:18:19 +00:00
0664a67fe1
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
...
llvm-svn: 107550
2010-07-03 00:40:23 +00:00
c3525dc0fd
Remove early IT block formation. It's not used.
...
llvm-svn: 107513
2010-07-02 21:07:09 +00:00
771d04b969
Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so
...
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.
llvm-svn: 107487
2010-07-02 17:23:44 +00:00
8a99b730a9
ARM function alignments were off by a power of two. svn 83242 changed
...
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer. The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.
llvm-svn: 107435
2010-07-01 22:26:26 +00:00
be157b0ea8
Add support for encoding VDUP (ARM core register) instructions.
...
llvm-svn: 107201
2010-06-29 20:13:29 +00:00
ab0819e10d
Add support for encoding NEON VMOV (from core register to scalar) instructions.
...
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.
llvm-svn: 107167
2010-06-29 17:34:07 +00:00
5bee07ec68
skip dbg_value instructions
...
llvm-svn: 107154
2010-06-29 16:55:24 +00:00
83b993a977
The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add
...
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.
llvm-svn: 107147
2010-06-29 16:25:11 +00:00
38a7d7cbc3
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
...
of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
llvm-svn: 107140
2010-06-29 14:02:34 +00:00
193bb1ee6a
Remove pointless variable LastDef.
...
llvm-svn: 107135
2010-06-29 13:23:22 +00:00
257eba4df7
Remove unused variable Loc and pointless variables unified_syntax
...
and thumb_mode.
llvm-svn: 107133
2010-06-29 13:04:35 +00:00
78ad27ca2b
Remove an unused and a pointless variable.
...
llvm-svn: 107131
2010-06-29 13:00:29 +00:00
6d28e73acc
Remove initialized but otherwise unused variables.
...
llvm-svn: 107127
2010-06-29 11:22:26 +00:00
b59dd8f10a
PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
...
llvm-svn: 107122
2010-06-29 05:38:36 +00:00
0c30739cbb
Change if-cvt options to something that actually as useable.
...
llvm-svn: 107121
2010-06-29 05:37:59 +00:00
c1eccbc468
When no memoperands are present, assume unaligned, volatile.
...
llvm-svn: 107114
2010-06-29 01:13:07 +00:00
3d12ff797b
Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is
...
the same as ARM except that the condition code field is always set to ARMCC::AL.
llvm-svn: 107107
2010-06-29 00:26:13 +00:00
4469a892b4
Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
...
of the Subtarget.
llvm-svn: 107086
2010-06-28 22:23:17 +00:00
f31c004666
tidy up style. no functional change.
...
llvm-svn: 107073
2010-06-28 21:29:17 +00:00
544317dfda
Refactor encoding function for NEON 1-register with modified immediate format.
...
llvm-svn: 107070
2010-06-28 21:16:30 +00:00
584387d5e3
Support Thumb mode encoding of NEON instructions.
...
llvm-svn: 107068
2010-06-28 21:12:19 +00:00
7ea5fc0794
minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change.
...
llvm-svn: 106988
2010-06-28 04:27:01 +00:00
8cfa7713e9
Followup to r106770: actually generate SXTB and SXTH for sign-extensions.
...
llvm-svn: 106940
2010-06-26 04:36:50 +00:00
0248da9db4
Add support for encoding NEON VMOV (from scalar to core register) instructions.
...
llvm-svn: 106938
2010-06-26 04:07:15 +00:00
b71233f34d
It's now possible to run code placement pass for ARM.
...
llvm-svn: 106935
2010-06-26 01:52:05 +00:00
b4d39841e4
Renumber NEON instruction formats to be consecutive.
...
llvm-svn: 106927
2010-06-26 00:05:09 +00:00
cc386fb125
Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to
...
"N..." instead of "NEON..." for consistency with the other NEON format names.
llvm-svn: 106921
2010-06-25 23:56:05 +00:00
d66f66a5cf
Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.
...
Renumber MiscFrm to 25.
llvm-svn: 106916
2010-06-25 23:45:37 +00:00
acbdf53db4
Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was
...
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.
llvm-svn: 106908
2010-06-25 23:14:54 +00:00
Jim Grosbach