c4ad46605e
Add llvm-size.
...
llvm-svn: 140722
2011-09-28 20:57:46 +00:00
800619f2bb
Object: Add isSection{Data,BSS}.
...
llvm-svn: 140721
2011-09-28 20:57:30 +00:00
c7a710f61e
NULL cannot be portably used as the last argument to a function with __attribute((sentinel)), even though it usually works. Use (void*)0 instead. PR11002.
...
llvm-svn: 140720
2011-09-28 20:41:50 +00:00
315b9573c6
Perform the lowering only if there are invokes.
...
llvm-svn: 140719
2011-09-28 20:29:45 +00:00
dfe5acd34e
Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.
...
llvm-svn: 140718
2011-09-28 20:29:28 +00:00
508503b473
Add a note on removing LLVMC.
...
llvm-svn: 140715
2011-09-28 19:47:28 +00:00
3714065a94
Introduce llvm-cov.
...
Add llvm-cov skeleton. It has initial support to read coverage info generated by GCOVProfiling.cpp.
Today, you can do
prompt> clang a.c -ftest-coverage -fprofile-arcs -o a
prompt> ./a
prompt> llvm-cov -gcno a.gcno -gcda a.gcda
a.c
: #include "a.h"
:
: int main() {
: int i = 0;
: if (i) {
1: int j = 0;
1: j = 1;
1: } else {
: int k = 1;
: k = 2;
: }
1: return 0;
: }
:
:
llvm-svn: 140712
2011-09-28 18:50:00 +00:00
933d51682f
PTX: Fix alignment logic
...
llvm-svn: 140709
2011-09-28 18:24:58 +00:00
6f37b4a5a5
Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.
...
llvm-svn: 140705
2011-09-28 18:11:19 +00:00
edc172d4cc
Remove definitions of branch-on-FP-likely instructions. They are deprecated.
...
llvm-svn: 140704
2011-09-28 17:56:55 +00:00
c117967b19
Mips64 predicate definitions. Patch by Liu.
...
llvm-svn: 140703
2011-09-28 17:50:27 +00:00
ef8e4efff8
indvars: generalize SCEV getPreStartForSignExtend.
...
Handle general Add expressions to avoid leaving around redundant
32-bit IVs.
llvm-svn: 140701
2011-09-28 17:02:54 +00:00
f3d1d4eb4b
PTX: MC-ize the PTX backend (patch 2 of N)
...
Get rid of some of the no-longer-needed parts of PTXAsmPrinter.
llvm-svn: 140698
2011-09-28 14:32:06 +00:00
5e18b14ee2
PTX: MC-ize the PTX back-end (patch 1 of N)
...
Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.
llvm-svn: 140697
2011-09-28 14:32:04 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
...
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
56c58ce3d6
Changed comments on foreign C++ exceptions (generated with type info 7),
...
handling with references to
http://sourcery.mentor.com/public/cxx-abi/abi-eh.html (r 1.22).
llvm-svn: 140695
2011-09-28 10:53:56 +00:00
2e67937f76
A typeid of zero means a cleanup, not a catch. This case occurs
...
when there is both a catch and a cleanup. Correct the comment.
llvm-svn: 140686
2011-09-28 09:13:02 +00:00
8747e3e7ea
PTX: Simplify code. No functionality change.
...
llvm-svn: 140680
2011-09-28 04:32:36 +00:00
5d7a73fa8c
PTX: Pass param name strings per const reference.
...
The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++)
llvm-svn: 140679
2011-09-28 04:08:02 +00:00
baf3941fde
Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.
...
llvm-svn: 140678
2011-09-28 03:52:41 +00:00
225e8481b0
Bitcast the alloca to an i8* to match the intrinsic's signature.
...
llvm-svn: 140677
2011-09-28 03:47:11 +00:00
66b110f571
Create and use an llvm.eh.sjlj.functioncontext intrinsic.
...
This intrinsic is used to pass the index of the function context to the back-end
for further processing. The back-end is in charge of filling in the rest of the
entries.
llvm-svn: 140676
2011-09-28 03:36:43 +00:00
2e76ca9d9a
In the new EH model, setup the function context and the call site info.
...
The DWARF exception pass uses the call site information, which is set up here. A
pre-RA pass is too late for it to use this information. So create and setup the
function context here, and then insert the call site values here (and map the
call sites for the DWARF EH pass). This is simpler than the original pass, and
doesn't make the CFG lose its SSA-ness.
It's a win-win-win-win-lose-win-win situation.
llvm-svn: 140675
2011-09-28 03:14:05 +00:00
e6138e3ad1
Don't conditionalize execution of the SjLj EH prepare pass.
...
We may need an SjLj EH preparation pass for some call site information, at least
in the short term.
llvm-svn: 140674
2011-09-28 03:07:34 +00:00
8c219ecd1a
Test case for r140670: indvars should hoist sext.
...
llvm-svn: 140671
2011-09-28 02:13:32 +00:00
e0e30532a5
indvars should hoist [sz]ext because licm is not rerun.
...
llvm-svn: 140670
2011-09-28 01:35:36 +00:00
5f476dc3ef
PR10628: Fix getModRefInfo so it queries the underlying alias() implementation correctly while checking nocapture calls.
...
llvm-svn: 140666
2011-09-28 00:34:27 +00:00
bd5109f14d
Rename class and clean up source.
...
No functional change intended.
llvm-svn: 140664
2011-09-28 00:01:56 +00:00
934b7d7645
Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.
...
I'll clean up the source in the next commit.
llvm-svn: 140663
2011-09-28 00:01:54 +00:00
ae40dc735d
Remove MipsFPRound. Mips1 is no longer supported.
...
llvm-svn: 140661
2011-09-27 23:55:37 +00:00
30c811246f
Remove X86-dependent stuff from SSEDomainFix.
...
This also enables domain swizzling for AVX code which required a few
trivial test changes.
The pass will be moved to lib/CodeGen shortly.
llvm-svn: 140659
2011-09-27 23:50:46 +00:00
e3e36f80f5
Unbreak CMake build.
...
llvm-svn: 140655
2011-09-27 23:29:59 +00:00
f9b71a2e01
Implement TII::get/setExecutionDomain() for ARM.
...
llvm-svn: 140653
2011-09-27 22:57:21 +00:00
b48c994cc0
Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.
...
I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass. They are essentially doing the same
thing.
llvm-svn: 140652
2011-09-27 22:57:18 +00:00
c63af1b7b6
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
...
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
llvm-svn: 140647
2011-09-27 22:18:54 +00:00
354ff9e348
This is the start of the new SjLj EH preparation pass, which will replace the
...
current IR-level pass.
The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).
Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.
llvm-svn: 140646
2011-09-27 22:14:12 +00:00
a5d18f2d7e
Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
...
of the instruction definitions using Pat<>.
llvm-svn: 140644
2011-09-27 22:01:01 +00:00
7a6e8f2c5d
Remove an invalid assert that is really just asserting when the scheduler emits
...
a suboptimal schedule.
llvm-svn: 140643
2011-09-27 21:59:16 +00:00
6a2eb5c1c8
test/CMakeLists.txt: Depend on llvm-objdump. "make check" is expected to resolve test-dependent targets on CMake build.
...
llvm-svn: 140641
2011-09-27 21:54:50 +00:00
af136f71ec
Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().
...
Naming conventions consistency. No functional change.
llvm-svn: 140636
2011-09-27 20:59:33 +00:00
547b6c5ecd
Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit.
...
If someone prefers %tmp42 to %42, run instnamer.
llvm-svn: 140634
2011-09-27 20:39:19 +00:00
b762df5840
Remove incorrect passage.
...
llvm-svn: 140631
2011-09-27 20:16:57 +00:00
bf415251df
These symbols appear to be visible by SearchForAddressOfSymbol and no longer
...
require special case handling.
rdar://10117377
llvm-svn: 140629
2011-09-27 20:01:41 +00:00
2bc774ac1a
Add binary archive support to llvm-nm.
...
llvm-svn: 140627
2011-09-27 19:37:18 +00:00
d3b7b12618
Object: Add archive support.
...
llvm-svn: 140626
2011-09-27 19:36:55 +00:00
68ba81346e
Check that catch clauses have pointer type.
...
llvm-svn: 140625
2011-09-27 19:34:22 +00:00
4f7054e56e
PTX: Fix case where printed alignment could be 0
...
llvm-svn: 140624
2011-09-27 19:25:49 +00:00
554a012eb5
Unbreak tests.
...
llvm-svn: 140622
2011-09-27 19:06:37 +00:00
d9f23c4f6b
Add FCA to the lexicon.
...
llvm-svn: 140619
2011-09-27 18:44:01 +00:00
e074593498
PTX: Use external symbols to keep track of params and locals. This also fixes
...
a couple of outstanding issues with frame objects occuring as instruction
operands.
llvm-svn: 140616
2011-09-27 18:12:55 +00:00
1c7597693c
Use existing function.
...
llvm-svn: 140615
2011-09-27 17:55:08 +00:00
e41b1d59f0
Fix function MipsRegisterInfo::getRegisterNumbering.
...
Return numbers of 64-bit registers.
llvm-svn: 140609
2011-09-27 17:15:27 +00:00
ff5d0965b0
Do not add the pass that restores $gp if target is Mips64.
...
llvm-svn: 140607
2011-09-27 16:58:43 +00:00
86de1a666d
Have the verifier check that all landingpad operands are constants.
...
llvm-svn: 140606
2011-09-27 16:43:19 +00:00
38b3b83362
Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC.
...
Add a new method: getAnyExtOrTrunc and use it to replace the manual check.
llvm-svn: 140603
2011-09-27 11:16:47 +00:00
1b857d2762
Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8,
...
while the decision is to bit-pack small values.
llvm-svn: 140601
2011-09-27 10:48:29 +00:00
614c8e5146
Remove some not-really-correct wording.
...
llvm-svn: 140600
2011-09-27 10:37:28 +00:00
bb050745e7
Mark MipsPseudo isPseudo.
...
llvm-svn: 140598
2011-09-27 04:57:54 +00:00
9f01f89386
PTX: Add support for sitofp in backend
...
llvm-svn: 140593
2011-09-27 01:04:47 +00:00
90f90da156
Split the landing pad basic block with the correct function. Also merge the
...
split landingpad instructions into a PHI node.
PR11016
llvm-svn: 140592
2011-09-27 00:59:31 +00:00
581243919d
Disable LSR retry by default.
...
Disabling aggressive LSR saves compilation time, and with the new
indvars behavior usually improves performance.
llvm-svn: 140590
2011-09-27 00:44:14 +00:00
f6fbfd3f83
Last batch of test conversions to new atomic instructions.
...
llvm-svn: 140585
2011-09-27 00:17:29 +00:00
8868faec63
LSR, one of the new Cost::isLoser() checks did not get merged in the previous checkin.
...
llvm-svn: 140583
2011-09-26 23:35:25 +00:00
a486cb972f
Convert a bunch more tests over to the new atomic instructions.
...
llvm-svn: 140582
2011-09-26 23:15:09 +00:00
b1a9f65487
Remove extraneous commit garbage.
...
llvm-svn: 140581
2011-09-26 23:14:02 +00:00
784729d408
LSR cost metric minor fix and verification.
...
The minor bug heuristic was noticed by inspection. I added the
isLoser/isValid helpers because they will become more
important with subsequent checkins.
llvm-svn: 140580
2011-09-26 23:11:04 +00:00
287d6ef088
Fix an incorrect decoder test.
...
llvm-svn: 140579
2011-09-26 23:08:34 +00:00
02bb7573fb
Remove old hack for compiling with gcc-4.0.
...
llvm-svn: 140573
2011-09-26 22:30:57 +00:00
d20cd25c69
Remove incorrect testcases.
...
llvm-svn: 140572
2011-09-26 22:13:55 +00:00
a6a9c20c23
Set register class of a register according to value of HasMips64.
...
llvm-svn: 140570
2011-09-26 21:55:17 +00:00
7b502920ef
Define variable HasMips64 in MipsTargetLowering.
...
llvm-svn: 140569
2011-09-26 21:47:02 +00:00
e5ce709022
In single float mode, double precision FP arguments are passed in integer
...
registers, so there is no need to check here.
llvm-svn: 140568
2011-09-26 21:37:50 +00:00
ab7b99ab9c
Convert more tests to new atomic instructions.
...
llvm-svn: 140567
2011-09-26 21:36:10 +00:00
6fb0c1e474
Convert more tests over to the new atomic instructions.
...
I did not convert Atomics-32.ll and Atomics-64.ll by hand; the diff is autoupgrade output.
The wmb test is gone because there isn't any way to express wmb with the new atomic instructions; if someone really needs a non-asm way to write a wmb on Alpha, a platform-specific intrisic could be added.
llvm-svn: 140566
2011-09-26 21:30:17 +00:00
878a67397d
Fix grammar.
...
llvm-svn: 140564
2011-09-26 21:10:31 +00:00
dec0ee3237
Remove dead table entry.
...
llvm-svn: 140563
2011-09-26 21:08:28 +00:00
58c80f886c
Some minor (and more involved) cleanups. No real context changes.
...
llvm-svn: 140561
2011-09-26 21:06:33 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
...
llvm-svn: 140560
2011-09-26 21:06:22 +00:00
c064f2c33e
Convert more tests over to the new atomic instructions.
...
llvm-svn: 140559
2011-09-26 20:27:49 +00:00
bda9e7af58
Upgrade a couple more tests to the new atomic instructions.
...
llvm-svn: 140558
2011-09-26 20:15:56 +00:00
5c91891cf3
Enhance alias analysis for atomic instructions a bit. Upgrade a couple alias-analysis tests to the new atomic instructions.
...
llvm-svn: 140557
2011-09-26 20:15:28 +00:00
da2919dbd8
PTX: Fix memcpy intrinsic to handle 64-bit pointers
...
llvm-svn: 140556
2011-09-26 19:19:48 +00:00
67d33b3bf2
Fix this test so it doesn't fail on Mac.
...
llvm-svn: 140553
2011-09-26 19:13:47 +00:00
b40da7f956
PTX: Implement PTXSelectionDAGInfo
...
llvm-svn: 140549
2011-09-26 18:57:27 +00:00
c3edaddfea
PTX: Implement ISD::ANY_EXTEND
...
llvm-svn: 140548
2011-09-26 18:57:24 +00:00
1395cf8423
PTX: Fix detection of stack load/store vs. global load/store, as well as fix the
...
printing of local offsets
llvm-svn: 140547
2011-09-26 18:57:22 +00:00
0ceb8cadd2
Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more.
...
llvm-svn: 140539
2011-09-26 17:40:42 +00:00
55f340eb62
PTX: Add .align tests to stack object test file
...
llvm-svn: 140537
2011-09-26 16:20:38 +00:00
f8dd701bf9
PTX: SM > 2.0 implies +double
...
llvm-svn: 140536
2011-09-26 16:20:36 +00:00
14defde057
PTX: Fix some lingering issues with stack allocation
...
llvm-svn: 140535
2011-09-26 16:20:34 +00:00
37fd87675f
PTX: Split up the TableGen instruction definitions into logical units
...
llvm-svn: 140534
2011-09-26 16:20:31 +00:00
d40f5ababf
PTX: Unify handling of loads/stores
...
llvm-svn: 140533
2011-09-26 16:20:28 +00:00
8c80019352
PTX: Handle FrameIndex nodes
...
llvm-svn: 140532
2011-09-26 16:20:25 +00:00
1748b37acd
Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported
...
llvm-svn: 140517
2011-09-26 06:44:27 +00:00
b1fbf9ff26
PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
...
llvm-svn: 140516
2011-09-26 06:13:20 +00:00
45faba98b4
Fix VEX decoding in i386 mode. Fixes PR11008.
...
llvm-svn: 140515
2011-09-26 05:12:43 +00:00
df977fedb6
Add target hook for pseudo instruction expansion.
...
Many targets use pseudo instructions to help register allocation. Like
the COPY instruction, these pseudos can be expanded after register
allocation. The early expansion can make life easier for PEI and the
post-ra scheduler.
This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.
llvm-svn: 140472
2011-09-25 19:21:35 +00:00
2279949129
[vector-select] Address one of the issues in pr10902. EXTRACT_VECTOR_ELEMENT
...
SDNodes may return values which are wider than the incoming element types. In
this patch we fix the integer promotion of these nodes.
Fixes spill-q.ll when running -promote-elements.
llvm-svn: 140471
2011-09-25 18:59:42 +00:00
fd719d184e
Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos.
...
No functional change intended.
llvm-svn: 140470
2011-09-25 16:46:08 +00:00
f152df1e6b
Rename LowerSubregs to ExpandPostRAPseudos.
...
I'll fix the file contents in the next commit.
This pass is currently expanding the COPY and SUBREG_TO_REG pseudos. I
am going to add a hook so targets can expand more pseudo-instructions
after register allocation.
Many targets have pseudo-instructions that assist the register
allocator. They can be expanded after register allocation, before PEI
and PostRA scheduling.
llvm-svn: 140469
2011-09-25 16:46:00 +00:00
Michael J. Spencer