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86 Commits

Author SHA1 Message Date
Chris Lattner adcaf294d7 Move the Imp tblgen class from the X86 backend to common code. 
llvm-svn: 30907
 2006-10-12 17:49:27 +00:00
Evan Cheng c767acd25a Add code size to target instruction use it as the 3rd isel sorting tie-breaker. 
llvm-svn: 29193
 2006-07-19 00:24:41 +00:00
Evan Cheng f3cbd7ef31 Added a Flags field to TargetOperandInfo. Currently the only flag is 
M_LOOK_UP_PTR_REG_CLASS which allows the register class of the operand to be
resolved via a callback at runtime.

llvm-svn: 28387
 2006-05-18 20:44:26 +00:00
Evan Cheng 297e1cb10a Remove CalleeSavedRegisters from class Target. 
llvm-svn: 28377
 2006-05-18 00:09:53 +00:00
Evan Cheng dcec882286 Remove PointerType from class Target 
llvm-svn: 28368
 2006-05-17 21:20:27 +00:00
Vladimir Prus 788db2c812 Replace "../whatever.td" with "whatever.td", so that out-of-tree backends 
can just add lib/Target to TableGen includes.

llvm-svn: 28318
 2006-05-16 06:39:36 +00:00
Chris Lattner fce45ffcd6 Improve comment, patch provided by Vladimir Prus! 
llvm-svn: 28307
 2006-05-15 18:35:02 +00:00
Chris Lattner 215280d8b9 Update comment. 
llvm-svn: 28283
 2006-05-14 02:05:19 +00:00
Chris Lattner 85e9909755 Put PHI/INLINEASM into the correct namespace. 
llvm-svn: 28037
 2006-05-01 17:00:49 +00:00
Evan Cheng 52df74000a Renamed AddedCost to AddedComplexity. 
llvm-svn: 27843
 2006-04-19 20:38:28 +00:00
Evan Cheng aa3325e925 Allow "let AddedCost = n in" to increase pattern complexity. 
llvm-svn: 27834
 2006-04-19 18:07:24 +00:00
Jim Laskey 3b338d5566 Add support for dwarf register numbering. 
llvm-svn: 27080
 2006-03-24 21:13:21 +00:00
Chris Lattner c6b13e21cc Shuffle some includes around 
llvm-svn: 27073
 2006-03-24 18:52:35 +00:00
Chris Lattner b203355298 Split the valuetypes out of Target.td into ValueTypes.td 
llvm-svn: 26490
 2006-03-03 01:55:26 +00:00
Evan Cheng 91c574b642 New type v2f32. 
llvm-svn: 26435
 2006-03-01 01:06:22 +00:00
Evan Cheng 43070b7541 Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit 
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

llvm-svn: 26294
 2006-02-20 22:34:53 +00:00
Evan Cheng d98701c639 Subtarget feature can now set any variable to any value 
llvm-svn: 25678
 2006-01-27 08:09:42 +00:00
Chris Lattner 1240574609 PHI and INLINEASM are now built-in instructions provided by Target.td 
llvm-svn: 25674
 2006-01-27 01:46:15 +00:00
Evan Cheng 7785e5b3a4 New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace 
hasInFlag, hasOutFlag.

llvm-svn: 25155
 2006-01-09 18:28:21 +00:00
Evan Cheng 14c53b45f5 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
 2005-12-26 09:11:45 +00:00
Evan Cheng 9ae486047e * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. 
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997
 2005-12-23 22:14:32 +00:00
Evan Cheng d296a43f96 Added support to specify predicates. 
llvm-svn: 24715
 2005-12-14 22:02:59 +00:00
Evan Cheng e8531381e2 * Added instruction property hasCtrlDep for those which r/w control-flow 
chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
  chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.

llvm-svn: 24586
 2005-12-04 08:13:17 +00:00
Nate Begeman 006bb04f3a Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.

llvm-svn: 24563
 2005-12-01 04:51:06 +00:00
Nate Begeman 89b049af90 Add the majority of the vector machien value types we expect to support, 
and make a few changes to the legalization machinery to support more than
16 types.

llvm-svn: 24511
 2005-11-29 05:45:29 +00:00
Chris Lattner c418b5d938 refix typo 
llvm-svn: 24505
 2005-11-29 00:42:30 +00:00
Chris Lattner d3bc8cb26d revert my change for the time being, which broke the build 
llvm-svn: 24503
 2005-11-29 00:24:08 +00:00
Chris Lattner 50986909dc fix a typo :) 
llvm-svn: 24501
 2005-11-28 22:42:15 +00:00
Chris Lattner 252d88c68e Capture more operand info, patch by Evan Cheng 
llvm-svn: 24422
 2005-11-19 07:00:10 +00:00
Nate Begeman 227f1bdd2f Also add the new vector value type here, for completeness. 
llvm-svn: 24405
 2005-11-18 00:53:32 +00:00
Jim Laskey 53ad110490 Add attribute name and type to SubtargetFeatures. 
llvm-svn: 24012
 2005-10-26 17:28:23 +00:00
Jim Laskey 9ed9032e22 Plugin new subtarget backend into the build. 
llvm-svn: 23870
 2005-10-21 19:05:19 +00:00
Jim Laskey 74ab9960f2 Added InstrSchedClass to each of the PowerPC Instructions. 
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.

llvm-svn: 23830
 2005-10-19 19:51:16 +00:00
Jim Laskey 9761100055 Push processor descriptions to the top of target and add command line info. 
llvm-svn: 23820
 2005-10-19 13:34:52 +00:00
Chris Lattner d83571bbf2 Pull DAG ISel generation nodes out of the PowerPC backend to where they 
can be used by other targets.  For those targets that want to use it,
have at.  :)

llvm-svn: 23680
 2005-10-10 06:00:30 +00:00
Chris Lattner d1a5bc8dbd Add a forward def 
llvm-svn: 23621
 2005-10-04 05:09:20 +00:00
Chris Lattner 33ce5f8a73 Now that self referential classes are supported, get rid of a work-around. 
llvm-svn: 23544
 2005-09-30 04:13:23 +00:00
Chris Lattner c6a0338c04 spell this right 
llvm-svn: 23099
 2005-08-26 20:55:40 +00:00
Chris Lattner 0081dfa91e Add a flag 
llvm-svn: 23092
 2005-08-26 20:29:01 +00:00
Chris Lattner d24ad52efa add an enum value 
llvm-svn: 23048
 2005-08-25 17:07:09 +00:00
Chris Lattner bd26a82051 Split RegisterClass 'Methods' into MethodProtos and MethodBodies 
llvm-svn: 22929
 2005-08-19 19:13:20 +00:00
Chris Lattner 3fb85f2702 Require that targets specify a namespace for their register classes. 
llvm-svn: 22921
 2005-08-19 18:48:48 +00:00
Chris Lattner 5cfa377947 Add a new flag 
llvm-svn: 22881
 2005-08-18 23:17:07 +00:00
Chris Lattner 182db0cac0 Add some bits that can be set for instructions. 
llvm-svn: 19241
 2005-01-02 02:27:48 +00:00
Misha Brukman dba1f62eb8 Add isLittleEndianEncoding to InstrInfo class, defaults to `off' 
llvm-svn: 16976
 2004-10-14 05:53:40 +00:00
Chris Lattner 42c43b2cb3 Add initial support for variants 
llvm-svn: 16635
 2004-10-03 19:34:18 +00:00
Nate Begeman c762ab723b Add support for the isLoad and isStore flags, needed by the instruction scheduler 
llvm-svn: 16555
 2004-09-28 21:29:00 +00:00
Chris Lattner 6652223bd6 Capture delay slot info 
llvm-svn: 16551
 2004-09-28 18:34:14 +00:00
Chris Lattner e8e81a2941 Revamp the Register class, and allow the use of the RegisterGroup class to 
specify aliases directly in register definitions.

Patch contributed by Jason Eckhardt!

llvm-svn: 16330
 2004-09-14 04:17:02 +00:00
Chris Lattner 6a92fdef72 Add two values 
llvm-svn: 15959
 2004-08-21 02:17:39 +00:00