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5967 Commits

Author SHA1 Message Date
Chris Lattner 95129a7f22 Expose method and ivars for measuring inline asm length properly. 
llvm-svn: 30934
 2006-10-13 17:50:07 +00:00
Rafael Espindola 5ab3166f74 add FNEGS and FNEGD 
llvm-svn: 30932
 2006-10-13 17:37:35 +00:00
Rafael Espindola d6050c3149 add SBCS and SUBS 
llvm-svn: 30930
 2006-10-13 17:19:20 +00:00
Rafael Espindola 79d9807c87 implement calls to functions that return long 
llvm-svn: 30929
 2006-10-13 16:47:22 +00:00
Rafael Espindola 3874a168d0 implement unordered floating point compares 
llvm-svn: 30928
 2006-10-13 13:14:59 +00:00
Chris Lattner 03fda13dbb add a note 
llvm-svn: 30921
 2006-10-12 22:01:26 +00:00
Evan Cheng a7956d2894 Doh. This wasn't causing problems by luck. 
llvm-svn: 30914
 2006-10-12 19:13:59 +00:00
Evan Cheng 694810c227 Some X86ISD::CMP were created with wrong ValueType's. 
llvm-svn: 30913
 2006-10-12 19:12:56 +00:00
Chris Lattner 8c9422c4b8 mark call adjustments as modifying the SP 
llvm-svn: 30911
 2006-10-12 18:00:26 +00:00
Chris Lattner 0e0ee36f45 adjcallstack up/down clobbers the sp 
llvm-svn: 30910
 2006-10-12 18:00:14 +00:00
Chris Lattner d376e9f4ac adjcallstackup/down clobbers the stack pointer 
llvm-svn: 30909
 2006-10-12 17:57:58 +00:00
Chris Lattner 7374bc0577 mark adjcallstack up/down as clobbering and using the SP 
llvm-svn: 30908
 2006-10-12 17:56:34 +00:00
Chris Lattner adcaf294d7 Move the Imp tblgen class from the X86 backend to common code. 
llvm-svn: 30907
 2006-10-12 17:49:27 +00:00
Chris Lattner b5cda3daa9 Mark ADJCALLSTACKUP/DOWN as clobbering ESP so that virtregmap will notice 
that it can't assume ESP is unmodified across the instrs.

llvm-svn: 30905
 2006-10-12 17:42:56 +00:00
Chris Lattner 40ec2bebf9 fix compilation failure of smg2000 
llvm-svn: 30900
 2006-10-12 03:55:48 +00:00
Chris Lattner d5fcfaa6da Fold "zero extending vector loads" now that evan added the chain manip stuff. 
This compiles both tests in X86/vec_ss_load_fold.ll into:

_test1:
        movss 4(%esp), %xmm0
        subss LCPI1_0, %xmm0
        mulss LCPI1_1, %xmm0
        minss LCPI1_2, %xmm0
        xorps %xmm1, %xmm1
        maxss %xmm1, %xmm0
        cvttss2si %xmm0, %eax
        andl $65535, %eax
        ret

instead of:

_test1:
        movss LCPI1_0, %xmm0
        movss 4(%esp), %xmm1
        subss %xmm0, %xmm1
        movss LCPI1_1, %xmm0
        mulss %xmm0, %xmm1
        movss LCPI1_2, %xmm0
        minss %xmm0, %xmm1
        xorps %xmm0, %xmm0
        maxss %xmm0, %xmm1
        cvttss2si %xmm1, %eax
        andl $65535, %eax
        ret

llvm-svn: 30894
 2006-10-11 22:09:58 +00:00
Evan Cheng 4090dc4703 ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands. 
llvm-svn: 30892
 2006-10-11 21:06:01 +00:00
Evan Cheng 577ef7694e Add properties to ComplexPattern. 
llvm-svn: 30891
 2006-10-11 21:03:53 +00:00
Andrew Lenharth fa8cbfd8e8 Reduce the amount of state in the lowering code and drop old pattern ISel functions 
llvm-svn: 30881
 2006-10-11 16:24:51 +00:00
Evan Cheng d35734bd1f Naming consistency. 
llvm-svn: 30878
 2006-10-11 07:10:22 +00:00
Chris Lattner 6487854b3f Use cute tblgen tricks to make zap handling more powerful. Specifically, 
when the dag combiner simplifies an and mask, notice this and allow those bits
to be missing from the zap mask.

This compiles Alpha/zapnot4.ll into:

        sll $16,3,$0
        zapnot $0,3,$0
        ret $31,($26),1

instead of:

        ldah $0,1($31)
        lda $0,-8($0)
        sll $16,3,$1
        and $1,$0,$0
        ret $31,($26),1

It would be *really* nice to replace the hunk of code in the
AlphaISelDAGToDAG.cpp file that matches (and (srl (x, C), c2) into
(SRL (ZAPNOTi)) with a similar pattern, but I've spent enough time poking
at alpha.  Make andrew will do this.

llvm-svn: 30875
 2006-10-11 05:13:56 +00:00
Andrew Lenharth a6bbf33cbf Jimptables working again on alpha. 
As a bonus, use the GOT node instead of the AlphaISD::GOT for internal stuff.

llvm-svn: 30873
 2006-10-11 04:29:42 +00:00
Chris Lattner 9f86f7c2ab Remove dead/redundant instructions. These are handled by ZAPNOTi 
llvm-svn: 30872
 2006-10-11 04:12:39 +00:00
Andrew Lenharth 4a57e2a6ed This entry is done. switched to the gcc way of doing things. 
llvm-svn: 30867
 2006-10-11 01:48:03 +00:00
Chris Lattner 3d74556d74 This has apparently been fixed 
llvm-svn: 30864
 2006-10-11 01:44:46 +00:00
Rafael Espindola 8429e1f6c3 uint <-> double conversion 
llvm-svn: 30862
 2006-10-10 20:38:57 +00:00
Rafael Espindola b5f1ff336a add fp sub 
llvm-svn: 30859
 2006-10-10 19:35:01 +00:00
Rafael Espindola 57d109fb08 add double <-> int conversion 
llvm-svn: 30858
 2006-10-10 18:55:14 +00:00
Rafael Espindola d1a4ea41c9 compare doubles 
llvm-svn: 30856
 2006-10-10 16:33:47 +00:00
Rafael Espindola d15c892433 initial support for fp compares. Unordered compares not implemented yet 
llvm-svn: 30854
 2006-10-10 12:56:00 +00:00
Evan Cheng 61b8b43bbe More isel time load folding checking for nodes that produce flag values. 
See comment in CanBeFoldedBy() for detailed explanation.

llvm-svn: 30851
 2006-10-10 01:46:56 +00:00
Evan Cheng 57ccb6d372 Don't go too crazy with these AddComplexity. Try matching shufps with load 
folding first.

llvm-svn: 30848
 2006-10-09 21:42:15 +00:00
Evan Cheng e646abb7b6 Don't convert to MOVLP if using shufps etc. may allow load folding. 
llvm-svn: 30847
 2006-10-09 21:39:25 +00:00
Evan Cheng e71fe34d75 Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
llvm-svn: 30844
 2006-10-09 20:57:25 +00:00
Rafael Espindola 9e29ec371a add float -> double and double -> float conversion 
llvm-svn: 30835
 2006-10-09 17:50:29 +00:00
Rafael Espindola 396b4a6b7b add ADDS and ADCS 
llvm-svn: 30830
 2006-10-09 17:18:28 +00:00
Rafael Espindola e4c3276afc expand ISD::SELECT 
llvm-svn: 30829
 2006-10-09 16:28:33 +00:00
Rafael Espindola c154dacb2f add a note 
llvm-svn: 30828
 2006-10-09 14:18:33 +00:00
Rafael Espindola 41730922bb expand ISD::EXTLOAD 
llvm-svn: 30827
 2006-10-09 14:13:40 +00:00
Rafael Espindola 78d6c2bf59 most ARM targets are little endian 
llvm-svn: 30826
 2006-10-09 14:12:15 +00:00
Chris Lattner 398195ebbe completely disable folding of loads into scalar sse instructions and provide 
a framework for doing it right.  This fixes
CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll.

Once X86DAGToDAGISel::SelectScalarSSELoad is implemented right, this task
will be done.

llvm-svn: 30817
 2006-10-07 21:55:32 +00:00
Chris Lattner 942009fee5 convert packed FP add/sub/mul/div to use a multiclass. 
llvm-svn: 30815
 2006-10-07 21:17:13 +00:00
Chris Lattner 4005f4e49c one multiclass now defines all 8 variants of binary-scalar-sse-fp operations. 
llvm-svn: 30814
 2006-10-07 20:55:57 +00:00
Chris Lattner 6eaee2c8e3 Switch ADD/MUL/DIV/SUB scalarsse fp ops to a multiclass 
llvm-svn: 30813
 2006-10-07 20:35:44 +00:00
Chris Lattner c8c6441821 Random acts of shrinkage 
llvm-svn: 30812
 2006-10-07 19:49:05 +00:00
Chris Lattner b5df7e554d Convert pand/por/pxor to use multiclass 
llvm-svn: 30811
 2006-10-07 19:37:30 +00:00
Chris Lattner 6138cba5f1 Convert some more instructions over to use a new multiclass. 
Fix a bug where the asmstring for PSUBQrm was wrong.

llvm-svn: 30810
 2006-10-07 19:34:33 +00:00
Chris Lattner 662ba43f08 Fix a bug where PADDQrm printed paddd instead of paddq. 
llvm-svn: 30809
 2006-10-07 19:15:46 +00:00
Chris Lattner 29c62a3c88 Add multiclass for SSE2 instructions that correspond to simple binops. 
llvm-svn: 30808
 2006-10-07 19:14:49 +00:00
Chris Lattner e0928d9d7b rename: 
PDI_binop_rm -> PDI_binop_rm_int
  PDI_binop_rmi -> PDI_binop_rmi_int

to make it clear that these are for use with intrinsics.

llvm-svn: 30807
 2006-10-07 19:02:31 +00:00