6f54a46133
Detect unaligned loads/stores that have been added for Mips64 support.
...
llvm-svn: 147234
2011-12-24 03:07:37 +00:00
79329ce425
Test case for r147232.
...
llvm-svn: 147233
2011-12-24 03:05:43 +00:00
695d113adc
If target ABI is N64, LEA should be daddiu.
...
llvm-svn: 147232
2011-12-24 02:59:27 +00:00
908d2ed14e
Move x86 specific bits of the COFF writer to lib/Target/X86.
...
llvm-svn: 147231
2011-12-24 02:14:02 +00:00
b120ea2b92
Define trivial destructor inline.
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llvm-svn: 147230
2011-12-24 01:53:13 +00:00
a2da8aa505
Make GetRelocType pure virtual.
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llvm-svn: 147229
2011-12-24 01:36:25 +00:00
d9d1de4f69
Fix typo "infinte".
...
llvm-svn: 147226
2011-12-23 23:49:25 +00:00
854c869c36
Move this test from date-name to feature-name, and port it to FileCheck.
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llvm-svn: 147223
2011-12-23 18:41:31 +00:00
5d44a4332a
When not destroying the source, the linker is not remapping the types. Added support
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to CloneFunctionInto to allow remapping for this case.
llvm-svn: 147217
2011-12-23 02:18:32 +00:00
6ea1b76d71
Use 'check_symbol_exists' instead of 'check_function_exists' for finding isatty. This change allows Xcode generated projects to have HAVE_ISATTY to be properly defined.
...
llvm-svn: 147215
2011-12-23 01:31:45 +00:00
0965585cb1
Experimental support for aligned NEON spills.
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ARM targets with NEON units have access to aligned vector loads and
stores that are potentially faster than unaligned operations.
Add support for spilling the callee-saved NEON registers to an aligned
stack area using 16-byte aligned NEON loads and store.
This feature is off by default, controlled by an -align-neon-spills
command line option.
llvm-svn: 147211
2011-12-23 00:36:18 +00:00
1a74de9504
Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>
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My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used. This
caused massive failures on the testsuite when compiling for Thumb1. While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.
llvm-svn: 147204
2011-12-22 23:39:48 +00:00
f3b1760496
TableGen: add a comment
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llvm-svn: 147199
2011-12-22 23:16:09 +00:00
345b7430a9
try to fix MSVC build
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llvm-svn: 147198
2011-12-22 23:08:39 +00:00
9e5b178ecc
drop unneeded config.h includes
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llvm-svn: 147197
2011-12-22 23:04:07 +00:00
54671a787c
Attempt #2 to fix mingw crossbuild. This time with more ugly hacks!
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llvm-svn: 147196
2011-12-22 22:50:44 +00:00
00bbedff03
Fix 80-column violations.
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llvm-svn: 147192
2011-12-22 22:35:21 +00:00
942b28759d
Make the -fvisibility-inlines-hidden check more thorough in a hopeless attempt to fix mingw cross-compiles.
...
llvm-svn: 147191
2011-12-22 22:25:26 +00:00
e61724aa00
Move all the dependencies on X86FixupKinds.h to a single method in preparation
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to moving it to lib/Target/X86.
llvm-svn: 147190
2011-12-22 22:21:47 +00:00
ea2319112f
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
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rdar://10558523
llvm-svn: 147189
2011-12-22 22:19:05 +00:00
268d2599e0
Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.
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Noticed by inspection; I don't have a testcase for this.
llvm-svn: 147188
2011-12-22 22:12:44 +00:00
f96715d7f0
Remove broken command to copy tblgen tool.
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tblgen has been renamed to llvm-tblgen so this command has been failing,
and it's no longer needed because llvm-tblgen is already installed by default.
llvm-svn: 147187
2011-12-22 22:12:40 +00:00
f70c862393
Some unittests for APInt rotates; patch by Cameron McInally.
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llvm-svn: 147186
2011-12-22 22:11:19 +00:00
c4d8d2f155
Tidy up. Use predicate function a bit more liberally.
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llvm-svn: 147184
2011-12-22 22:02:35 +00:00
d90b595599
Reenable building with -fvisibility-inlines-hidden.
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This was disabled years ago because of a bug in GCC 4.1, which is
on our "broken compilers" list for other reasons. Saving ~500k
on a clang binary (Release+Asserts) is well worth dropping support
for it.
We currently disable it for shared libraries (where it would bring
the biggest win) because clang is broken (PR11642).
IMPORTANT: If you're doing incremental builds you may get tons of
linker warnings. make clean will fix them.
llvm-svn: 147182
2011-12-22 21:41:32 +00:00
6ca42c5be3
Fix incorrect relocation generation. Patch by Kristof Beyls.
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Fixes PR11214.
llvm-svn: 147180
2011-12-22 21:36:43 +00:00
3ba90a1655
Add the actual code for r147175.
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llvm-svn: 147176
2011-12-22 21:10:46 +00:00
388769427d
Reinstate r146578; it doesn't appear to be the cause of some recent execution-
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time regressions. In general, it is beneficial to compile-time.
Original commit message:
Fix for bug #11429 : Wrong behaviour for switches. Small improvement for code
size heuristics.
llvm-svn: 147175
2011-12-22 21:06:36 +00:00
f0d25117c6
ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.
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The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.
Partial for: rdar://10558523
llvm-svn: 147170
2011-12-22 19:55:21 +00:00
b65dd04923
Remove some bogus comments.
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llvm-svn: 147169
2011-12-22 19:45:01 +00:00
a0a6d01d4d
fix typo
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llvm-svn: 147159
2011-12-22 19:20:51 +00:00
489ed5929e
ARM pre-UAL aliases. fcmp[sd].
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llvm-svn: 147158
2011-12-22 19:20:45 +00:00
250096233b
Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for reporting
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it. It does need some some tests...
llvm-svn: 147154
2011-12-22 18:38:06 +00:00
12ccf45bbb
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
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Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
llvm-svn: 147153
2011-12-22 18:04:04 +00:00
21488b8839
ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.
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llvm-svn: 147152
2011-12-22 17:37:00 +00:00
3794d82af5
Tidy up. Trailing whitespace.
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llvm-svn: 147151
2011-12-22 17:17:10 +00:00
62bffd8827
Nuke invalid comment from copy/paste.
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llvm-svn: 147150
2011-12-22 17:04:50 +00:00
f1fd6e394d
Give string constants generated by IRBuilder private linkage.
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Fixes PR11640.
llvm-svn: 147144
2011-12-22 14:22:14 +00:00
4977edd33d
Add configure support for kfreebsd and hurd. Patch by Sylvestre Ledru.
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Fixes pr11620.
llvm-svn: 147143
2011-12-22 14:01:18 +00:00
b024aa021d
Make the unreachable probability much much heavier. The previous
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probability wouldn't be considered "hot" in some weird loop structures
or other compounding probability patterns. This makes it much harder to
confuse, but isn't really a principled fix. I'd actually like it if we
could model a zero probability, as it would make this much easier to
reason about. Suggestions for how to do this better are welcome.
llvm-svn: 147142
2011-12-22 09:26:37 +00:00
29abd977de
Kill the monstrosity that was ELFObjectWriter.h.
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llvm-svn: 147136
2011-12-22 03:38:00 +00:00
34a68afc05
Misc cleanups.
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llvm-svn: 147135
2011-12-22 03:24:43 +00:00
2aae94fa70
Fix APInt::rotl and APInt::rotr so that they work correctly. Found while writing some code that tried to use them.
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llvm-svn: 147134
2011-12-22 03:15:35 +00:00
1dc45d8df4
Move the Mips only bits of the ELF writer to lib/Target/Mips.
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llvm-svn: 147133
2011-12-22 03:03:17 +00:00
84d00f11cd
Make the virtual methods in ARMELFObjectWriter public.
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llvm-svn: 147132
2011-12-22 02:58:12 +00:00
1b7e2baf47
Speculatively revert r146578 to determine if it is the cause of a number of
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performance regressions (both execution-time and compile-time) on our
nightly testers.
Original commit message:
Fix for bug #11429 : Wrong behaviour for switches. Small improvement for code
size heuristics.
llvm-svn: 147131
2011-12-22 02:40:57 +00:00
cc369ac0a2
Move the MBlaze ELF writer bits to lib/Target/MBlaze.
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llvm-svn: 147129
2011-12-22 02:28:24 +00:00
1c3b1efa58
Hoisted some loop invariant smallvector lookups out of a MachineLICM loop
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llvm-svn: 147127
2011-12-22 02:13:25 +00:00
428b9ee036
Fix cmake.
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llvm-svn: 147126
2011-12-22 02:06:17 +00:00
1eed5b51e8
Changed MachineLICM to use a worklist list MachineCSE instead of recursion.
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Fixes <rdar://problem/10584116>
llvm-svn: 147125
2011-12-22 02:05:40 +00:00
38a400df3b
Move PPC bits to lib/Target/PowerPC.
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llvm-svn: 147124
2011-12-22 01:57:09 +00:00
2da9777cef
Hopefully fix the cmake build.
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llvm-svn: 147121
2011-12-22 01:11:01 +00:00
4449b21294
Fix name in comments.
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llvm-svn: 147119
2011-12-22 01:06:53 +00:00
e2eed9649e
Local dynamic TLS model for direct object output. Create the correct TLS MIPS
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ELF relocations.
Patch by Jack Carter.
llvm-svn: 147118
2011-12-22 01:05:17 +00:00
32a756b7ce
Unbreak cmake build after r147115.
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llvm-svn: 147117
2011-12-22 01:03:35 +00:00
a0124055b1
Move the ARM specific parts of the ELF writer to Target/ARM.
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llvm-svn: 147115
2011-12-22 00:37:50 +00:00
6faa1533fb
getEFlags is const.
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llvm-svn: 147114
2011-12-22 00:21:50 +00:00
fc8a4bc969
Fixed typo.
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llvm-svn: 147113
2011-12-22 00:12:51 +00:00
2b80dad572
ARM NEON mnemonic aliase for vrecpeq.
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llvm-svn: 147109
2011-12-21 23:52:37 +00:00
7869d8c01e
ARM VFP optional data type on VMOV GPR<-->SPR.
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llvm-svn: 147104
2011-12-21 23:24:15 +00:00
260b4b336a
ARM NEON optional data type on VSWP instructions.
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llvm-svn: 147103
2011-12-21 23:09:28 +00:00
a50e24fcb3
ARM NEON mnemonic aliases for vzipq and vswpq.
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llvm-svn: 147102
2011-12-21 23:04:33 +00:00
9061616f9e
Revert patch from 147090. There is not point to make code less readable if we
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don't get any serious benefit there.
llvm-svn: 147101
2011-12-21 23:02:08 +00:00
1152cc0cad
ARM asm parser should be more lenient w/ .thumb_func directive.
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Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.
rdar://10611140
llvm-svn: 147100
2011-12-21 22:30:16 +00:00
51c81685a8
Fix a copy+pasto. No testcase, because the symptoms of dereferencing
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an invalid iterator aren't reproducible. rdar://10614085.
llvm-svn: 147098
2011-12-21 21:43:50 +00:00
8c59bbc1ed
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
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Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
llvm-svn: 147096
2011-12-21 21:04:19 +00:00
3172488cc0
Fix 80-column violations.
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llvm-svn: 147095
2011-12-21 20:59:09 +00:00
b3ef713e44
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
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These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
llvm-svn: 147094
2011-12-21 20:54:00 +00:00
c186d07bbe
Continue counting intrinsics as instructions (except when they aren't, such as
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debug info) and for being vector operations. Fixes regression from r147037.
llvm-svn: 147093
2011-12-21 20:26:03 +00:00
281e2747e0
Fix typo and spacing, no functionality change.
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llvm-svn: 147092
2011-12-21 20:21:55 +00:00
df5133455f
- Change a few operator[] to lookup which is cheaper.
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- Add some constantness.
llvm-svn: 147090
2011-12-21 20:18:54 +00:00
e49fbd0755
Oops - LiveIntervalUnion.cpp file does use std::find. Moving STL header include to LiveIntervalUnion.cpp file.
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llvm-svn: 147089
2011-12-21 20:16:11 +00:00
93176d72e7
Remove disused STL header include.
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llvm-svn: 147088
2011-12-21 20:12:54 +00:00
f61ff34252
Switch from WriteEFlags to getEFlags in preparation for moving it
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to Target/.
llvm-svn: 147087
2011-12-21 20:09:46 +00:00
3588a43e3a
Move common code into an MRI function.
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llvm-svn: 147071
2011-12-21 19:50:05 +00:00
c80a264386
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
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llvm-svn: 147069
2011-12-21 19:40:55 +00:00
3ede414127
No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't
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necessary. Please chime in if I'm mistaken.
llvm-svn: 147065
2011-12-21 19:14:52 +00:00
7248bda595
Fix a couple of copy-n-paste bugs. Noticed by George Russell!
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llvm-svn: 147064
2011-12-21 18:56:22 +00:00
25eb0ac418
Changes the JSON parser to use the SourceMgr.
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Diagnostics are now emitted via the SourceMgr and we use MemoryBuffer
for buffer management. Switched the code to make use of the trailing
'0' that MemoryBuffer guarantees where it makes sense.
llvm-svn: 147063
2011-12-21 18:16:39 +00:00
b264d33854
Move the X86 specific bits of the ELF writer to the Target/X86 directory.
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Other targets will follow shortly.
llvm-svn: 147060
2011-12-21 17:30:17 +00:00
1ad4095d6b
Reduce the exposure of Triple::OSType in the ELF object writer. This will
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avoid including ADT/Triple.h in many places when the target specific bits are
moved.
llvm-svn: 147059
2011-12-21 17:00:36 +00:00
46f0c15208
Add const.
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llvm-svn: 147054
2011-12-21 14:48:04 +00:00
9e252bf038
Small refactoring so that RelocNeedsGOT can stay in the target independent
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side when the target specific bits are moved to the Target directory.
llvm-svn: 147053
2011-12-21 14:26:29 +00:00
b761ff3e24
Removes unused field TheError from LLLexer.
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llvm-svn: 147049
2011-12-21 10:02:45 +00:00
b8b1b4c1de
Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored.
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llvm-svn: 147046
2011-12-21 08:06:52 +00:00
f30188418b
Fix typo in a couple comments
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llvm-svn: 147045
2011-12-21 06:30:53 +00:00
da22fc6a1d
A call to a function marked 'noinline' is not an inline candidate. The sole
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call site of an intrinsic is also not an inline candidate. While here, make it
more obvious that this code ignores all intrinsics. Noticed by inspection!
llvm-svn: 147037
2011-12-21 06:06:30 +00:00
b4039f633c
Make some intrinsics safe to speculatively execute.
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llvm-svn: 147036
2011-12-21 05:52:02 +00:00
dc8a1aaea6
Fix a couple of copy-n-paste bugs. Noticed by George Russell.
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llvm-svn: 147032
2011-12-21 03:04:10 +00:00
7de7ab83fa
ARM assembly parsing allows constant expressions for lane indices.
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llvm-svn: 147028
2011-12-21 01:19:23 +00:00
afbe7520a6
Regenerate.
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llvm-svn: 147027
2011-12-21 00:52:44 +00:00
c5af54ec89
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
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llvm-svn: 147025
2011-12-21 00:38:54 +00:00
964c891e61
Fix bug in zero-store peephole pattern reported in pr11615.
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The patch and test case were originally written by Mans Rullgard.
llvm-svn: 147024
2011-12-21 00:31:10 +00:00
1d8efaba7e
Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
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case for DCLO and DCLZ.
llvm-svn: 147022
2011-12-21 00:20:27 +00:00
410ce9cb44
Expand 64-bit CTPOP and CTTZ.
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llvm-svn: 147021
2011-12-21 00:14:05 +00:00
91c052c4d8
Expand 64-bit atomic load and store.
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llvm-svn: 147019
2011-12-21 00:02:58 +00:00
bd95275f7a
Test case for r147017.
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llvm-svn: 147018
2011-12-20 23:58:36 +00:00
4706ac9715
Add definition of DSBH (Double Swap Bytes within Halfwords) and
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DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.
llvm-svn: 147017
2011-12-20 23:56:43 +00:00
43c1ff4db3
Add definition of WSBH (Word Swap Bytes within Halfwords), which is an
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instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
WSBW is removed since it is not an instruction the current architectures
support.
llvm-svn: 147015
2011-12-20 23:47:44 +00:00
79aed157e7
64-bit uint-fp conversion nodes are expanded.
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llvm-svn: 147014
2011-12-20 23:40:56 +00:00
2bb8d068f5
Enable custom lowering DYNAMIC_STACKALLOC nodes.
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llvm-svn: 147013
2011-12-20 23:35:46 +00:00
8e2c02e2d6
Set the correct stack pointer register that should be saved or restored.
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llvm-svn: 147012
2011-12-20 23:28:36 +00:00
6ac54afeba
Enable and fix a test.
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llvm-svn: 147011
2011-12-20 23:20:00 +00:00
eaf9b7629a
Fix a nasty bug in the type remapping stuff that I added that is breaking kc++ on
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the build bot in some cases. The basic issue happens when a source module contains
both a "%foo" type and a "%foo.42" type. It will see the later one, check to see if
the destination module contains a "%foo" type, and it will return true... because
both the source and destination modules are in the same LLVMContext. We don't want
to map source types to other source types, so don't do the remapping if the mapped
type came from the source module.
Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is
pretty great that way.
llvm-svn: 147010
2011-12-20 23:14:57 +00:00
cd22e4a81e
ARM .req register name aliases are case insensitive, just like regnames.
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llvm-svn: 147009
2011-12-20 23:11:00 +00:00
cb2a85bc22
Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates
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nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.
llvm-svn: 147008
2011-12-20 23:10:57 +00:00
2c8d1734f8
Fix indentation.
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llvm-svn: 147007
2011-12-20 22:58:01 +00:00
cf10f08825
64-bit data directive.
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llvm-svn: 147005
2011-12-20 22:52:19 +00:00
494fdf1499
32-to-64-bit sext_inreg pattern.
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llvm-svn: 147004
2011-12-20 22:40:40 +00:00
8756816e6f
Add 64-bit extload patterns.
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llvm-svn: 147003
2011-12-20 22:36:08 +00:00
0cee2045c9
Add patterns for matching extloads with 64-bit address. The patterns are enabled
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only when the target ABI is N64.
llvm-svn: 147001
2011-12-20 22:33:53 +00:00
4eda145c7f
Move comment to appropriate place.
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llvm-svn: 147000
2011-12-20 22:26:38 +00:00
dac1d48d8d
Add code in MipsDAGToDAGISel for selecting constant +0.0.
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MIPS64 can generate constant +0.0 with a single DMTC1 instruction.
llvm-svn: 146999
2011-12-20 22:25:50 +00:00
b95c102c2f
Heed spill slot alignment on ARM.
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Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
llvm-svn: 146997
2011-12-20 22:15:04 +00:00
14468c6cb6
Revert part of r146995 that was accidentally commmitted.
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llvm-svn: 146996
2011-12-20 22:09:36 +00:00
4e210691c0
32-to-64-bit sign extension pattern.
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llvm-svn: 146995
2011-12-20 22:06:20 +00:00
9b9bd1cc15
Add a pattern for matching zero-store with 64-bit address. The pattern is enabled
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only when the target ABI is N64.
llvm-svn: 146992
2011-12-20 21:50:49 +00:00
2c59052984
ARM assembly parsing and encoding for VST2 single-element, double spaced.
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llvm-svn: 146990
2011-12-20 20:46:29 +00:00
6cee53d06e
Fix assert condition.
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llvm-svn: 146987
2011-12-20 20:23:40 +00:00
96f8c551e3
Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.
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llvm-svn: 146986
2011-12-20 20:03:10 +00:00
c8ebeff9a1
ARM enable a few more tests.
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llvm-svn: 146985
2011-12-20 20:03:00 +00:00
9224540efc
Add support to add named metadata operand.
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Patch by Andrew Wilkins!
llvm-svn: 146984
2011-12-20 19:29:36 +00:00
75e2ab5db2
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
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llvm-svn: 146983
2011-12-20 19:21:26 +00:00
68132d8093
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
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llvm-svn: 146981
2011-12-20 18:26:50 +00:00
135d244b56
First steps in ARM AsmParser support for .eabi_attribute and .arch
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(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
llvm-svn: 146977
2011-12-20 17:38:12 +00:00
ec7e6e0946
This is the second fix related to VZEXT_MOVL node.
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The failure that I see in the current version is:
LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
0x18b9870: v4i64 = undef [ID=4]
0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9970: i32 = Constant<0> [ID=3]
0x18b9170: v2i64 = undef [ORD=1] [ID=1]
0x18b9570: i32 = Constant<2> [ID=5]
llvm-svn: 146975
2011-12-20 13:34:28 +00:00
24680c24d8
Begin teaching the X86 target how to efficiently codegen patterns that
...
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.
The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.
llvm-svn: 146974
2011-12-20 11:19:37 +00:00
fe198ced31
Fixes a potential compilation error.
...
Pulling the template implementation into the header to guarantee
that it's visible to all possible instantiations.
llvm-svn: 146973
2011-12-20 11:04:23 +00:00
47151c37b6
Pulls the implementation of skip() into JSONParser.
...
This is the first step towards migrating more of the parser
implementation into the parser class.
llvm-svn: 146971
2011-12-20 10:42:52 +00:00
860d978ef6
Fixing option for JSON benchmark broken since the change to size_t.
...
llvm-svn: 146970
2011-12-20 10:34:29 +00:00
f8d73192cc
Addressing style issues in JSON parser.
...
llvm-svn: 146968
2011-12-20 09:26:26 +00:00
e805b16e3d
Fix up the CMake build for the new files added in r146960, they're
...
likely to stay either way that discussion ends up resolving itself.
llvm-svn: 146966
2011-12-20 08:42:11 +00:00
5ca16b1030
Revert pragma clang suppressions that confuse GCC. (I'll worry about how to suppress/fix these problems properly when we figure out how to keep LLVM -Wweak-vtables clean)
...
llvm-svn: 146965
2011-12-20 08:22:49 +00:00
1a0ae42d14
Add a few lines to the release notes:
...
1. pointer-vector
2. type legalizer changes and vector-select
3. X86 ISA changes.
llvm-svn: 146964
2011-12-20 08:02:50 +00:00
a379b18173
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
...
llvm-svn: 146960
2011-12-20 02:50:00 +00:00
a34a8c45b4
Unit test for r146950: LSR postinc expansion, PR11571.
...
llvm-svn: 146951
2011-12-20 01:43:20 +00:00
b9aa26f8ea
LSR: Fix another corner case in expansion of postinc users.
...
Fixes PR11571: Instruction does not dominate all uses
llvm-svn: 146950
2011-12-20 01:42:24 +00:00
75f12cc3fe
Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.
...
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers. But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore. Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early. This also more accurately reflects
when the registers are clobbered.
llvm-svn: 146949
2011-12-20 01:29:27 +00:00
00723591b8
fix typo
...
llvm-svn: 146940
2011-12-20 01:11:37 +00:00
948ec427fa
Add a line to ReleaseNotes for half float.
...
llvm-svn: 146939
2011-12-20 01:10:56 +00:00
e2ca9e5b5f
ARM assembly shifts by zero should be plain 'mov' instructions.
...
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
9eb3f00406
Now that PR11464 is fixed, reapply the patch to fix PR11464,
...
merging types by name when we can. We still don't guarantee type name linkage
but we do it when obviously the right thing to do. This makes LTO type names
easier to read, for example.
llvm-svn: 146932
2011-12-20 00:12:26 +00:00
5e3bd9727a
fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all.
...
llvm-svn: 146929
2011-12-20 00:03:52 +00:00
55619074d8
add a method to improve compatibility with SmallVector.
...
llvm-svn: 146928
2011-12-20 00:03:41 +00:00
94580ab375
Add basic generic CodeGen support for half.
...
llvm-svn: 146927
2011-12-20 00:02:33 +00:00
045b6c71a6
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
...
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"
rdar://10603913
llvm-svn: 146925
2011-12-19 23:51:07 +00:00
3bfaefe9e7
Move tests to FileCheck.
...
llvm-svn: 146923
2011-12-19 23:26:44 +00:00
8648c10184
ARM assembly parsing and encoding support for LDRD(label).
...
rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
4266a79351
Add a if-conversion optimization that allows 'true' side of a diamond to be
...
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://8951196
llvm-svn: 146914
2011-12-19 22:01:30 +00:00
6dbc17dffe
Add "using" to silence warnings.
...
llvm-svn: 146913
2011-12-19 21:53:12 +00:00
Akira Hatanaka