a340febe52
Add immediate forms of in/out. Use let to shorten lines
...
llvm-svn: 12895
2004-04-13 17:19:31 +00:00
a24f986333
Fix issues that the local allocator has dealing with instructions that implicitly use ST(0)
...
llvm-svn: 12855
2004-04-12 03:02:48 +00:00
2e2b0ceab9
No really, fix printing for LLC. I gotta get a way for CVS to whine at me if
...
I have unsaved emacs buffers, geeze...
llvm-svn: 12854
2004-04-12 01:52:04 +00:00
ba1038e0f3
Correct printing for LLC and the encoding for the JIT
...
llvm-svn: 12853
2004-04-12 01:50:04 +00:00
6c84d4ca44
Add two new instructions
...
llvm-svn: 12850
2004-04-12 01:38:55 +00:00
b6e0b58fbc
Add some new instructions
...
llvm-svn: 12838
2004-04-11 20:24:15 +00:00
c28c3b625f
Changes recommended by Chris:
...
InstSelectSimple.cpp:
Change the checks for proper I/O port address size into an exit() instead
of an assertion. Assertions aren't used in Release builds, and handling
this error should be graceful (not that this counts as graceful, but it's
more graceful).
Modified the generation of the IN/OUT instructions to have 0 arguments.
X86InstrInfo.td:
Added the OpSize attribute to the 16 bit IN and OUT instructions.
llvm-svn: 12786
2004-04-08 22:39:13 +00:00
10db062d41
Added the llvm.readport and llvm.writeport intrinsics for x86. These do
...
I/O port instructions on x86. The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output. This required adjustment to some
methods so that a leading comma would or would not be printed.
llvm-svn: 12782
2004-04-08 20:31:47 +00:00
ba33ae5831
Fix incorrect encoding of some ADC and SBB instuctions
...
llvm-svn: 12710
2004-04-06 19:20:32 +00:00
9366f0347d
The sbb instructions really ARE sbb's, not adc's
...
llvm-svn: 12682
2004-04-06 02:02:11 +00:00
fe66caa9a0
Fix type in comments
...
llvm-svn: 12611
2004-04-02 16:02:50 +00:00
d186ed02e4
Add more ADC and SBB variants
...
llvm-svn: 12607
2004-04-02 07:11:10 +00:00
9fe1646804
Add FP conditional move instructions, which annoyingly have special properties
...
that require the asmwriter to be extended (printing implicit uses before the
explicit operands)
llvm-svn: 12574
2004-03-31 22:02:13 +00:00
1563983d81
Fix some serious bugs in the cmov descriptions, which didn't cause a problem because
...
we never generated them
Make indentation a bit more consistent
llvm-svn: 12549
2004-03-30 20:18:02 +00:00
804dc659b6
Add LAHF instruction
...
llvm-svn: 12424
2004-03-15 17:20:14 +00:00
9884bda541
Add support for a wider range of CMOV instructions.
...
llvm-svn: 12336
2004-03-12 17:59:56 +00:00
8a3f2f3600
Differentiate between extended precision floats (80-bit) and double precision floats (64-bit)
...
llvm-svn: 12254
2004-03-09 03:37:54 +00:00
d6f62ba55b
Add memory operand version of conditional move.
...
llvm-svn: 12190
2004-03-07 03:19:11 +00:00
0824ffc697
Use correct template for SHLD and SHRD instructions so that the memory
...
operand size is correctly specified.
llvm-svn: 11997
2004-02-29 09:19:40 +00:00
ea81b79a97
A big X86 instruction rename. The instructions are renamed to make
...
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:
ADD8rr -> add, 8-bit register, 8-bit register
IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate
IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate
MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
llvm-svn: 11995
2004-02-29 08:50:03 +00:00
876f6f96d0
Use correct template for ADC instruction with memory operands.
...
llvm-svn: 11974
2004-02-29 02:18:17 +00:00
fa63580517
SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them
...
to denote this fact.
llvm-svn: 11972
2004-02-28 23:46:44 +00:00
4953ae085a
Floating point loads/stores act on memory operands. Rename them to
...
denote this fact.
llvm-svn: 11971
2004-02-28 23:42:35 +00:00
c6948fa762
Rename instruction templates to be easier to the human eye to
...
parse. The name is now I (operand size)*. For example:
Im32 -> instruction with 32-bit memory operands.
Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
operands.
llvm-svn: 11970
2004-02-28 23:09:03 +00:00
194939086d
Each instruction now has both an ImmType and a MemType. This describes
...
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).
llvm-svn: 11967
2004-02-28 22:02:05 +00:00
2debead504
Do not generate instructions with mismatched memory/immediate sized
...
operands. The X86 backend doesn't handle them properly right now.
llvm-svn: 11944
2004-02-28 06:01:43 +00:00
24b3d0bdae
Further comment updates.
...
llvm-svn: 11933
2004-02-28 03:20:31 +00:00
f87966b8c4
Update comments.
...
llvm-svn: 11932
2004-02-28 03:12:31 +00:00
2dbc79df84
My previous commit broke the jit. The shift instructions always take
...
an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.
A bug still exists:
def SHLDmri32 : I2A8 <"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8
The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.
llvm-svn: 11931
2004-02-28 02:56:26 +00:00
b10b04c5ec
Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of
...
instructions.
llvm-svn: 11923
2004-02-27 19:46:30 +00:00
75ed0f67bf
Fix encoding of ADD and SUB family of instructions. Also rearrange
...
them so that they are consistent with AND, XOR, etc...
llvm-svn: 11922
2004-02-27 18:57:00 +00:00
58270fcf1f
Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}.
...
llvm-svn: 11921
2004-02-27 18:55:12 +00:00
9476b7cbe5
Add memory operand folding support for the SETcc family of
...
instructions.
llvm-svn: 11907
2004-02-27 16:13:37 +00:00
8d99063b38
Add memory operand folding support for SHLD and SHRD instructions.
...
llvm-svn: 11905
2004-02-27 15:03:18 +00:00
3537404299
Add memory operand folding support for SHL, SHR and SAR, SHLD instructions.
...
llvm-svn: 11903
2004-02-27 09:28:43 +00:00
f020dfb43c
Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them
...
consistent with the rest and also pepare for the addition of their
memory operand variants.
llvm-svn: 11902
2004-02-27 06:57:05 +00:00
378157c3d7
Add a new cmove instruction
...
llvm-svn: 11722
2004-02-23 01:16:05 +00:00
6401b22fc2
Fix argument size for MOVSX and MOVZX instructions.
...
llvm-svn: 11576
2004-02-18 16:20:40 +00:00
47ea17a852
These store to memory too.
...
llvm-svn: 11558
2004-02-17 17:53:48 +00:00
49794be442
These store to memory, not read from it.
...
llvm-svn: 11556
2004-02-17 17:46:50 +00:00
546513ccfd
Add TEST and XCHG memory operand support.
...
llvm-svn: 11550
2004-02-17 15:48:42 +00:00
f08064b714
Add OR and XOR memory operand support.
...
llvm-svn: 11549
2004-02-17 15:33:14 +00:00
e5585328d8
Add memory operand folding support for MUL, DIV, IDIV, NEG, NOT,
...
MOVSX, and MOVZX.
llvm-svn: 11546
2004-02-17 09:14:23 +00:00
574c7c9ce9
Add CMP{rm,mr,mi}{8,16,32}, INCm{8,16,32} and DECm{8,16,32} instructions.
...
llvm-svn: 11544
2004-02-17 08:49:00 +00:00
d5ce14ddd1
Add SUB{rm,mr,mi}{8,16,32} instructions.
...
llvm-svn: 11543
2004-02-17 08:17:40 +00:00
b591e5de31
Add support for ADC{rm.mr}32 and SBB{rm,mr}32.
...
llvm-svn: 11540
2004-02-17 08:06:31 +00:00
3abcdf3b90
Fix the mneumonics for the mov instructions to have the source and destination
...
order in the correct sense!! Arg!
llvm-svn: 11530
2004-02-17 06:28:19 +00:00
ebd90733b0
Fix the last crimes against nature that used the 'ir' ordering to use the
...
'ri' ordering instead... no it's not possible to store a register into an
immediate!
llvm-svn: 11529
2004-02-17 06:24:02 +00:00
288e043e1b
Rename MOVi[mr] instructions to MOV[rm]i
...
llvm-svn: 11527
2004-02-17 06:16:44 +00:00
c9586411cf
Add mem forms of AND instructions
...
llvm-svn: 11521
2004-02-17 05:25:50 +00:00
Chris Lattner