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366 Commits

Author SHA1 Message Date
Chris Lattner fd47c79774 add a missing type cast. 
llvm-svn: 96574
 2010-02-18 06:33:42 +00:00
David Greene 9641d06809 Add support for emitting non-temporal stores for DAGs marked 
non-temporal.  Fix from r96241 for botched encoding of MOVNTDQ.

Add documentation for !nontemporal metadata.

Add a simpler movnt testcase.

llvm-svn: 96386
 2010-02-16 20:50:18 +00:00
Chris Lattner bcbaaba532 revert r96241. It breaks two regression tests, isn't documented, 
and the testcase needs improvement.

llvm-svn: 96265
 2010-02-15 20:53:01 +00:00
David Greene 63cedef74b Add support for emitting non-temporal stores for DAGs marked 
non-temporal.

llvm-svn: 96241
 2010-02-15 17:02:56 +00:00
Chris Lattner 064e926362 Remove special cases for [LM]FENCE, MONITOR and MWAIT from 
encoder and decoder by using new MRM_ forms.

llvm-svn: 96048
 2010-02-12 23:54:57 +00:00
Nate Begeman c780af6471 Add a missing pattern for movhps so that we get: 
movq	(%ecx,%edx,2), %xmm2
movhps	(%ecx,%eax,2), %xmm2

rather than:

movq     (%eax, %edx, 2), %xmm2		
movq     (%eax, %ebx, 2), %xmm3		
movlhps  %xmm3, %xmm2			

Testcase forthcoming.

llvm-svn: 95948
 2010-02-12 01:10:45 +00:00
Kevin Enderby a7c1d6cfd1 Fix the encoding of the movntdqa X86 instruction. It was missing the 0x66 
prefix which is part of the opcode encoding.

llvm-svn: 95729
 2010-02-10 00:10:31 +00:00
Chris Lattner 86bd194234 really kill off the last MRMInitReg inst, remove logic from encoder. 
llvm-svn: 95437
 2010-02-05 21:34:18 +00:00
Chris Lattner e96d534ce0 lower the last of the MRMInitReg instructions in MCInstLower. 
llvm-svn: 95435
 2010-02-05 21:30:49 +00:00
David Greene 206351a1ff Implement a feature (-vector-unaligned-mem) to allow targets to 
ignore alignment requirements for SIMD memory operands.  This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.

llvm-svn: 93151
 2010-01-11 16:29:42 +00:00
Evan Cheng 71d7eaa87e Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. 
llvm-svn: 91910
 2009-12-22 17:47:23 +00:00
Evan Cheng 4cf30b72bf On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0

llvm-svn: 91672
 2009-12-18 07:40:29 +00:00
Sean Callanan 04d8cb74f3 Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638
 2009-12-18 00:01:26 +00:00
Evan Cheng 493b882f80 Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g. 
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>

iff ptr is 16-byte aligned (or can be made into 16-byte aligned).

llvm-svn: 90984
 2009-12-09 21:00:30 +00:00
Sean Callanan c1f532e930 Recommitting PALIGNR shift width fixes. 
Thanks to Daniel Dunbar for fixing clang intrinsics:
  http://llvm.org/viewvc/llvm-project?view=rev&revision=89499

llvm-svn: 89500
 2009-11-20 22:28:42 +00:00
Sean Callanan 19d92728d0 Reverting PALIGNR fix until I figure out how this 
broke the Clang testsuite.

llvm-svn: 89495
 2009-11-20 22:09:28 +00:00
Sean Callanan fbed130173 Fixed PALIGNR to take 8-bit rotations in all cases. 
Also fixed the corresponding testcase, and the PALIGNR
  intrinsic (tested for correctness with llvm-gcc).

llvm-svn: 89491
 2009-11-20 21:40:28 +00:00
Evan Cheng 5392cc9d14 Re-apply 89011. It's not to be blamed. 
llvm-svn: 89081
 2009-11-17 09:51:18 +00:00
Evan Cheng 05938e819b Revert 89011. Buildbot thinks it might be breaking stuff. 
llvm-svn: 89076
 2009-11-17 09:20:28 +00:00
Evan Cheng ce28f6f478 A few more instructions that should be marked re-materializable. 
llvm-svn: 89011
 2009-11-17 00:23:22 +00:00
Evan Cheng f25ef4ffb0 - Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots. 
- Mark MOVUPSrm re-materializable.

llvm-svn: 88974
 2009-11-16 21:56:03 +00:00
Nate Begeman 3a313df69b x86 vector shuffle cleanup/fixes: 
1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect.  The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.

llvm-svn: 86415
 2009-11-07 23:17:15 +00:00
Eric Christopher bd05185ef1 Fix a couple of shuffle patterns to use movhlps instead 
of movhps as the constraint.  Changes optimizations so
update testcases as appropriate as well.

llvm-svn: 86360
 2009-11-07 08:45:53 +00:00
Dan Gohman 453d64c9f5 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Evan Cheng f64db3e1d0 X86 palignr intrinsics immediate field is in bits. ISel must transform it into bytes. 
llvm-svn: 85379
 2009-10-28 06:30:34 +00:00
Nate Begeman 18df82a20c Add support for matching shuffle patterns with palignr. 
llvm-svn: 84459
 2009-10-19 02:17:23 +00:00
Dan Gohman 69499b13fd Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool 
loads in order to reduce register pressure.

llvm-svn: 82470
 2009-09-21 18:30:38 +00:00
Sean Callanan e739ac8900 Added a variety of floating-point and SSE instructions. 
All of these do not have patterns (they're for the
disassembler).

Many of the floating-point instructions will probably
be rolled into definitions that have patterns, and may
eventually be superseded by mdefs.  So I put them
together and left a comment.

llvm-svn: 81979
 2009-09-16 01:13:52 +00:00
Sean Callanan 46bb77f2cf Fixed PCMPESTRM128 to have opcode 0x60 instead of 0x62, as specified by the 
Intel documentation.

llvm-svn: 79554
 2009-08-20 18:24:27 +00:00
Eric Christopher 9fe912de5f Implement sse4.2 string/text processing instructions: 
Add patterns and instruction encoding information.
Add custom lowering to deal with hardwired return register of
uncertain type (xmm0).

llvm-svn: 79377
 2009-08-18 22:50:32 +00:00
Daniel Dunbar c4f8ea4ccb Add 'isCodeGenOnly' bit to Instruction .td records. 
- Used to mark fake instructions which don't correspond to an actual machine
   instruction (or are duplicates of a real instruction). This is to be used for
   "special cases" in the .td files, which should be ignored by things like the
   assembler and disassembler. We still need a good solution to handle pervasive
   duplication, like with the Int_ instructions.

 - Set the bit on fake "mov 0" style instructions, which allows turning an
   assembler matcher warning into a hard error.

 - -2 FIXMEs.

llvm-svn: 78731
 2009-08-11 22:17:52 +00:00
Eric Christopher 458c91732c Fix up whitespace, remove commented out code. 
llvm-svn: 78600
 2009-08-10 21:48:58 +00:00
Daniel Dunbar 17410a4b92 llvm-mc/AsmMatcher: Change assembler parser match classes to their own record 
structure.

llvm-svn: 78581
 2009-08-10 18:41:10 +00:00
Daniel Dunbar 447c4ab91d Extend comment on ParserMatchClass .td field, and add some missing 
classes for X86.

llvm-svn: 78524
 2009-08-09 06:00:04 +00:00
Eric Christopher 7dfa9f2e56 Add crc32 instruction and intrinsics. Add a new class of prefix 
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.

New test.

llvm-svn: 78508
 2009-08-08 21:55:08 +00:00
Eric Christopher 45d7185117 Whitespace and 80-col cleanup. 
llvm-svn: 77718
 2009-07-31 20:07:27 +00:00
Dan Gohman 49a6f16b7c Add a new register class to describe operands that can't be SP, 
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.

llvm-svn: 77565
 2009-07-30 01:56:29 +00:00
Eric Christopher f7802a33ce Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower 
to ptest instruction plus setcc. Revamp ptest instruction. Add test.

llvm-svn: 77407
 2009-07-29 00:28:05 +00:00
Eric Christopher f37ea3ad75 Update insertps handling based on feedback. Move to a v4f32 style 
to support vector arguments and scalar arguments correctly. Update
lowering and fix comment to refer to pinsr* instead of insertps.

llvm-svn: 76921
 2009-07-24 00:33:09 +00:00
Eric Christopher b1b77ca862 Support insertps via the intrinsic and add a couple of simple 
testcases to make sure it's being generated.

llvm-svn: 76843
 2009-07-23 02:22:41 +00:00
Eli Friedman 2fc939c809 Fix for PR2484: add an SSE1 pattern for a shuffle we normally prefer to 
handle with an SSE2 instruction.

llvm-svn: 73760
 2009-06-19 07:00:55 +00:00
Eli Friedman 868bd6ab52 Fix an obvious typo. 
llvm-svn: 72987
 2009-06-06 05:55:37 +00:00
Bill Wendling 2e09bd3d34 The MONITOR and MWAIT instructions have insufficient information for 
decoding. Essentially, they both map to the same column in the "opcode
extensions for one- and two-byte opcodes" table in the x86 manual. The RawFrm
complicates decoding this.

Instead, use opcode 0x01, prefix 0x01, and form MRM1r. Then have the code
emitter special case these, a la [SML]FENCE.

llvm-svn: 72556
 2009-05-28 23:40:46 +00:00
Evan Cheng cc3ae1f2ff Fix MOVMSKPDrr encoding. 
llvm-svn: 72535
 2009-05-28 18:55:28 +00:00
Evan Cheng 60618fe4ac Fix PSIGND encoding bug. Patch by Sean Callanan. 
llvm-svn: 72534
 2009-05-28 18:48:53 +00:00
Bill Wendling 0feb0e6071 "The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but 
the Intel manual (screenshot) says it should be 0b11110110 (f6).  The existing
encoding causes a disassembly conflict with MMX_PAVGBrm, which really should be
0f e0."

Patch by Sean Callanan!

llvm-svn: 72508
 2009-05-28 02:04:00 +00:00
Evan Cheng 4db1631a43 Fix sfence jit encoding. Patch by Sean Callanan. 
llvm-svn: 72488
 2009-05-27 18:38:01 +00:00
Evan Cheng b41de47856 80 col violations. 
llvm-svn: 71582
 2009-05-12 20:17:52 +00:00
Nate Begeman 7e6e352735 Fix infinite recursion in the C++ code which handles movddup by making it unnecessary. 
llvm-svn: 70425
 2009-04-29 22:47:44 +00:00
Nate Begeman 8d6d4b9289 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan. 
PR2957

ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

llvm-svn: 70225
 2009-04-27 18:41:29 +00:00