d20628ff7d
Pattern match bitfield insert, which helps shift long by immediate, among
...
other things.
llvm-svn: 21127
2005-04-06 23:51:40 +00:00
505f6b760d
Fix some shift bugs
...
llvm-svn: 21126
2005-04-06 22:42:08 +00:00
39ef2f1d43
Fixed version of optimized integer divide is now fixed. Calculate the
...
quotient, not the remainder. Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.
llvm-svn: 21111
2005-04-06 06:44:57 +00:00
dd397119b0
Turn off the div -> mul optimization until it works correctly 100% of the
...
time.
llvm-svn: 21105
2005-04-06 03:36:33 +00:00
4164c4baac
Add support for MULHS and MULHU nodes
...
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.
llvm-svn: 21104
2005-04-06 00:25:27 +00:00
524417357c
Behold, rlwinm with certain immediate arguments is printed as the much more
...
readable slwi or srwi (shift left/right word immediate).
llvm-svn: 21099
2005-04-05 18:19:50 +00:00
a188b698a2
Fix cut & paste errors (32->64), and codegen float->int more optimally.
...
llvm-svn: 21098
2005-04-05 17:32:30 +00:00
9203e169a7
Remove 64 bit simple ISel, it never worked correctly
...
Add initial (buggy) implementation of 64 bit pattern ISel
llvm-svn: 21096
2005-04-05 08:51:15 +00:00
4bde071216
Back out the previous change to SelectBranchCC, since there are cases it
...
could miscompile. A correct solution will be found in the near future.
llvm-svn: 21095
2005-04-05 04:32:16 +00:00
9049e4beec
Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better
...
indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.
llvm-svn: 21094
2005-04-05 04:22:58 +00:00
d6933f5078
Implement SDIV by power of 2 as srawi/addze rather than load imm, divw
...
llvm-svn: 21091
2005-04-05 00:15:08 +00:00
1d5d767a09
Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub
...
llvm-svn: 21090
2005-04-04 23:40:36 +00:00
d96350095c
Add support for multiply-add, multiply-sub, and their negated versions
...
llvm-svn: 21089
2005-04-04 23:01:51 +00:00
1194531057
Make sure that arg regs used by the call instruction are marked as such, so
...
that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.
llvm-svn: 21086
2005-04-04 22:17:48 +00:00
c7186025de
Remove unnecessary register copy now that regalloc is fixed
...
llvm-svn: 21085
2005-04-04 21:48:13 +00:00
d753765460
i1 loads should also be from the low byte of the argument word.
...
llvm-svn: 21077
2005-04-04 09:09:00 +00:00
1ce4839890
Fix i64 return, fix CopyFromReg
...
llvm-svn: 21076
2005-04-04 06:52:38 +00:00
629cdaea39
Full varargs support. All of UnitTests now passes
...
llvm-svn: 21070
2005-04-03 23:11:17 +00:00
7a3e929efc
Pass the correct value for the chain to the store
...
llvm-svn: 21066
2005-04-03 22:22:56 +00:00
f6dc43bd46
Fix SHL_PARTS
...
Start implementation of integer varargs
llvm-svn: 21065
2005-04-03 22:13:27 +00:00
34cc5b329f
Keeping up with the Joneses.
...
Implement not, nor, nand, and eqv
llvm-svn: 21060
2005-04-03 11:20:20 +00:00
165cf4844e
Set shift amount to Extend
...
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions
llvm-svn: 21018
2005-04-02 05:59:34 +00:00
0b7e4cd107
This target doesn't support fabs/fneg yet.
...
llvm-svn: 21010
2005-04-02 05:03:24 +00:00
cfc452d088
Fix i64 returns
...
Generate PowerPC 'subfic' instruction when appropriate
llvm-svn: 20995
2005-04-02 00:42:16 +00:00
cda9aa7fa9
Add ISD::UNDEF node
...
Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
arguments, but not shadowing their value. This allows us to do the right
thing with both fixed and vararg floating point arguments.
llvm-svn: 20988
2005-04-01 22:34:39 +00:00
1c3aea6019
Fix Olden/bh, CR0 was being set in the wrong order
...
LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.
llvm-svn: 20981
2005-04-01 08:57:43 +00:00
c9e50238c5
Also apply Chris's fix to FP select and SETCC
...
llvm-svn: 20979
2005-04-01 07:21:30 +00:00
ffc7f243fe
Move the selection of the arms of the select operation up to the conditional
...
part to make sure we get the side effects and to avoid confusing the CFG.
llvm-svn: 20977
2005-04-01 07:10:02 +00:00
2095f3b06b
Fix stores to global addresses
...
Fix calls with no arguments
llvm-svn: 20975
2005-04-01 05:57:17 +00:00
839b34c367
Support indexed loads and stores. This drops Shootout/matrix time from
...
18.8 to 14.8 seconds. The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.
llvm-svn: 20973
2005-04-01 04:45:11 +00:00
f4d91610ff
Implement FP_TO_SINT and FP_TO_UINT
...
llvm-svn: 20972
2005-04-01 02:59:27 +00:00
508aac2ca8
Add support for adding 0.0 and -0.0 to the constant pool, since we lie and
...
say that we support them, for the purposes of generating fsel instructions.
llvm-svn: 20970
2005-04-01 01:08:07 +00:00
4f3a9860d3
Factor out common code, support FP comparison in folded SetCC
...
llvm-svn: 20969
2005-04-01 00:32:34 +00:00
6215b35918
fsel generation for f32 and f64 select
...
generate compare immediate for integer compare with constant
fold setcc into branch
fold setcc into select
Code generation quality for Shootout is now on par with the Simple ISel
llvm-svn: 20968
2005-03-31 23:55:40 +00:00
eddfff338a
Pass the correct values to the chain argument for node construction during
...
LowerCallTo.
Handle ISD::ADD in SelectAddr, allowing us to have nonzero immediates for
loads and stores, amazing!
llvm-svn: 20946
2005-03-31 02:05:53 +00:00
9de7ddf7d5
Rewrite LowerCallTo and Select(ISD::CALL) to properly handle float varargs
...
Tell the SelectionDAG ISel to expand SEXTLOAD of i1 and i8, rather than
complicate the code in ISD::SEXTLOAD to do it by hand
Combine the FP and Int ISD::LOAD codegen
Generate better code for constant pool loads
As a result, all of Shootout, and likely many other programs are now
working.
llvm-svn: 20945
2005-03-31 00:15:26 +00:00
4c0780cf42
Fix calls whose arguments fit entirely in registers to not break the Chain.
...
Implement SINT_TO_FP and UINT_TO_FP
Remove some dead code from the simple ISel
llvm-svn: 20944
2005-03-30 19:38:35 +00:00
a8114a0f48
Fix frame index code to generate legal PowerPC instructions. About half of
...
Shootout now works.
llvm-svn: 20940
2005-03-30 02:23:08 +00:00
5851a66128
Fix external symbol printing in the AsmPrinter. Tell the ISel that we
...
don't support things like memcpy directly. This allows a handful of the
Shootout programs to work, yay!
llvm-svn: 20939
2005-03-30 01:45:43 +00:00
9c40e9c61f
Fix BranchCC (it's still dumb), and implement FP select (also dumb)
...
llvm-svn: 20935
2005-03-29 22:48:55 +00:00
28145edd30
Implement integer select and i1 sign extend
...
llvm-svn: 20934
2005-03-29 22:24:51 +00:00
28c5ac9ff4
Implement SetCC, fix ZERO_EXTEND_INREG
...
llvm-svn: 20933
2005-03-29 21:54:38 +00:00
1ce9aacf2e
fix a warning in the optimized build
...
llvm-svn: 20920
2005-03-29 15:13:27 +00:00
60956dd52f
Implement div, rem, and frameindex
...
llvm-svn: 20907
2005-03-29 00:03:27 +00:00
731bed10c7
Pattern ISel: fix argument loading for i64s (thanks chris)
...
Simple ISel: fix i64 subtract
llvm-svn: 20903
2005-03-28 23:08:54 +00:00
66acad746f
Remove fake instruction 'subc' (mnemonic for subfc).
...
More pattern isel updates
llvm-svn: 20902
2005-03-28 22:28:37 +00:00
5bdfc63516
Implement proper loads and zero-extends of all types
...
llvm-svn: 20897
2005-03-28 19:36:43 +00:00
518a994b7d
Fix that pesky floats in integer regs problem by assigning the f32 type to
...
the correct register class. Also remove the loading of float data into int
regs part of varargs; it will need to be implemented differently later.
llvm-svn: 20857
2005-03-26 08:25:22 +00:00
dcad53e7bd
Get closer to having varargs working. There's still something strange
...
going on with copies between floating point and integer register files
being generated. Once that is solved, varargs will be done.
llvm-svn: 20856
2005-03-26 07:46:36 +00:00
c95bf7b226
Make 64bit args and float args work correct with calls. Thanks to Chris
...
for explaining EXTRACT_ELEMENT to me.
llvm-svn: 20847
2005-03-26 02:17:46 +00:00
e70b5c79f8
Next round of pattern isel changes, mostly dealing with calls.
...
llvm-svn: 20841
2005-03-26 01:28:53 +00:00
5d7610de65
Correct a documention link
...
llvm-svn: 20840
2005-03-26 01:28:05 +00:00
0ad33afe22
Support global addresses and fix call returns. Varargs still aren't
...
handled correctly for floating point arguments, or more than 8 arguemnts.
This does however, allow hello world to run.
llvm-svn: 20832
2005-03-25 08:34:25 +00:00
ad5151d785
Implement next round of Pattern ISel fixes
...
1. void returns
2. multiplies
3. calls
llvm-svn: 20822
2005-03-24 23:35:30 +00:00
3a9a2f9ec7
Fix an incorrect argument being passed to BuildMI for indirect calls.
...
llvm-svn: 20821
2005-03-24 23:34:38 +00:00
d73c87a424
Commit Gabor Greif's patch to use iterators in lowering intrinsics.
...
llvm-svn: 20816
2005-03-24 20:07:16 +00:00
b15317b74a
eliminate dead variables, patch contributed by Gabor Greif!
...
llvm-svn: 20812
2005-03-24 17:32:20 +00:00
7ec19b4d5a
Implement more of the PPC32 Pattern ISel:
...
1) dynamic stack alloc
2) loads
3) shifts
4) subtract
5) immediate form of add, and, or, xor
6) change flag from -pattern-isel to -enable-ppc-pattern-isel
Remove dead arguments from getGlobalBaseReg in the simple ISel
llvm-svn: 20810
2005-03-24 06:28:42 +00:00
a3abb4c01a
Fix silly "no newline at end of file" warning
...
llvm-svn: 20809
2005-03-24 06:16:18 +00:00
20e7e28ee7
Addition of the PPC32 Pattern ISel. While it is far from complete, it will
...
be brought up to parity with the current simple ISel in the coming days.
Currently, -pattern-isel is required to trigger it.
llvm-svn: 20805
2005-03-24 04:41:43 +00:00
82ae9e1dda
We may be adding functions to the Module during initialization, so
...
conservatively, it's modified
llvm-svn: 20735
2005-03-21 19:22:14 +00:00
531f9e92d4
This mega patch converts us from using Function::a{iterator|begin|end} to
...
using Function::arg_{iterator|begin|end}. Likewise Module::g* -> Module::global_*.
This patch is contributed by Gabor Greif, thanks!
llvm-svn: 20597
2005-03-15 04:54:21 +00:00
1f1462fafa
Fix a crash handling 'undef bool', fixing an llc crash on 186.crafty
...
llvm-svn: 20523
2005-03-08 22:53:09 +00:00
5b5caaf3cd
cleanup the cfg after lsr
...
llvm-svn: 20410
2005-03-02 21:56:00 +00:00
c8bb99760a
Add a temporary option for llc-beta: -enable-lsr-for-ppc, which turns on
...
Loop Strength Reduction.
llvm-svn: 20399
2005-03-02 06:19:22 +00:00
915fd0de4b
Fix a problem where the PPC backend lost track of the fact that it had
...
to save and restore the LR register on entry and exit of a leaf function
that needed to access globals or the constant pool. This should hopefully
fix oscar from sending the PPC tester spinning out of control.
llvm-svn: 20197
2005-02-15 20:26:49 +00:00
d7bffad559
Fix Regression/CodeGen/PowerPC/2005-01-14-UndefLong.ll
...
llvm-svn: 19557
2005-01-14 20:22:02 +00:00
c3ed31f837
Fix: Regression/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll
...
llvm-svn: 19555
2005-01-14 19:31:00 +00:00
82787e90f3
This hunk:
...
- unsigned TrueValue = getReg(TrueVal, BB, BB->begin());
+ unsigned TrueValue = getReg(TrueVal);
Fixes the PPC regressions from last night.
The other hunk is just a clarity improvement.
llvm-svn: 19263
2005-01-02 23:07:31 +00:00
83df5d25b7
Fix a FIXME: Select instructions on longs were miscompiled.
...
While we're at it, improve codegen of select instructions. For this
testcase:
int %test(bool %C, int %A, int %B) {
%D = select bool %C, int %A, int %B
ret int %D
}
We used to generate this code:
_test:
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
b .LBB_test_3 ;
.LBB_test_2: ;
or r5, r4, r4
.LBB_test_3: ;
or r3, r5, r5
blr
Now we emit:
_test:
cmpwi cr0, r3, 0
bne .LBB_test_2 ;
.LBB_test_1: ;
or r4, r5, r5
.LBB_test_2: ;
or r3, r4, r4
blr
-Chris
llvm-svn: 19214
2005-01-01 16:10:12 +00:00
a38954dd64
Specify all of the targets built.
...
llvm-svn: 18985
2004-12-16 17:26:44 +00:00
0782e27d85
Factor out common .td file chunks.
...
llvm-svn: 18982
2004-12-16 16:31:57 +00:00
cbd47631ea
Fix Regression/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll, and all programs
...
when compiled with debug information.
llvm-svn: 18835
2004-12-12 20:36:19 +00:00
10b637eade
CSE calls to getTypeSize.
...
llvm-svn: 18833
2004-12-12 20:31:00 +00:00
17550c456c
Use the target triple to pick this target.
...
llvm-svn: 18830
2004-12-12 17:40:28 +00:00
bd11625469
Fix several bugs in 'op x, imm' handling. Foremost is that we now emit
...
addi r3, r3, -1
instead of
addi r3, r3, 1
for 'sub int X, 1'.
Secondarily, this fixes several cases where we could crash given an unsigned
constant. And fixes a couple of minor missed optimization cases, such as
xor X, ~0U -> not X
llvm-svn: 18379
2004-11-30 07:30:20 +00:00
7562a05735
Fix CodeGen/PowerPC/2004-11-30-shr-var-crash.ll
...
llvm-svn: 18376
2004-11-30 06:40:04 +00:00
ce350cbd3a
Fix test/Regression/CodeGen/PowerPC/2004-11-29-ShrCrash.ll
...
llvm-svn: 18374
2004-11-30 06:36:11 +00:00
9eeb2033ff
Fix test/Regression/CodeGen/PowerPC/2004-11-30-shift-crash.ll
...
llvm-svn: 18371
2004-11-30 06:29:10 +00:00
c0f8a1c721
The LLVM bool type shall have 1 byte alignment on PPC.
...
llvm-svn: 18311
2004-11-28 21:16:45 +00:00
43123c9f7a
Remove the ISel->AsmPrinter link via the TargetMachine that was put in
...
place to help bring up the PowerPC back end on Darwin. This code is no
longer serves any purpose now that the AsmPrinter does the right thing
all the time printing GlobalValues. --Cruft.
llvm-svn: 18267
2004-11-27 04:45:11 +00:00
b50fd9262d
There is no reason to store <x,x>, just store <x>.
...
llvm-svn: 18263
2004-11-26 20:25:17 +00:00
3f76eb69f6
Enable optimization suggested by Chris Lattner to not emit reloc stubs for
...
static global variables whose addresses are taken. This allows us to
convert the following code for taking the address of a static function foo
addis r2, r30, ha16(Ll1__2E_foo_2$non_lazy_ptr-"L00001$pb")
lwz r3, lo16(Ll1__2E_foo_2$non_lazy_ptr-"L00001$pb")(r2)
which also includes linker stub code emitted at the end of the .s file not
shown here, and replace it with this:
addis r2, r30, ha16(l1__2E_foo_2-"L00001$pb")
la r3, lo16(l1__2E_foo_2-"L00001$pb")(r2)
which in addition to not needing linker help, also has no load instruction.
For those not up on PowerPC mnemonics, la is shorthand for add immediate.
llvm-svn: 18239
2004-11-25 07:09:01 +00:00
8cbad8efcf
Fix the build on non ppc machines
...
llvm-svn: 18235
2004-11-25 06:14:45 +00:00
497a622376
The JIT works enough
...
llvm-svn: 18228
2004-11-25 04:14:54 +00:00
da76c16ba4
Fix encoding of fsel, fixing olden/power, McCat/bisort and several others.
...
All of Olden passes now! :)
llvm-svn: 18227
2004-11-25 04:11:07 +00:00
305f78f646
Fix encoding of fneg instruction
...
llvm-svn: 18226
2004-11-25 03:53:44 +00:00
191e525bae
Fix encoding of swari, fixing several programs, including Olden/mst
...
llvm-svn: 18225
2004-11-25 03:40:20 +00:00
5d8ae54267
There is not a 1-1 mappign between llvm blocks and PPC blocks, do not use
...
LLVM blocks as the keys for the branch rewriter. This fixes treeadd and
many other programs with the JIT.
llvm-svn: 18223
2004-11-25 00:33:57 +00:00
dd516799d7
* Rename existing relocations to be more specific
...
* Add relocations for refernces to non-lazy darwin stubs and implement
them correctly.
With this change, we can correctly references external globals, and now
all but two UnitTests and all but 1 Regression/C tests pass.
More importantly, bugpoint-jit will start giving us useful testcases,
instead of always telling us that references to external globals don't
work :)
llvm-svn: 18222
2004-11-24 22:30:08 +00:00
e49936af54
Add the same optimization that we do loading from fixed alloca slots to
...
storing to fixed alloca slots.
llvm-svn: 18221
2004-11-24 21:53:14 +00:00
078b6f2b62
Write CompilationCallback as an explicit assembly stub to avoid getting GCC's
...
prolog.
llvm-svn: 18220
2004-11-24 21:01:46 +00:00
659d72e319
When rewriting the original call instruction, make sure to rewrite it to
...
call the right address.
llvm-svn: 18213
2004-11-24 18:00:02 +00:00
cb9af557e7
Force the intregs ptr into R2 and the FPregs ptr into R3. This fixes a really
...
obscure problem where we were doing:
lmw r3,0(r9)
which is undefined on PPC. Now we do:
lmw r3,0(r2)
by force, not relying on the GCC register allocator for luck :)
llvm-svn: 18212
2004-11-24 17:42:55 +00:00
130888ad37
Fix a few more tests by encoding the extsb and other XForm11 instructions
...
correctly.
llvm-svn: 18200
2004-11-24 03:52:02 +00:00
022e271db5
Fix the encoding of ORi and other DForm4 instructions. This brings us to
...
36/42 SingleSource/UnitTests passing!
llvm-svn: 18199
2004-11-24 02:15:41 +00:00
57542fcfc2
Loads are relocatable too
...
llvm-svn: 18198
2004-11-24 02:03:44 +00:00
7b1cf0d6c6
Calls do not need a MovPCtoLR instruction
...
llvm-svn: 18197
2004-11-24 02:00:06 +00:00
6a7ebe034e
Get constant pools working. This fixes even more programs, allowing us to
...
pass 24/42 in UnitTests (up from 20).
llvm-svn: 18196
2004-11-24 01:56:12 +00:00
193b6f3281
Rewrite branches more closely to correct. This makes more stuff pass, and
...
stops the infinite loops!
llvm-svn: 18194
2004-11-24 01:35:12 +00:00
Nate Begeman