3aeaf9e4c1
Add 132986 back, but avoid non-determinism if a bb address gets reused.
...
llvm-svn: 132995
2011-06-14 15:31:54 +00:00
0e230bc7bb
Add a testcase for #9623
...
llvm-svn: 132991
2011-06-14 13:23:10 +00:00
06ba7a68de
revert 132986 to see if the bots go green.
...
llvm-svn: 132988
2011-06-14 12:48:26 +00:00
a0da74677e
This testcase cause a failure on some bots. Remove the failing test until
...
further investigation.
llvm-svn: 132986
2011-06-14 09:10:37 +00:00
10193c830b
Add a testcase for checking the integer-promotion of many different vector
...
types (with power of two types such as 8,16,32 .. 512).
Fix a bug in the integer promotion of bitcast nodes. Enable integer expanding
only if the target of the conversion is an integer (when the type action is
scalarize).
Add handling to the legalization of vector load/store in cases where the saved
vector is integer-promoted.
llvm-svn: 132985
2011-06-14 08:11:52 +00:00
844485af13
Implement Jakob's suggestion on how to detect fall thought without calling
...
AnalyzeBranch.
llvm-svn: 132981
2011-06-14 06:08:32 +00:00
29386fb10d
Since ARM's prefetch implementation predicted the presence of a instruction
...
cache prefetch and now that the info from "prefetch" to "ARMPreload" is present,
only add a testcase for PLI.
llvm-svn: 132978
2011-06-14 05:11:46 +00:00
dc9ff3a4b1
Add one more argument to the prefetch intrinsic to indicate whether it's a data
...
or instruction cache access. Update the targets to match it and also teach
autoupgrade.
llvm-svn: 132976
2011-06-14 04:58:37 +00:00
da24f2f8e1
Make the threshold used by branch folding softer. Before we would get a
...
sharp all or nothing transition when one extra predecessor was added. Now
we still test first ones for merging.
llvm-svn: 132974
2011-06-14 04:41:17 +00:00
e712449688
Heuristic: If the number of operands in the alias are more than the number of
...
operands in the aliasee, don't print the alias.
llvm-svn: 132963
2011-06-14 03:17:20 +00:00
fb03a92c33
Be less aggressive about hinting in RAFast.
...
In particular, don't spill dirty registers only to satisfy a hint. It is
not worth it.
The attached test case provides an example where the fast allocator
would spill a register when other registers are available.
llvm-svn: 132900
2011-06-13 03:26:46 +00:00
2f3c2fe7c5
Really fix the fall-through logic.
...
Add a triple to the tests.
llvm-svn: 132885
2011-06-12 05:57:01 +00:00
cb55e752ed
Test for the previous commit.
...
llvm-svn: 132884
2011-06-12 05:35:39 +00:00
defd4b0875
AnalyzeBranch doesn't change which successors a bb has, just the order
...
we try to branch to them.
Before we were creating successor lists with duplicated entries. Fixing that
found a bug in isBlockOnlyReachableByFallthrough that would causes it to
return the wrong answer for
-----------
...
jne foo
jmp bar
foo:
----------
llvm-svn: 132882
2011-06-12 03:20:32 +00:00
cd2124a3f0
Add full x86 fast-isel support for memcpy and memset.
...
rdar://9431466
llvm-svn: 132864
2011-06-10 23:39:36 +00:00
82818e4d95
Add -mattr=+sse2 to make the buildbots happy.
...
llvm-svn: 132839
2011-06-10 08:26:26 +00:00
19d5253f60
Adding a test case for revision 132825.
...
llvm-svn: 132830
2011-06-10 02:44:19 +00:00
e3944cd825
Add a simple test which makes sure folding immediate float zero to a memory operand works.
...
llvm-svn: 132824
2011-06-10 00:30:08 +00:00
361548d4b4
A CCState was being created without setting whether it is in the Call or Prologue state,
...
causing an assertion failure downstream. This fixes <rdar://problem/9562908>.
This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.
llvm-svn: 132811
2011-06-09 22:30:07 +00:00
1877ac9937
Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine. Part of rdar://9562809.
...
The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now.
llvm-svn: 132809
2011-06-09 22:14:44 +00:00
f15601f19a
Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
...
llvm-svn: 132777
2011-06-09 16:03:19 +00:00
cafa08cbf3
Recommit r132764 since it didn't cause the windows buildbot failures.
...
llvm-svn: 132776
2011-06-09 15:39:01 +00:00
76fd742d16
Temporarily revert 132764 to see if it fixes the Windows buildbot.
...
llvm-svn: 132771
2011-06-09 06:29:54 +00:00
0683a7212e
Initial support for inline asm memory operand constraints.
...
llvm-svn: 132768
2011-06-09 03:31:05 +00:00
11edab6a46
If the alignment of the byval argument is greater than the alignment
...
of the frame then increase the maximum alignment of the frame to
match.
Fixes PR6965
llvm-svn: 132764
2011-06-09 00:15:19 +00:00
4e9af454f7
Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
...
dynamically allocated stack area was not set.
llvm-svn: 132758
2011-06-08 21:28:09 +00:00
2e252de512
Fix an issue where the two-address conversion pass incorrectly rewrites untied
...
operands to an early clobber register. This fixes <rdar://problem/9566076>.
llvm-svn: 132738
2011-06-07 23:54:00 +00:00
c85e0d81e4
Fix a silly error I introduce in r131951.
...
Fixes PR10095.
llvm-svn: 132735
2011-06-07 23:26:45 +00:00
7ae360f2e1
Tweak this test for ARM-hosted 'bot.
...
llvm-svn: 132711
2011-06-07 15:23:11 +00:00
d1e8f9a1e0
Move the legalizer tests to the X86 directory because the test uses the x86
...
codegen. Thanks Galina.
llvm-svn: 132706
2011-06-07 05:23:58 +00:00
08b7a779ef
Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue:
...
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
callee-saved register is emitted even when no callee-saved registers are
saved.
- When a callee-saved double precision register is saved, two cfi_offset
directives, one for each of the paired single precision registers, should be
emitted.
llvm-svn: 132703
2011-06-07 02:17:21 +00:00
df476270eb
Simplify local live range splitting's safeguard to fix PR10070.
...
When local live range splitting creates a live range with the same
number of instructions as the old range, mark it as RS_Local. When such
a range is seen again, require that it be split in a way that reduces
the number of instructions. That guarantees we are making progress while
still being able to perform 3 -> 2+3 splits as required by PR10070.
This also means that the PrevSlot map is no longer needed. This was also
used to estimate new spill weights, but that is no longer necessary
after slotIndexes::insertMachineInstrInMaps() got the extra Late
insertion argument.
llvm-svn: 132697
2011-06-06 23:55:20 +00:00
e0d3426e1a
Followup to 132458, omit unnecessary stack copy when x87 input is a
...
load. rdar://problem/6373334
llvm-svn: 132696
2011-06-06 23:15:58 +00:00
c807fa5687
Add methods to support the integer-promotion of vector types. Methods to
...
legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc.
llvm-svn: 132689
2011-06-06 20:55:56 +00:00
2f7f64f9e1
Test case for PR10085.
...
llvm-svn: 132682
2011-06-06 20:03:22 +00:00
bd375f1a3f
PR10077: fix fast-isel of extractvalue of aggregate constants.
...
llvm-svn: 132676
2011-06-06 05:46:34 +00:00
59652d36a5
Harden tests for windows path separators.
...
llvm-svn: 132671
2011-06-05 18:20:05 +00:00
38080e8700
Fix a test that keeps breaking when allocation orders change.
...
Who said FileCheck couldn't handle arbitrarily complex conditions?
llvm-svn: 132654
2011-06-04 23:34:40 +00:00
06bd6d304e
TypeLegalizer: Add support for passing of vector-promoted types in registers (copyFromParts/copyToParts).
...
llvm-svn: 132649
2011-06-04 20:58:08 +00:00
be605494ac
Reapply 132424 with fixes. This fixes PR10068.
...
rdar://problem/5993888
llvm-svn: 132606
2011-06-03 23:53:54 +00:00
496fa5556f
Fix some tests that depend on register allocation.
...
llvm-svn: 132602
2011-06-03 22:45:21 +00:00
1e3e8933ed
Another possible bug. Stopgap until we can autogenerate tables and
...
constraint lengths.
Part of rdar://9037836 and rdar://9119939
llvm-svn: 132598
2011-06-03 22:09:12 +00:00
761a5d4280
Fix an off by one error.
...
Part of rdar://9037836 and rdar://9119939
llvm-svn: 132590
2011-06-03 20:44:52 +00:00
b8bf3c0f8b
Switch AllocationOrder to using RegisterClassInfo instead of a BitVector
...
of reserved registers.
Use RegisterClassInfo in RABasic as well. This slightly changes som
allocation orders because RegisterClassInfo puts CSR aliases last.
llvm-svn: 132581
2011-06-03 20:34:53 +00:00
354b2a25f3
Make the Uv constraint a memory operand. This doesn't solve the
...
addressing mode problem mentioned in r132559.
Backend part of rdar://9037836 and part of rdar://9119939
llvm-svn: 132561
2011-06-03 17:24:37 +00:00
a4a59aebd9
Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.
...
- Check for MTCTR8 in addition to MTCTR when looking up a hazard.
- When lowering an indirect call use CTR8 when targeting 64bit.
- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.
The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.
llvm-svn: 132552
2011-06-03 15:47:49 +00:00
86585798af
Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.
...
rdar://9431157
llvm-svn: 132522
2011-06-03 01:13:19 +00:00
e5feef0fe1
During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def.
...
Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint!
llvm-svn: 132483
2011-06-02 20:07:12 +00:00
e37b939793
Add test for PR10068.
...
llvm-svn: 132482
2011-06-02 20:02:48 +00:00
aa318ae495
Revert 132424 to fix PR10068.
...
llvm-svn: 132479
2011-06-02 19:57:47 +00:00
351422bdc8
Andy pointed out a dumb omission in this test case. Thanks Andy!
...
llvm-svn: 132477
2011-06-02 19:26:49 +00:00
e239a6920e
Jakob pointed out a dumb omission in this test case. Thanks Jakob!
...
llvm-svn: 132472
2011-06-02 18:44:05 +00:00
8d530ad22a
Omit unnecessary stack copy when x87 input is a load.
...
rdar://problem/6373334
llvm-svn: 132458
2011-06-02 15:57:11 +00:00
7f25c32d5b
Tweak testcase for ARM bot. rdar://problem/5993888
...
llvm-svn: 132454
2011-06-02 05:05:39 +00:00
2446869410
Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.
...
llvm-svn: 132448
2011-06-02 01:03:14 +00:00
d84c76f2a7
Test case for r132444.
...
llvm-svn: 132445
2011-06-02 00:25:53 +00:00
324f843107
Do not drop constant values when a variable's content is described using .debug_loc entries.
...
llvm-svn: 132427
2011-06-01 22:03:25 +00:00
7adc95f69e
Recommit 132404 with fixes. rdar://problem/5993888
...
llvm-svn: 132424
2011-06-01 21:33:14 +00:00
690030c116
Allow bitcasts between valid types of the same size and vector
...
types if the vector type is legal.
Fixes rdar://9306086
llvm-svn: 132420
2011-06-01 19:55:10 +00:00
aab130d995
Revert 132404 to appease a buildbot. rdar://problem/5993888
...
llvm-svn: 132419
2011-06-01 19:52:20 +00:00
41b1aa466d
Cleanup test case. rdar://problem/5660695
...
llvm-svn: 132408
2011-06-01 18:23:14 +00:00
7b7c102f2c
Add support for x86 CMPEQSS and friends. These instructions do a
...
floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs. Only profitable when the user wants a materialized 0
or 1 at runtime. rdar://problem/5993888
llvm-svn: 132404
2011-06-01 17:17:45 +00:00
6f89e2ffaa
A forthcoming SSE patch will break this test; since the test is also
...
valid for x87, re-target to x87. rdar://problem/5993888
llvm-svn: 132401
2011-06-01 16:13:09 +00:00
4d2fe66dc0
Test case for 132396. rdar://problem/5660695
...
llvm-svn: 132399
2011-06-01 15:50:29 +00:00
8b24a731f2
This patch is another step in the direction of adding vector select. In this
...
patch we add a flag to enable a new type legalization decision - to promote
integer elements in vectors. Currently, the rest of the codegen does not support
this kind of legalization. This flag will be removed when the transition is
complete.
llvm-svn: 132394
2011-06-01 12:51:46 +00:00
2f14b0bb1d
Add XCore intrinsic for crc8.
...
llvm-svn: 132340
2011-05-31 16:24:49 +00:00
542f9a2bcf
Add XCore intrinsic for crc32.
...
llvm-svn: 132336
2011-05-31 14:47:36 +00:00
36d027f7f6
Convert test to FileCheck.
...
llvm-svn: 132335
2011-05-31 14:00:05 +00:00
98fc4c8bbc
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
...
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.
Patch by Sasa Stankovic.
llvm-svn: 132323
2011-05-31 02:54:07 +00:00
bf3c1251e0
This patch implements the thread local storage. Implemented are General
...
Dynamic, Initial Exec and Local Exec TLS models.
Patch by Sasa Stankovic
llvm-svn: 132322
2011-05-31 02:53:58 +00:00
08600bcf65
Use the dwarf->llvm mapping to print register names in the cfi
...
directives.
Fixes PR9826.
llvm-svn: 132317
2011-05-30 20:20:15 +00:00
dd6fcc4e46
Fix PR10046 by updating LiveVariables kill info when splitting live ranges.
...
This only affects targets like Mips where branch instructions may kill virtual
registers. Most other targets branch on flag values, so virtual registers are
not involved.
The problem is that MachineBasicBlock::updateTerminator deletes branches and
inserts new ones while LiveVariables keeps a list of pointers to instructions
that kill virtual registers. That list wasn't properly updated in
MBB::SplitCriticalEdge.
llvm-svn: 132298
2011-05-29 20:10:28 +00:00
7d84ece09b
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
...
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
Take 2, now with more basic competence.
llvm-svn: 132295
2011-05-29 19:50:32 +00:00
e64371b932
I didn't mean to commit these residues of a personal project.
...
llvm-svn: 132293
2011-05-29 19:41:56 +00:00
085d891d80
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
...
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
llvm-svn: 132291
2011-05-29 19:39:04 +00:00
325110f30d
Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs
...
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.
llvm-svn: 132248
2011-05-28 04:07:29 +00:00
d00e8ad803
Implement the 'M' output modifier for arm inline asm. This is fairly
...
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.
rdar://9119939
llvm-svn: 132242
2011-05-28 01:40:44 +00:00
b406843fe5
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
...
Need this to prevent emitting illegal conditional move instructions.
llvm-svn: 132240
2011-05-28 01:07:07 +00:00
1d553a2cc4
Fix the remaining atomic intrinsics to use the right register classes on Thumb2,
...
and add some basic tests for them.
llvm-svn: 132235
2011-05-27 23:54:00 +00:00
873106a932
Force a triple to make this test pass on Darwin.
...
llvm-svn: 132228
2011-05-27 23:12:48 +00:00
75d99e4b70
Add a GR32_NOREX_NOSP register class and fix a bug where getMatchingSuperRegClass()
...
was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.
llvm-svn: 132225
2011-05-27 22:26:04 +00:00
d23bfb8a7a
Make size computation less brittle.
...
llvm-svn: 132222
2011-05-27 22:05:41 +00:00
2348f3133f
Make room for register allocation to improve.
...
llvm-svn: 132213
2011-05-27 20:15:06 +00:00
518bcd0ef4
Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789
...
llvm-svn: 132211
2011-05-27 20:11:27 +00:00
63a9cef5c2
Delete a test that is no longer relevant.
...
According to PR2536, the old spiller had trouble with the IMPLICIT_DEF in this
code:
%reg1028<def> = MOV16rm %reg0, 1, %reg0, <ga:g_5>, Mem:LD(2,2) [g_5 + 0]
%reg1039<def> = IMPLICIT_DEF
%reg1038<def> = INSERT_SUBREG %reg1039, %reg1028, 2
%reg1025<def> = AND32ri %reg1038, 65534, %%EFLAGS<imp-def>
However, today we emit a zero-extending load instead:
%vreg10<def> = MOVZX32rm16 %noreg, 1, %noreg, <ga:@g_5>, %noreg; %mem:LD2[@g_5] GR32:%vreg10
%vreg0<def> = AND32ri %vreg10, 65534, %%EFLAGS<imp-def,dead>; %GR32:%vreg0,%vreg10
This makes the test pointless since it no longer creates the spiller hazard.
llvm-svn: 132210
2011-05-27 20:02:42 +00:00
97c9f84f68
Add iOS test
...
llvm-svn: 132203
2011-05-27 19:04:21 +00:00
3a8d9625b0
And fix the test in r132194.
...
llvm-svn: 132196
2011-05-27 18:14:28 +00:00
fe84bd659c
Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076
...
llvm-svn: 132194
2011-05-27 18:02:04 +00:00
3c6aed2d98
Select DW_AT_const_value size based on variable size.
...
llvm-svn: 132193
2011-05-27 16:45:18 +00:00
34ef49dc74
Fix PR10029 - VerifyCoalescing failure on patterns_dfa.c of 445.gobmk.
...
llvm-svn: 132181
2011-05-27 05:04:51 +00:00
b362884ca9
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist.
...
crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].
llvm-svn: 132163
2011-05-26 23:13:19 +00:00
42ddaa10d3
During branch folding avoid inserting redundant DBG_VALUE machine instructions.
...
llvm-svn: 132148
2011-05-26 21:47:59 +00:00
aa560006ed
Add support for C++ exception handling.
...
llvm-svn: 132131
2011-05-26 18:59:03 +00:00
c48f7c212e
Fix test on Windows.
...
llvm-svn: 132126
2011-05-26 18:00:32 +00:00
493a12bf5e
Reverting 132105: it broke some LLVM-GCC DejaGNU tests.
...
llvm-svn: 132108
2011-05-26 04:09:49 +00:00
276f231c2f
Correctly handle a one-word struct passed byval on x86_64.
...
rdar://problem/6920088
llvm-svn: 132105
2011-05-26 02:44:56 +00:00
c70355195c
Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
...
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).
rdar://9437928 .
llvm-svn: 132099
2011-05-25 23:49:02 +00:00
fa63d3096d
Define WeakRefDirective.
...
llvm-svn: 132098
2011-05-25 23:30:30 +00:00
8c5e4192e6
Implement the 'm' modifier. Note that it only works for memory operands.
...
Part of rdar://9119939
llvm-svn: 132081
2011-05-25 20:51:58 +00:00
44eba3ac49
Custom-lower FCOPYSIGN nodes.
...
llvm-svn: 132074
2011-05-25 19:32:07 +00:00
3088e0a179
Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This
...
fixes <rdar://problem/9495913>
llvm-svn: 132042
2011-05-25 04:45:27 +00:00
fc9bae6f8b
Replace the -unwind-tables option with a per function flag. This is more
...
LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.
llvm-svn: 132033
2011-05-25 03:44:17 +00:00
aac670c1c8
Fix lowering of DYNAMIC_STACKALLOC nodes.
...
llvm-svn: 132030
2011-05-25 02:20:00 +00:00
1b724948e9
Implement the arm 'L' asm modifier.
...
Part of rdar://9119939
llvm-svn: 132024
2011-05-24 23:27:13 +00:00
b1dda56ac2
Implement the immediate part of the 'B' modifier.
...
Part of rdar://9119939
llvm-svn: 132023
2011-05-24 23:15:43 +00:00
7617883ce3
Add support for the arm 'y' asm modifier.
...
Fixes part of rdar://9444657
llvm-svn: 132011
2011-05-24 22:10:34 +00:00
2486729839
Test case for r132003.
...
llvm-svn: 132005
2011-05-24 21:28:18 +00:00
ce4037ebcf
Fix test case.
...
llvm-svn: 131988
2011-05-24 19:37:15 +00:00
0f30561bae
Revision 131986 test case.
...
llvm-svn: 131987
2011-05-24 19:29:37 +00:00
0f33be1b87
Fix the defaults for .eh_frame. We were marking it as writable.
...
llvm-svn: 131951
2011-05-24 02:50:20 +00:00
88f9137fd7
- Teach SelectionDAG::isKnownNeverZero to return true (op x, c) when c is
...
non-zero.
- Teach X86 cmov optimization to eliminate the cmov from ctlz, cttz extension
when the source of X86ISD::BSR / X86ISD::BSF is proven to be non-zero.
rdar://9490949
llvm-svn: 131948
2011-05-24 01:48:22 +00:00
6af5bd2537
Add pattern for double-to-integer conversion. Patch by Sasa Stankovic.
...
llvm-svn: 131927
2011-05-23 22:16:43 +00:00
6c4a319088
When checking for signed multiplication overflow, watch out for INT_MIN and -1.
...
This fixes PR9845.
llvm-svn: 131919
2011-05-23 21:07:39 +00:00
f9e5750fc8
Change StackDirection from StackGrowsUp to StackGrowsDown.
...
The following improvements are accomplished as a result of applying this patch:
- Fixed frame objects' offsets (relative to either the virtual frame pointer or
the stack pointer) are set before instruction selection is completed. There is
no need to wait until Prologue/Epilogue Insertion is run to set them.
- Calculation of final offsets of fixed frame objects is straightforward. It is
no longer necessary to assign negative offsets to fixed objects for incoming
arguments in order to distinguish them from the others.
- Since a fixed object has its relative offset set during instruction
selection, there is no need to conservatively set its alignment to 4.
- It is no longer necessary to reorder non-fixed frame objects in
MipsFrameLowering::adjustMipsStackFrame.
llvm-svn: 131915
2011-05-23 20:16:59 +00:00
9987d3098b
Test case for r131908.
...
llvm-svn: 131909
2011-05-23 17:49:29 +00:00
c4d9a84159
While replacing all uses of a SDValue with another value, do not forget to transfer SDDbgValue.
...
llvm-svn: 131907
2011-05-23 17:35:08 +00:00
bc90690b24
Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches
...
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.
llvm-svn: 131894
2011-05-23 01:57:17 +00:00
4cd5187f5b
RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller.
...
llvm-svn: 131868
2011-05-22 21:41:23 +00:00
2fd48f2730
Implement mulo x, 2 -> addo x, x in DAGCombiner.
...
llvm-svn: 131800
2011-05-21 18:31:55 +00:00
e08fb1dce9
Merge and FileCheckize test cases.
...
llvm-svn: 131799
2011-05-21 18:31:48 +00:00
60afcc2a6f
Add fast-isel support for byval calls on x86.
...
llvm-svn: 131764
2011-05-20 22:21:04 +00:00
91f1d24736
Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.
...
rdar://problem/8614450
llvm-svn: 131746
2011-05-20 19:04:40 +00:00
43407fe633
Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle
...
saving and restoring them.
llvm-svn: 131745
2011-05-20 18:39:33 +00:00
ad00f3d0b9
Fixed regression due to commit 131709, which disables vararg tail call optimizations on Win64
...
llvm-svn: 131740
2011-05-20 17:49:39 +00:00
0bf26746d9
Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility.
...
llvm-svn: 131730
2011-05-20 15:11:26 +00:00
e0a52df6e5
Fix PR9960 by teaching SimpleRegisterCoalescing::AdjustCopiesBackFrom() to preserve
...
the phikill flag.
llvm-svn: 131717
2011-05-20 03:54:04 +00:00
fe4f9d5977
Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic
...
llvm-svn: 131714
2011-05-20 02:30:51 +00:00
552f8c4819
Don't attempt to tail call optimize for Win64.
...
llvm-svn: 131709
2011-05-20 00:59:28 +00:00
e8d2e9eb35
Revert r131664 and fix it in instcombine instead. rdar://9467055
...
llvm-svn: 131708
2011-05-20 00:54:37 +00:00
22da799428
Add fast-isel support for zeroext and signext ret instructions on x86.
...
llvm-svn: 131689
2011-05-19 22:16:13 +00:00
4014e5e208
Oddly people want to use the 'r' constraint for fp constants on x86.
...
Fixes rdar://9218925
Fixes PR9601
llvm-svn: 131682
2011-05-19 21:33:47 +00:00
e53a77d3a6
Fix up this test to use explicit triples (Win64 passes a different number of arguments in registers).
...
llvm-svn: 131676
2011-05-19 21:13:08 +00:00
9e6a8cca5d
Align i64 arguments to 64 bit boundaries.
...
llvm-svn: 131668
2011-05-19 20:29:48 +00:00
2b9bd38678
crc32 with 64-bit output zeros upper 32-bits. rdar://9467055
...
llvm-svn: 131664
2011-05-19 18:57:12 +00:00
ae012a7525
Move test to Transforms/InstCombine.
...
llvm-svn: 131634
2011-05-19 05:53:22 +00:00
1d11720ae4
Handle perfect shuffle case that generates a vrev for vectors of floats.
...
Add test case.
llvm-svn: 131582
2011-05-18 21:44:54 +00:00
f4e832b14e
Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible.
...
llvm-svn: 131560
2011-05-18 19:59:50 +00:00
51d696766c
An imminent fix to the x86_64 byval logic will expose a flaw in the
...
x86_64 sibcall logic. I've filed PR9943 for the sibcall problem, and
this patch alters the testcase to work around the flaw. When PR9943
is fixed, this patch should be reverted.
llvm-svn: 131557
2011-05-18 19:19:17 +00:00
3f46c3e702
Force a triple on a couple of tests; we don't support fast-isel of ret on Win64.
...
llvm-svn: 131540
2011-05-18 17:16:37 +00:00
38849debb5
Merge pmovzx test case into existing file.
...
llvm-svn: 131539
2011-05-18 17:02:04 +00:00
bbdcd17d44
PTX: add flag to disable mad/fma selection
...
Patch by Dan Bailey
llvm-svn: 131537
2011-05-18 15:42:23 +00:00
48b182c3a4
In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
...
Updated test case and reverted change to the PerfectShuffle Table.
llvm-svn: 131529
2011-05-18 06:42:21 +00:00
7d7ad8374f
Make some of the fast-isel tests actually test fast-isel (and fix test failures).
...
llvm-svn: 131510
2011-05-18 00:00:10 +00:00
5bd18b6638
X86 pmovsx/pmovzx ignore the upper half of their inputs.
...
rdar://problem/6945110
llvm-svn: 131493
2011-05-17 22:13:31 +00:00
c7e291b354
vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.
...
llvm-svn: 131488
2011-05-17 20:48:40 +00:00
dd45646a47
Move test for appropriate directory.
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llvm-svn: 131477
2011-05-17 19:06:43 +00:00
7b27942fe7
Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872.
...
This is r131438 with a couple small fixes.
llvm-svn: 131474
2011-05-17 18:29:03 +00:00
7335e8a720
Back out r131444 and r131438; they're breaking nightly tests. I'll look into
...
it more tomorrow.
llvm-svn: 131451
2011-05-17 02:36:59 +00:00
e5f7f26df0
Fix test.
...
llvm-svn: 131444
2011-05-17 00:39:14 +00:00
54459240e3
Add target triple so test doesn't fail on Windows machines.
...
llvm-svn: 131439
2011-05-17 00:15:58 +00:00
83ba150f3a
Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872.
...
llvm-svn: 131438
2011-05-17 00:13:47 +00:00
4edf17d91f
Teach LiveInterval::isZeroLength about null SlotIndexes.
...
When instructions are deleted, they leave tombstone SlotIndex entries.
The isZeroLength method should ignore these null indexes.
This causes RABasic to sometimes spill a callee-saved register in the
abi-isel.ll test, so don't run that test with -regalloc=basic. Prioritizing
register allocation according to spill weight can cause more registers to be
used.
llvm-svn: 131436
2011-05-16 23:50:05 +00:00
d4a3609d30
Remove dead code. Fix associated test to use FileCheck.
...
llvm-svn: 131424
2011-05-16 21:28:22 +00:00
a4d4a0162d
Make fast-isel work correctly s/uadd.with.overflow intrinsics.
...
llvm-svn: 131420
2011-05-16 21:06:17 +00:00
9ac944774f
Basic fast-isel of extractvalue. Not too helpful on its own, given the IR clang generates for cases like this, but it should become more useful soon.
...
llvm-svn: 131417
2011-05-16 20:27:46 +00:00
df9db7ed92
Don't produce a vmovntdq if we don't have AVX support.
...
llvm-svn: 131330
2011-05-14 00:30:01 +00:00
e53b7d1a11
Make codegen able to handle values of empty types. This is one way
...
to fix PR9900. I will keep it open until sable is able to comment on it.
llvm-svn: 131294
2011-05-13 15:18:06 +00:00
aa02c0847d
Since I can't reproduce the failures from 131261, re-trying with a
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simplified version. <rdar://problem/9298790>
llvm-svn: 131274
2011-05-13 00:51:54 +00:00
8d57d8ea64
Revert 131266 and 131261 due to buildbot complaints.
...
rdar://problem/9298790
llvm-svn: 131269
2011-05-13 00:15:17 +00:00
ef4940254f
Tweak 131261 (thumb2-cbnz.ll) to generate the intended cbnz.
...
rdar://problem/9298790
llvm-svn: 131266
2011-05-13 00:10:03 +00:00
89f1b47e3a
Non-fast-isel followup to 129634; correctly handle branches controlled
...
by non-CMP expressions. The executable test case (129821) would test
this as well, if we had an "-O0 -disable-arm-fast-isel" LLVM-GCC
tester. Alas, the ARM assembly would be very difficult to check with
FileCheck.
The thumb2-cbnz.ll test is affected; it generates larger code (tst.w
vs. cmp #0 ), but I believe the new version is correct.
rdar://problem/9298790
llvm-svn: 131261
2011-05-12 23:36:41 +00:00
9e56e51fab
Correction. Use explicit target triple in the test.
...
llvm-svn: 131252
2011-05-12 21:55:34 +00:00
43054e6159
Re-enable branchfolding common code hoisting optimization. Fixed a liveness test bug and also taught it to update liveins.
...
llvm-svn: 131241
2011-05-12 20:30:01 +00:00
114ecbd0f4
Move this test to CodeGen/Thumb. rdar://problem/9416774
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llvm-svn: 131196
2011-05-11 19:41:28 +00:00
34a6620748
Identify end of prologue (and beginning of function body) using DW_LNS_set_prologue_end line table opcode.
...
llvm-svn: 131194
2011-05-11 19:22:19 +00:00
8a7beb80f0
Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain).
...
If there is a store after the load node, then there is a chain, which means
that there is another user. Thus, asking hasOneUser would fail. Instead we
ask hasNUsesOfValue on the 'data' value.
llvm-svn: 131183
2011-05-11 14:40:50 +00:00
8f971c27fb
Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a splat vector.
...
llvm-svn: 131179
2011-05-11 08:12:09 +00:00
2a09d65979
Revert 131172 as it is causing clang to miscompile itself. I will try
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to provide a reduced testcase.
llvm-svn: 131176
2011-05-11 03:27:17 +00:00
05fc35e275
Add a late optimization to BranchFolding that hoist common instruction sequences
...
at the start of basic blocks to their common predecessor. It's actually quite
common (e.g. about 50 times in JM/lencod) and has shown to be a nice code size
benefit. e.g.
pushq %rax
testl %edi, %edi
jne LBB0_2
## BB#1:
xorb %al, %al
popq %rdx
ret
LBB0_2:
xorb %al, %al
callq _foo
popq %rdx
ret
=>
pushq %rax
xorb %al, %al
testl %edi, %edi
je LBB0_2
## BB#1:
callq _foo
LBB0_2:
popq %rdx
ret
rdar://9145558
llvm-svn: 131172
2011-05-11 01:03:01 +00:00
19c1a56287
Produce a __debug_frame section on darwin ARM when appropriate.
...
llvm-svn: 131151
2011-05-10 21:04:45 +00:00
3c0447259c
PTX: add test cases for cvt, fneg, and selp
...
Patch by Dan Bailey
llvm-svn: 131128
2011-05-10 14:53:13 +00:00
d724a590e5
X86: Add a bunch of peeps for add and sub of SETB.
...
"b + ((a < b) ? 1 : 0)" compiles into
cmpl %esi, %edi
adcl $0, %esi
instead of
cmpl %esi, %edi
sbbl %eax, %eax
andl $1, %eax
addl %esi, %eax
This saves a register, a false dependency on %eax
(Intel's CPUs still don't ignore it) and it's shorter.
llvm-svn: 131070
2011-05-08 18:36:07 +00:00
a5c889982a
Emit a proper error message when register allocators run out of registers.
...
This can't be just an assertion, users can always write impossible inline
assembly. Such an assembly statement should be included in the error message.
llvm-svn: 131024
2011-05-06 21:58:30 +00:00
11d70b6b32
PTX: add PTX 2.3 language target
...
Patch by Wei-Ren Chen
llvm-svn: 130980
2011-05-06 11:40:36 +00:00
5401962643
Re-revert r130877; it's apparently causing a regression on 197.parser,
...
possibly related to cbnz formation.
llvm-svn: 130977
2011-05-06 05:23:07 +00:00
a4982bddf3
Don't produce a __debug_frame.
...
I tested both gdb on a bootstrapped clang and and the gdb testsuite on OS X (snow leopard)
and both are happy using __eh_frame.
llvm-svn: 130937
2011-05-05 18:43:39 +00:00
441a01a2b8
Avoid extra vreg copies for arguments passed in registers. Specifically, this can make MachineCSE more effective in some cases (especially in small functions). PR8361 / part of rdar://problem/8259436 .
...
llvm-svn: 130928
2011-05-05 16:53:34 +00:00
17d4f9bbcc
Prepare remaining tests for -join-physreg going away.
...
llvm-svn: 130893
2011-05-04 23:54:59 +00:00
369bddf5ad
Fix a batch of x86 tests to be coalescer independent.
...
Most of these tests require a single mov instruction that can come either before
or after a 2-addr instruction. -join-physregs changes the behavior, but the
results are equivalent.
llvm-svn: 130891
2011-05-04 23:54:51 +00:00
dd550305e6
Give this test an explicit register allocator, so that it can work even if
...
the default register allocator is changed.
llvm-svn: 130883
2011-05-04 23:14:02 +00:00
2a40131f6b
SjLj EH could produce a machine basic block that legitimately has more than one
...
landing pad as its successor.
SjLj exception handling jumps to the correct landing pad via a switch statement
that's generated right before code-gen. Loosen the constraint in the machine
instruction verifier to allow for this. Note, this isn't the most rigorous check
since we cannot determine where that switch statement came from. But it's
marginally better than turning this check off when SjLj exceptions are used.
<rdar://problem/9187612>
llvm-svn: 130881
2011-05-04 22:54:05 +00:00
0fe4608af2
Re-commit r130862 with a minor change to avoid an iterator running off the edge in some cases.
...
Original message:
Teach MachineCSE how to do simple cross-block CSE involving physregs. This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .
llvm-svn: 130877
2011-05-04 22:10:36 +00:00
e53ae508ec
This test fails on ARM. The test shouldn't explicitly specify alignment (and alignment 4 is wrong) and requires hard-float.
...
llvm-svn: 130875
2011-05-04 21:57:44 +00:00
3bd79ba856
Back out r130862; it appears to be breaking bootstrap.
...
llvm-svn: 130867
2011-05-04 20:48:42 +00:00
a16fc2fec0
Teach MachineCSE how to do simple cross-block CSE involving physregs. This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .
...
llvm-svn: 130862
2011-05-04 19:54:24 +00:00
28a93a49bb
Fix more register and coalescing dependencies.
...
llvm-svn: 130859
2011-05-04 19:02:11 +00:00
d7fd7bfc31
Explicitly request physreg coalesing for a bunch of Thumb2 unit tests.
...
These tests all follow the same pattern:
mov r2, r0
movs r0, #0
$CMP r2, r1
it eq
moveq r0, #1
bx lr
The first 'mov' can be eliminated by rematerializing 'movs r0, #0' below the
test instruction:
$CMP r0, r1
mov.w r0, #0
it eq
moveq r0, #1
bx lr
So far, only physreg coalescing can do that. The register allocators won't yet
split live ranges just to eliminate copies. They can learn, but this particular
problem is not likely to show up in real code. It only appears because r0 is
used for both the function argument and return value.
llvm-svn: 130858
2011-05-04 19:02:07 +00:00
e7528c45ea
FileCheckize and break dependence on coalescing order.
...
llvm-svn: 130856
2011-05-04 19:02:01 +00:00
067ba3c23c
Explicitly request -join-physregs for some tests that depend on it.
...
llvm-svn: 130855
2011-05-04 19:01:59 +00:00
39ecf816c5
Do not emit location expression size twice.
...
llvm-svn: 130854
2011-05-04 19:00:57 +00:00
3bace5d223
Remove LLVM IR metadata in test case committed in r130847.
...
llvm-svn: 130849
2011-05-04 18:28:36 +00:00
23e8ecf125
Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp.
...
llvm-svn: 130847
2011-05-04 17:54:27 +00:00
f1b401800a
Don't depend on the physreg coalescing order.
...
llvm-svn: 130818
2011-05-04 01:01:47 +00:00
5b5abb4ea1
Don't run this test through -regalloc=basic.
...
The basic allocator is really bad about hinting, so it doesn't eliminate all
copies when physreg joining is disabled.
llvm-svn: 130817
2011-05-04 01:01:44 +00:00
d3b2f44c9d
Fix register-dependent XCore tests
...
llvm-svn: 130816
2011-05-04 01:01:41 +00:00
7f7fc82141
Fix register-dependent test in MSP430.
...
llvm-svn: 130815
2011-05-04 01:01:39 +00:00
51b35f7bb1
Fix a bunch of ARM tests to be register allocation independent.
...
llvm-svn: 130800
2011-05-03 22:31:21 +00:00
db0996c822
Replace the "movnt" intrinsics with a native store + nontemporal metadata bit.
...
<rdar://problem/8460511>
llvm-svn: 130791
2011-05-03 21:11:17 +00:00
93b5cdc5ab
Make the test less likely to fail with minor changes.
...
llvm-svn: 130778
2011-05-03 19:09:32 +00:00
c5242b0e78
Remove test for iOS divmod function, since that is disabled for now.
...
llvm-svn: 130769
2011-05-03 17:54:49 +00:00
Rafael Espindola