Commit Graph

105211 Commits

Author SHA1 Message Date
Daniel Neilson 2574d7cbf6 All libcalls should be considered to be GC-leaf functions.
Summary:
It is possible for some passes to materialize a call to a libcall (ex: ldexp, exp2, etc),
but these passes will not mark the call as a gc-leaf-function. All libcalls are
actually gc-leaf-functions, so we change llvm::callsGCLeafFunction() to tell us that
available libcalls are equivalent to gc-leaf-function calls.

Reviewers: sanjoy, anna, reames

Reviewed By: anna

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35840

llvm-svn: 309291
2017-07-27 16:49:39 +00:00
Florian Hahn 67ddd1d08f [TargetParser] Use enum classes for various ARM kind enums.
Summary:
Using c++11 enum classes ensures that only valid enum values are used
for ArchKind, ProfileKind, VersionKind and ISAKind. This removes the
need for checks that the provided values map to a proper enum value,
allows us to get rid of AK_LAST and prevents comparing values from
different enums. It also removes a bunch of static_cast
from unsigned to enum values and vice versa, at the cost of introducing
static casts to access AArch64ARCHNames and ARMARCHNames by ArchKind.

FPUKind and ArchExtKind are the only remaining old-style enum in
TargetParser.h. I think it's beneficial to keep ArchExtKind as old-style
enum, but FPUKind can be converted too, but this patch is quite big, so
could do this in a follow-up patch. I could also split this patch up a
bit, if people would prefer that.

Reviewers: rengolin, javed.absar, chandlerc, rovka

Reviewed By: rovka

Subscribers: aemerson, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D35882

llvm-svn: 309287
2017-07-27 16:27:56 +00:00
Alexey Bataev 07b96e8e96 [SLP] Outline code for the check that instruction users are part of
vectorization tree, NFC.

llvm-svn: 309284
2017-07-27 15:48:44 +00:00
Simon Pilgrim 64a795c5f5 [SelectionDAG] Avoid repeated calls to getNumOperands in for loop. NFCI.
llvm-svn: 309283
2017-07-27 15:42:21 +00:00
David Blaikie 72c0b1cc1b Fix assert from r309278
llvm-svn: 309281
2017-07-27 15:28:10 +00:00
Adrian Prantl 960e7663f3 remove redundant check
llvm-svn: 309280
2017-07-27 15:24:20 +00:00
David Blaikie 2f0cc477ab ThinLTO: Don't import aliases of any kind (even linkonce_odr)
Summary:
Until a more advanced version of importing can be implemented for
aliases (one that imports an alias as an available_externally definition
of the aliasee), skip the narrow subset of cases that was possible but
came at a cost: aliases of linkonce_odr functions could be imported
because the linkonce_odr function could be safely duplicated from the
source module. This came/comes at the cost of not being able to 'home'
imported linkonce functions (they had to be emitted linkonce_odr in all
the destination modules (even if they weren't used by an alias) rather
than as available_externally - causing extra object size).

Tangentially, this also was the only reason ThinLTO would emit multiple
CUs in to the resulting DWARF - which happens to be a problem for
Fission (there's a fix for this in GDB but not released yet, etc).
(actually it's not the only reason - but I'm sending a patch to fix the
other reason shortly)

There's no reason to believe this particularly narrow alias importing
was especially/meaningfully important, only that it was /possible/ to
implement in this way. When a more general solution is done, it should
still satisfy the DWARF concerns above, since the import will still be
available_externally, and thus not create extra CUs.

Since now all aliases are treated the same, I removed/simplified some
test cases since they were testing corner cases where there are no
longer any corners.

Reviewers: tejohnson, mehdi_amini

Differential Revision: https://reviews.llvm.org/D35875

llvm-svn: 309278
2017-07-27 15:09:06 +00:00
Simon Pilgrim 0d543b5921 [SelectionDAG] Tidyup mask creation. NFCI.
Assign all concat elements to UNDEF and then just replace the first element, instead of copying everything individually.

llvm-svn: 309277
2017-07-27 15:08:53 +00:00
Florian Hahn db479524dd [ARM] Mark labels in skipAlignedDPRCS2Spills as fallthrough (NFC).
The comment at the top of the switch statement indicates that the
fall-through behavior is intentional. By using LLVM_FALLTHROUGH,
-Wimplicit-fallthrough are silenced, which is enabled by default in GCC
7.

llvm-svn: 309272
2017-07-27 14:37:17 +00:00
Andrew V. Tischenko e255526d0b Added cost of ZEROALL and ZEROUPPER instrs in btver2 cpu.
Differential Revision https://reviews.llvm.org/D35834

llvm-svn: 309269
2017-07-27 13:12:08 +00:00
Evgeny Astigeevich 61c1bd5abc [InlineCost, NFC] Change CallAnalyzer::isGEPFree to use TTI::getUserCost instead of TTI::getGEPCost
Currently CallAnalyzer::isGEPFree uses TTI::getGEPCost to check if GEP is free.
TTI::getGEPCost cannot handle cases when GEPs participate in Def-Use dependencies
(see https://reviews.llvm.org/D31186 for example).
There is TTI::getUserCost which can calculate the cost more accurately by
taking dependencies into account.

Differential Revision: https://reviews.llvm.org/D33685

llvm-svn: 309268
2017-07-27 12:49:27 +00:00
Daniel Sanders 8e82af2be6 Re-commit: r309094 [globalisel][tablegen] Fuse the generated tables together.
Summary:
Now that we have control flow in place, fuse the per-rule tables into a
single table. This is a compile-time saving at this point. However, this will
also enable the optimization of a table so that similar instructions can be
tested together, reducing the time spent on the matching the code.

This is NFC in terms of externally visible behaviour but some internals have
changed slightly. State.MIs is no longer reset between each rule that is
attempted because it's not necessary to do so. As a consequence of this the
restriction on the order that instructions are added to State.MIs has been
relaxed to only affect recorded instructions that require new elements to be
added to the vector. GIM_RecordInsn can now write to any element from 1 to
State.MIs.size() instead of just State.MIs.size().

The compile-time regressions from the last commit were caused by the ARM target
including a non-const variable (zero_reg) in the table and therefore generating
an initializer for it. That variable is now const.

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Reviewed By: rovka

Subscribers: kristof.beyls, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D35681

llvm-svn: 309264
2017-07-27 11:03:45 +00:00
Simon Pilgrim afc1ac2735 [X86] Tidyup MaskedLoad/Store mask creation. NFCI.
Assign all concat elements to zero and then just replace the first element, instead of setting them all to null and copying everything in.

llvm-svn: 309261
2017-07-27 10:29:04 +00:00
Mohammed Agabaria cef53dcb6f [TTI] fixing a bug in the isLegalMaskedScatter API
isLegalMaskedScatter called the Gather version which is a bug.
use test case is provided within the patch of AVX2 gathers at: https://reviews.llvm.org/D35772

Differential Revision: https://reviews.llvm.org/D35786

llvm-svn: 309260
2017-07-27 10:28:16 +00:00
Hiroshi Inoue 967dc58ac1 [PowerPC] enable optimizeCompareInstr for branch with static branch hint
In optimizeCompareInstr, a compare instruction is eliminated by using a record form instruction if possible.
If the branch instruction that uses the result of the compare has a static branch hint, the optimization does not happen.
This patch makes this optimization happen regardless of the branch hint by splitting branch hint and branch condition before checking the predicate to identify the possible optimizations.

Differential Revision: https://reviews.llvm.org/D35801

llvm-svn: 309255
2017-07-27 08:14:48 +00:00
Craig Topper 4eda7561b3 [X86] Improve the unknown stepping support for Intel CPUs in getHostCPUName
This patch improves our guessing of unknown Intel CPUs to support Goldmont and skylake-avx512.

Differential Revision: https://reviews.llvm.org/D35161

llvm-svn: 309246
2017-07-27 03:26:52 +00:00
Spyridoula Gravani 73e1796da2 [DWARF] Minor code style modification, no functionality change.
llvm-svn: 309240
2017-07-27 00:59:33 +00:00
David Blaikie 2195e13676 DebugInfo: Ensure imported entities at the top level of an inlined function don't cause degenerate concrete definitions
Local imported entities at the top level of a subprogram were being
handled differently from those in nested scopes - that different
handling would cause pseudo concrete out-of-line definitions to be
created (but without any of their attributes, nor an abstract_origin) in
the case where there was no real concrete definition.

These local imported entities also only appeared in the concrete
definition where those imported entities in nested scopes appear in all
cases (abstract, concrete, and inlined). This change at least makes top
level case handle the same as the others - though there's a FIXME to
improve this to /only/ emit them into the abstract origin (though this
requires more plumbing - like the abstract subprogram and variable
handling that must defer population until the end of the unit to
discover if there is an abstract origin, or only a standalone concrete
definition).

llvm-svn: 309237
2017-07-27 00:06:53 +00:00
Eugene Zelenko 569932d1e6 [Hexagon] Fix expensive checks build bot broken in r309230.
llvm-svn: 309236
2017-07-26 23:56:29 +00:00
Eugene Zelenko efd3d5887b [Hexagon] Partially revert r309230 which caused some build bots failures.
llvm-svn: 309233
2017-07-26 23:45:28 +00:00
Eugene Zelenko e4fc6ee790 [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 309230
2017-07-26 23:20:35 +00:00
Hiroshi Yamauchi 0445e31c88 Fix a comment (test commit).
llvm-svn: 309192
2017-07-26 21:54:43 +00:00
Stanislav Mekhanoshin 3197eb6981 [AMDGPU] Optimize SI_IF lowering for simple if regions
Currently SI_IF results in a s_and_saveexec_b64 followed by s_xor_b64.
The xor is used to extract only the changed bits. In case of a simple
if region where the only use of that value is in the SI_END_CF to
restore the old exec mask, we can omit the xor and perform an or of
the exec mask with the original exec value saved by the
s_and_saveexec_b64.

Differential Revision: https://reviews.llvm.org/D35861

llvm-svn: 309185
2017-07-26 21:29:15 +00:00
Evandro Menezes b3ed4bcb8f [ARM] Minor cosmetic edits (NFC)
Change the order of a case and the description for Exynos Mx processors.

llvm-svn: 309184
2017-07-26 21:28:20 +00:00
Evandro Menezes d192a8ae7d [AArch64] Adjust the cost model for Exynos M1 and M2
Add the information for the scalar reciprocal square root approximation.

llvm-svn: 309183
2017-07-26 21:28:15 +00:00
Wei Ding a126a13bb3 AMDGPU : Widen extending scalar loads to 32-bits.
Differential Revision: http://reviews.llvm.org/D35146

llvm-svn: 309178
2017-07-26 21:07:28 +00:00
Matt Arsenault 894e53d6ac AMDGPU: Fix using SMRD instructions for argument loads in functions
These are not actually uniform values except in kernels.

llvm-svn: 309172
2017-07-26 20:39:42 +00:00
Tom Stellard 55038cd1d3 AMDGPU/GlobalISel: Mark 32-bit G_OR as legal
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D35127

llvm-svn: 309165
2017-07-26 20:00:53 +00:00
Peter Collingbourne 081ffe2ff2 Change CallLoweringInfo::CS to be an ImmutableCallSite instead of a pointer. NFCI.
This was a use-after-free waiting to happen.

llvm-svn: 309159
2017-07-26 19:15:29 +00:00
Adam Nemet ea06e6e865 Migrate SimplifyLibCalls to new OptimizationRemarkEmitter
Summary:
This changes SimplifyLibCalls to use the new OptimizationRemarkEmitter
API.

In fact, as SimplifyLibCalls is only ever called via InstCombine,
(as far as I can tell) the OptimizationRemarkEmitter is added there,
and then passed through to SimplifyLibCalls later.

I have avoided changing any remark text.

This closes PR33787

Patch by Sam Elliott!

Reviewers: anemet, davide

Reviewed By: anemet

Subscribers: davide, mehdi_amini, eraman, fhahn, llvm-commits

Differential Revision: https://reviews.llvm.org/D35608

llvm-svn: 309158
2017-07-26 19:03:18 +00:00
Andrew V. Tischenko d1fefa3d7c This patch returns proper value to indicate the case when instruction throughput can't be calculated.
Differential revision https://reviews.llvm.org/D35831

llvm-svn: 309156
2017-07-26 18:55:14 +00:00
Adrian Prantl 833ad37c90 Do a better job at emitting prefrabricated skeleton CUs.
This is a better fix than r308708 for the problem introduced in
r304020. It restores the skeleton CU testcases modified by that commit
to their original form and most importantly ensures that
frontend-generated skeleton CUs (such as used to point to Clang
modules) come after the regular CUs. This broke for DICompileUnit
nodes that don't have any immediate children because they are now
constructed lazily instead of the order in which they are listed in
!llvm.dbg.cu. After this commit we still don't guarantee that order,
but we do guarantee that empty skeletons come last.

Shipping versions of LLDB are very sensitive to the ordering of
CUs. I'll track a fix for LLDB to be more permissive separately.
This fixes a test failure in the LLDB testsuite.

rdar://problem/33357252

llvm-svn: 309154
2017-07-26 18:48:32 +00:00
Eric Beckmann 6ba5c81387 Unlink nodes instead of copying, to avoid memory problems.
llvm-svn: 309151
2017-07-26 18:33:21 +00:00
Jakub Kuderski c271dea0a7 [Dominators] Move root-finding out of DomTreeBase and simplify it
Summary:
This patch moves root-finding logic from DominatorTreeBase to GenericDomTreeConstruction.h.
It makes the behavior simpler and more consistent by always adding a virtual root to PostDominatorTrees.

Reviewers: dberlin, davide, grosser, sanjoy

Reviewed By: dberlin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35597

llvm-svn: 309146
2017-07-26 18:07:40 +00:00
Rafael Espindola e06e4df8be Simplify. NFC.
llvm-svn: 309141
2017-07-26 17:27:27 +00:00
Florian Hahn 239e4b9301 [Hexagon] Mark raise_relocation_error as NORETURN.
Summary:
This silences a couple of implicit fallthrough warnings with GCC 7.1 in
this file.

Reviewers: colinl, kparzysz

Reviewed By: kparzysz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35889

llvm-svn: 309129
2017-07-26 16:07:51 +00:00
Dehao Chen 641f387cd0 Update the assertion to meet with the changes in r309121. (NFC)
llvm-svn: 309125
2017-07-26 15:47:00 +00:00
Dehao Chen e90d0153ca Make new PM honor -fdebug-info-for-profiling
Summary: The new PM needs to invoke add-discriminator pass when building with -fdebug-info-for-profiling.

Reviewers: chandlerc, davidxl

Reviewed By: chandlerc

Subscribers: sanjoy, llvm-commits

Differential Revision: https://reviews.llvm.org/D35744

llvm-svn: 309121
2017-07-26 15:01:20 +00:00
Stefan Pintilie df0ee9e1b9 [NFC] test commit.
Added a comment to explain how to add a PPCISD node.

llvm-svn: 309114
2017-07-26 13:44:59 +00:00
Yuka Takahashi 66256906c3 [Bash-autocompletion] Show HelpText with possible flags
Summary:
`clang --autocomplete=-std` will show
```
-std:   Language standard to compile for
-std=   Language standard to compile for
-stdlib=        C++ standard library to use
```
after this change.

However, showing HelpText with completion in bash seems super tricky, so
this feature will be used in other shells (fish, zsh...).

Reviewers: v.g.vassilev, teemperor, ruiu

Subscribers: cfe-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D35759

llvm-svn: 309113
2017-07-26 13:36:58 +00:00
Zvi Rackover 092f199188 DAGCombiner: Extend reduceBuildVecToTrunc to handle non-zero offset
Summary:
Adding support for combining power2-strided build_vector's where the
first build_vectori's operand is extracted from a non-zero index.

Example:

 v4i32 build_vector((extract_elt V, 1),
                    (extract_elt V, 3),
                    (extract_elt V, 5),
                    (extract_elt V, 7))
 -->
 v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)

Reviewers: delena, RKSimon, guyblank

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35700

llvm-svn: 309108
2017-07-26 12:57:03 +00:00
Martin Storsjo 0b7bf7a2e3 [COFF, ARM64] Fix symbol offsets in ADRP/ADD/LDR/STR relocations
In COFF, a symbol offset can't be stored in the relocation (as is
done in ELF or MachO), but is stored as the immediate in the
instruction itself. The immediate in the ADRP thus is the symbol
offset in bytes, not in pages. For the PAGEOFFSET_12A/L relocations,
ignore any offset outside of the lowest 12 bits; they won't have any
effect on the ADD/LDR/STR instruction itself but only on the associated
ADRP.

This is similar to how the same issue is handled for MOVW/MOVT
instructions in ELF (see e.g. SVN r307713, and r307728 in lld).

This fixes "fixup out of range" errors while building larger object
files, where temporary symbols end up as a plain section symbol and
an offset, and fixes any cases where the symbol offset mean that
the actual target ended up on a different page than the symbol
itself.

Differential Revision: https://reviews.llvm.org/D35791

llvm-svn: 309105
2017-07-26 11:19:17 +00:00
Diana Picus a5d6518e93 [ARM] GlobalISel: Map G_GLOBAL_VALUE to GPR
A G_GLOBAL_VALUE is basically a pointer, so it should live in the GPR.

llvm-svn: 309101
2017-07-26 11:01:13 +00:00
Diana Picus b1fd784936 [ARM] GlobalISel: Mark G_GLOBAL_VALUE as legal
llvm-svn: 309090
2017-07-26 09:25:15 +00:00
George Rimar 4530dffbc7 [libOption] - Add flag allowing to print options aliases in help text.
By default, we display only options that are not
hidden and have help texts. This patch adds flag
allowing to display aliases that have no help text.
In this case help text of aliased option used instead.

Differential revision: https://reviews.llvm.org/D35476

llvm-svn: 309087
2017-07-26 09:09:56 +00:00
Michael Zuckerman c1918ad571 [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess.
This patch expands the support of lowerInterleavedStore to 32x8i stride 4.

LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=4 VF=32) and we plan to include more patterns in the future. To reach our goal of "more patterns". We include two mask creators. The first function creates shuffle's mask equivalent to unpacklo/unpackhi instructions. The other creator creates mask equivalent to a concat of two half vectors(high/low).

The patch goal is to optimize the following sequence:
At the end of the computation, we have ymm2, ymm0, ymm12 and ymm3 holding
each 32 chars:

c0, c1, , c31
m0, m1, , m31
y0, y1, , y31
k0, k1, ., k31

And these need to be transposed/interleaved and stored like so:

c0 m0 y0 k0 c1 m1 y1 k1 c2 m2 y2 k2 c3 m3 y3 k3 ....

Reviewers:
dorit
Farhana
RKSimon
guyblank
DavidKreitzer

Differential Revision: https://reviews.llvm.org/D34601

llvm-svn: 309086
2017-07-26 08:10:14 +00:00
Zvi Rackover 1b73682243 TargetLowering: Change isShuffleMaskLegal's mask argument type to ArrayRef<int>. NFCI.
Changing mask argument type from const SmallVectorImpl<int>& to
ArrayRef<int>.

This came up in D35700 where a mask is received as an ArrayRef<int> and
we want to pass it to TargetLowering::isShuffleMaskLegal().
Also saves a few lines of code.

llvm-svn: 309085
2017-07-26 08:06:58 +00:00
Michael Zuckerman 60bc7e0f0a [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess part1.
splitting patch D34601 into two part. This part changes the location of two functions. 
The second part will be based on that patch. This was requested by @RKSimon.

Reviewers:
1. dorit	
2. Farhana	
3. RKSimon	
4. guyblank	
5. DavidKreitzer

llvm-svn: 309084
2017-07-26 07:45:02 +00:00
Max Kazantsev f282aed428 [SCEV] Cache results of computeExitLimit
This patch adds a cache for computeExitLimit to save compilation time. A lot of examples of
tests that take extensive time to compile are attached to the bug 33494.

Differential Revision: https://reviews.llvm.org/D35827

llvm-svn: 309080
2017-07-26 04:55:54 +00:00
Craig Topper 050c9c8f83 [X86] Prevent selecting masked aligned load instructions if the load should be non-temporal
Summary: The aligned load predicates don't  suppress themselves if the load is non-temporal the way the unaligned predicates do. For the most part this isn't a problem because the aligned predicates are mostly used for instructions that only load the the non-temporal loads have priority over those. The exception are masked loads.

Reviewers: RKSimon, zvi

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35712

llvm-svn: 309079
2017-07-26 04:31:04 +00:00
Sanjoy Das 469e740f2b [SCEV] Remove unnecessary call to forgetMemoizedResults
`SCEVUnknown::allUsesReplacedWith` does not need to call `forgetMemoizedResults`
since RAUW does a value-equivalent replacement by assumption.  If this
assumption was false then the later setValPtr(New) call would be incorrect too.

This is a non-trivial performance optimization for functions with a large number
of loops since `forgetMemoizedResults` walks all loop backedge taken counts to
see if any of them use the SCEVUnknown being RAUWed.  However, this improvement
is difficult to demonstrate without checking in an excessively large IR file.

llvm-svn: 309072
2017-07-26 01:32:19 +00:00
Eric Beckmann 36be14cbfe Move manifest utils into separate lib, to reduce libxml2 deps.
Summary:
Previously were in support.  Since many many things depend on support,
were all forced to also depend on libxml2, which we only want in a few cases.
This puts all the libxml2 deps in a separate lib to be used only in a few
places.

Reviewers: ruiu, thakis, rnk

Subscribers: mgorny, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D35819

llvm-svn: 309070
2017-07-26 01:21:55 +00:00
Reid Kleckner 037bcd9345 [PDB] Remove stale GSI.h header that I intended to remove in the previous commit
llvm-svn: 309069
2017-07-26 00:58:49 +00:00
Spyridoula Gravani dc635f40bb [DWARF] Generalized verification of .apple_names accelerator table to be applicable to any acceleration table. Added verification for .apple_types, .apple_namespaces and .apple_objc sections.
Differential Revision: https://reviews.llvm.org/D35853

llvm-svn: 309068
2017-07-26 00:52:31 +00:00
Reid Kleckner 14d90fd05c [PDB] Improve GSI hash table dumping for publics and globals
The PDB "symbol stream" actually contains symbol records for the publics
and the globals stream. The globals and publics streams are essentially
hash tables that point into a single stream of records. In order to
match cvdump's behavior, we need to only dump symbol records referenced
from the hash table. This patch implements that, and then implements
global stream dumping, since it's just a subset of public stream
dumping.

Now we shouldn't see S_PROCREF or S_GDATA32 records when dumping
publics, and instead we should see those record in the globals stream.

llvm-svn: 309066
2017-07-26 00:40:36 +00:00
Eric Beckmann b4dbe7231e Reapply "llvm-mt: implement simple merging of manifests, not factoring namespaces.
This time with correct #if.

This reverts commit 9cf4eca0e0383040c1ff1416815c7f649650c2a0.

llvm-svn: 309064
2017-07-26 00:25:12 +00:00
Eugene Zelenko 96d933da4f [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 309062
2017-07-25 23:51:02 +00:00
Wei Mi fc0e245464 Disable loop unswitching for some patterns containing equality comparison with undef.
This is a workaround for the bug described in PR31652 and
http://lists.llvm.org/pipermail/llvm-dev/2017-July/115497.html. The temporary
solution is to add a function EqualityPropUnSafe. In EqualityPropUnSafe, for
some simple patterns we can know the equality comparison may contains undef,
so we regard such comparison as unsafe and will not do loop-unswitching for
them. We also need to disable the select simplification when one of select
operand is undef and its result feeds into equality comparison.

The patch cannot clear the safety issue caused by the bug, but it can suppress
the issue from happening to some extent.

Differential Revision: https://reviews.llvm.org/D35811

llvm-svn: 309059
2017-07-25 23:37:17 +00:00
Adrian Prantl be66271f04 Debug Info: Support fragmented variables in the MMI side table
This reapplies commit r309034 with a bugfix+test for inlined variables.

llvm-svn: 309057
2017-07-25 23:32:59 +00:00
Eric Beckmann 455210e18f Revert "llvm-mt: implement simple merging of manifests, not factoring namespaces."
This reverts commit 813308e240792ca70ed2f998f21df24a5061ada0.

llvm-svn: 309050
2017-07-25 23:06:46 +00:00
Eric Beckmann 780fd409fb llvm-mt: implement simple merging of manifests, not factoring namespaces.
Summary:
Does a simple merge, where mergeable elements are combined, all others
are appended.  Does not apply trickly namespace rules.

Subscribers: llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D35753

llvm-svn: 309047
2017-07-25 22:50:25 +00:00
Eric Christopher 97ae58686f Update the comments on default subtargets based on feedback.
llvm-svn: 309041
2017-07-25 22:21:08 +00:00
Kostya Serebryany 6eab1a8ee6 [libFuzzer] don't disable msan for TracePC::CollectFeatures: this started to cause false positives in msan. No tests for libFuzzer+msan yet -- tests will need to wait until we move libFuzzer to compiler-rt
llvm-svn: 309038
2017-07-25 22:05:31 +00:00
Adrian Prantl b6d5faf2ea Revert "Debug Info: Support fragmented variables in the MMI side table"
This reverts commit r309034 because of a sanitizer issue.

llvm-svn: 309035
2017-07-25 21:50:45 +00:00
Adrian Prantl 3d1ab0cd1e Debug Info: Support fragmented variables in the MMI side table
<rdar://problem/17816343>

llvm-svn: 309034
2017-07-25 21:29:22 +00:00
Marek Olsak 6096f542d1 AMDGPU/SI: Fix Depth and Height computation for SI scheduler
Patch by: Axel Davy

Differential Revision: https://reviews.llvm.org/D34967

llvm-svn: 309028
2017-07-25 20:37:03 +00:00
Marek Olsak e6f74384b1 AMDGPU/SI: Force exports at the end for SI scheduler
Patch by: Axel Davy

Differential Revision: https://reviews.llvm.org/D34965

llvm-svn: 309027
2017-07-25 20:36:58 +00:00
Teresa Johnson a83c3f7879 [LTO] Prevent dead stripping and internalization of symbols with sections
Summary:
ELF linkers generate __start_<secname> and __stop_<secname> symbols
when there is a value in a section <secname> where the name is a valid
C identifier.  If dead stripping determines that the values declared
in section <secname> are dead, and we then internalize (and delete)
such a symbol, programs that reference the corresponding start and end
section symbols will get undefined reference linking errors.

To fix this, add the section name to the IRSymtab entry when a symbol is
defined in a specific section. Then use this in the gold-plugin to mark
the symbol as external and visible from outside the summary when the
section name is a valid C identifier.

Reviewers: pcc

Subscribers: mehdi_amini, inglorion, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D35639

llvm-svn: 309009
2017-07-25 19:42:32 +00:00
Eric Christopher adfe5368ee Revert "This patch enables the usage of constant Enum identifiers within Microsoft style inline assembly statements."
This reverts commit r308966.

llvm-svn: 309005
2017-07-25 19:22:09 +00:00
Nemanja Ivanovic 009016bb70 [PowerPC] Pretty-print CR bits the way the binutils disassembler does
This patch just adds printing of CR bit registers in a more human-readable
form akin to that used by the GNU binutils.

Differential Revision: https://reviews.llvm.org/D31494

llvm-svn: 309001
2017-07-25 18:26:35 +00:00
Nemanja Ivanovic 864c953773 [PowerPC] - Recommit r304907 now that the issue has been fixed
This is just a recommit since the issue that the commit exposed is now
resolved.

llvm-svn: 308995
2017-07-25 17:54:51 +00:00
Simon Pilgrim 18b97f78fe [X86][CGP] Reduce memcmp() expansion to 2 load pairs (PR33914)
D35067/rL308322 attempted to support up to 4 load pairs for memcmp inlining which resulted in regressions for some optimized libc memcmp implementations (PR33914).

Until we can match these more optimal cases, this patch reduces the memcmp expansion to a maximum of 2 load pairs (which matches what we do for -Os).

This patch should be considered for the 5.0.0 release branch as well

Differential Revision: https://reviews.llvm.org/D35830

llvm-svn: 308986
2017-07-25 17:04:37 +00:00
Simon Pilgrim 6d59933175 [DAG] Move DAGCombiner::GetDemandedBits to SelectionDAG
This patch moves the DAGCombiner::GetDemandedBits function to SelectionDAG::GetDemandedBits as a first step towards making it easier for targets to get to the source of any demanded bits without the limitations of SimplifyDemandedBits.

Differential Revision: https://reviews.llvm.org/D35841

llvm-svn: 308983
2017-07-25 16:36:44 +00:00
Fedor Sergeev 7856a3205f [Sparc] invalid adjustments in TLS_LE/TLS_LDO relocations removed
Summary:
Some SPARC TLS relocations were applying nontrivial adjustments
to zero value, leading to unexpected non-zero values in ELF and then
Solaris linker failures.

Getting rid of these adjustments.

Fixes PR33825.

Reviewers: rafael, asb, jyknight

Subscribers: joerg, jyknight, llvm-commits

Differential Revision: https://reviews.llvm.org/D35567

llvm-svn: 308978
2017-07-25 15:28:28 +00:00
Andrew V. Tischenko 32e9b1ad0b X86 Asm uses assertions instead of proper diagnostic. This patch fixes that.
Differential Revision: https://reviews.llvm.org/D35115

llvm-svn: 308972
2017-07-25 13:05:12 +00:00
Chandler Carruth 1dc34c6d80 [LIR] Teach LIR to avoid extending the BE count prior to adding one to
it when safe.

Very often the BE count is the trip count minus one, and the plus one
here should fold with that minus one. But because the BE count might in
theory be UINT_MAX or some such, adding one before we extend could in
some cases wrap to zero and break when we scale things.

This patch checks to see if it would be safe to add one because the
specific case that would cause this is guarded for prior to entering the
preheader. This should handle essentially all of the common loop idioms
coming out of C/C++ code once canonicalized by LLVM.

Before this patch, both forms of loop in the added test cases ended up
subtracting one from the size, extending it, scaling it up by 8 and then
adding 8 back onto it. This is really silly, and it turns out made it
all the way into generated code very often, so this is a surprisingly
important cleanup to do.

Many thanks to Sanjoy for showing me how to do this with SCEV.

Differential Revision: https://reviews.llvm.org/D35758

llvm-svn: 308968
2017-07-25 10:48:32 +00:00
Matan Haroush 2f21017be2 This patch enables the usage of constant Enum identifiers within Microsoft style inline assembly statements.
Differential Revision:
https://reviews.llvm.org/D33277
https://reviews.llvm.org/D33278

llvm-svn: 308966
2017-07-25 10:44:09 +00:00
Francois Pichet 82bf3de606 Fix endianness bug in DAGCombiner::visitTRUNCATE and visitEXTRACT_VECTOR_ELT
Summary:
Do not assume little endian architecture in DAGCombiner::visitTRUNCATE and DAGCombiner::visitEXTRACT_VECTOR_ELT.
PR33682

Reviewers: hfinkel, sdardis, RKSimon

Reviewed By: sdardis, RKSimon

Subscribers: uabelho, RKSimon, sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D34990

llvm-svn: 308960
2017-07-25 09:40:35 +00:00
Sam Parker 19a08e42a8 [ARM] Enable partial and runtime unrolling
Enable runtime and partial loop unrolling of simple loops without
calls on M-class cores. The thresholds are calculated based on
whether the target is Thumb or Thumb-2.

Differential Revision: https://reviews.llvm.org/D34619

llvm-svn: 308956
2017-07-25 08:51:30 +00:00
Martin Storsjo b9ff4191a1 [COFF] ARM64 support for COFFImportFile
A test will be committed separately in the lld repo.

Differential Revision: https://reviews.llvm.org/D35766

llvm-svn: 308951
2017-07-25 06:05:49 +00:00
Martin Storsjo 8cb3667541 [AArch64] Reserve a 16 byte aligned amount of fixed stack for win64 varargs
Create a dummy 8 byte fixed object for the unused slot below the first
stored vararg.

Alternative ideas tested but skipped: One could try to align the whole
fixed object to 16, but I haven't found how to add an offset to the stack
frame used in LowerWin64_VASTART.

If only the size of the fixed stack object size is padded but not the offset, via
MFI.CreateFixedObject(alignTo(GPRSaveSize, 16), -(int)GPRSaveSize, false),
PrologEpilogInserter crashes due to "Attempted to reset backwards range!".

This fixes misconceptions about where registers are spilled, since
AArch64FrameLowering.cpp assumes the offset from fixed objects is
aligned to 16 bytes (and the Win64 case there already manually aligns
the offset to 16 bytes).

This fixes cases where local stack allocations could overwrite callee
saved registers on the stack.

Differential Revision: https://reviews.llvm.org/D35720

llvm-svn: 308950
2017-07-25 05:20:01 +00:00
NAKAMURA Takumi 7ddaf3cf88 DWARFVerifier.cpp: Fix -m32 in r308928. Use PRIx64.
llvm-svn: 308949
2017-07-25 05:03:17 +00:00
Kostya Serebryany 6f7befd10f [libFuzzer] make one test faster, fix compiler warnings in tests
llvm-svn: 308945
2017-07-25 02:09:46 +00:00
Kostya Serebryany c485ca05ac [sanitizer-coverage] simplify the code, NFC
llvm-svn: 308944
2017-07-25 02:07:38 +00:00
Eugene Zelenko 48666a694c [Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 308936
2017-07-24 23:16:33 +00:00
Spyridoula Gravani e0ba415740 [DWARF] Added verification check for die ranges. If highPC is an address, then it should be greater than lowPC for each range.
Differential Revision: https://reviews.llvm.org/D35733

llvm-svn: 308928
2017-07-24 21:04:11 +00:00
Reid Kleckner c990b5d916 Revert "[X86][InlineAsm][Ms Compatibility]Prefer variable name over a register when the two collides"
This reverts r308867 and r308866.

It broke the sanitizer-windows buildbot on C++ code similar to the
following:

  namespace cl { }
  void f() {
    __asm {
      mov al, cl
    }
  }

t.cpp(4,13):  error: unexpected namespace name 'cl': expected expression
    mov al, cl
            ^

In this case, MSVC parses 'cl' as a register, not a namespace.

llvm-svn: 308926
2017-07-24 20:48:15 +00:00
Kevin Enderby 8100cdeddf Small tweak to one check in error handling to the dyld compact export
entries in libObject (done in r308690).  In the case when the last node
has no children setting State.Current = Children + 1; where that would be past
Trie.end() is actually ok since the pointer is not used with zero children.

rdar://33490512

llvm-svn: 308924
2017-07-24 20:33:41 +00:00
Krzysztof Parzyszek 1fd0c7e598 [Hexagon] Recognize C4_cmpneqi, C4_cmpltei and C4_cmplteui in NewValueJump
llvm-svn: 308914
2017-07-24 19:35:48 +00:00
Rafael Espindola 87c3f4a938 Move DWARFSectionMap to a .cpp file.
Thanks to Paul Robinson for the suggestion.

llvm-svn: 308913
2017-07-24 19:34:26 +00:00
George Karpenkov 9bc64acf90 Revert "Revert "[libFuzzer] Add a dependency on symbolizer from libFuzzer tests""
This reverts commit 15425f2bc6eac6249ee957a2a280511306c07547.

Should work now that atos is a default symbolizer on Darwin.

llvm-svn: 308910
2017-07-24 18:38:14 +00:00
Matt Arsenault 5fbc87021e RA: Replace asserts related to empty live intervals
These don't exactly assert the same thing anymore, and
allow empty live intervals with non-empty uses.

Removed in r308808 and r308813.

llvm-svn: 308906
2017-07-24 18:07:55 +00:00
Evandro Menezes 29ffb0e66a [AArch64] Adjust the cost model for Exynos M1 and M2
Fine tune the resources in a couple of ASIMD loads.

llvm-svn: 308904
2017-07-24 18:06:16 +00:00
Matt Arsenault 7052a6a505 AMDGPU: Fix allocating pseudo-registers
There's no need for these to be part of a class since
they are immediately replaced. New unreachable hit in
existing tests.'

llvm-svn: 308903
2017-07-24 18:06:15 +00:00
Tim Northover fe6be421a7 Revert "Debug: handle dumping the D language."
Reid beat me to it.

llvm-svn: 308902
2017-07-24 17:47:46 +00:00
Tim Northover c7bd8255b9 Debug: handle dumping the D language.
Mostly just to silence a warning about an unhandled case. There don't seem to
be any tests for this operator (at least that I could find).

llvm-svn: 308901
2017-07-24 17:39:44 +00:00
Reid Kleckner e2ba971302 Add missing case to switch
llvm-svn: 308894
2017-07-24 16:30:44 +00:00
Benjamin Kramer fc638c11bb [CodeGenPrepare] Cut off FindAllMemoryUses if there are too many uses.
This avoids excessive compile time. The case I'm looking at is
Function.cpp from an old version of LLVM that still had the giant memcmp
string matcher in it. Before r308322 this compiled in about 2 minutes,
after it, clang takes infinite* time to compile it. With this patch
we're at 5 min, which is still bad but this is a pathological case.

The cut off at 20 uses was chosen by looking at other cut-offs in LLVM
for user scanning. It's probably too high, but does the job and is very
unlikely to regress anything.

Fixes PR33900.

* I'm impatient and aborted after 15 minutes, on the bug report it was
  killed after 2h.

llvm-svn: 308891
2017-07-24 16:18:09 +00:00
Reid Kleckner 898ddf61c0 [codeview] Emit 'D' as the cv source language for D code
This matches DMD:
522263965c/src/ddmd/backend/cv8.c (L199)

Fixes PR33899.

llvm-svn: 308890
2017-07-24 16:16:42 +00:00
Reid Kleckner 7f6b2534fb Format some case labels and shrink an anonymous namespace NFC
llvm-svn: 308889
2017-07-24 16:16:17 +00:00
Florian Hahn f66efd6181 [LoopInterchange] Update code to use range-based for loops (NFC).
Summary:
The remaining non range-based for loops do not iterate over full ranges,
so leave them as they are.

Reviewers: karthikthecool, blitz.opensource, mcrosier, mkuper, aemerson

Reviewed By: aemerson

Subscribers: aemerson, mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D35777

llvm-svn: 308872
2017-07-24 11:41:30 +00:00
Ayman Musa b16ce777e3 [X86][AVX512] Add patterns for masked AVX512 floating point compare instructions that were missing.
patterns were missed by D33188. Adding for completion.
+Updating test.

Differential Revesion: https://reviews.llvm.org/D35179

llvm-svn: 308868
2017-07-24 08:10:32 +00:00
Coby Tayree c48388d3d3 [X86][InlineAsm][Ms Compatibility]Prefer variable name over a register when the two collides
On MS-style, the following snippet:

int eax;
__asm mov eax, ebx

should yield loading of ebx, into the location pointed by the variable eax

This patch sees to it.

Currently, a reg-to-reg move would have been invoked.

clang: D34740

Differential Revision: https://reviews.llvm.org/D34739

llvm-svn: 308866
2017-07-24 07:04:55 +00:00
Dylan McKay 6c5c6aa9d8 [AVR] Remove the instrumentation pass
I have a much better way of running integration tests now.

https://github.com/dylanmckay/avr-test-suite

llvm-svn: 308857
2017-07-23 23:39:11 +00:00
Petr Hosek 710479cede [CodeGen][X86] Fuchsia supports sincos* libcalls and sin+cos->sincos optimization
Patch by Roland McGrath

Differential Revision: https://reviews.llvm.org/D35748

llvm-svn: 308854
2017-07-23 22:30:00 +00:00
Chad Rosier 9b2b4c961a [AArch64] Redundant Copy Elimination - remove more zero copies.
This patch removes unnecessary zero copies in BBs that are targets of b.eq/b.ne
and we know the result of the compare instruction is zero.  For example,

BB#0:
  subs w0, w1, w2
  str w0, [x1]
  b.ne .LBB0_2
BB#1:
  mov w0, wzr  ; <-- redundant
  str w0, [x2]
.LBB0_2

Differential Revision: https://reviews.llvm.org/D35075

llvm-svn: 308849
2017-07-23 16:38:08 +00:00
Max Kazantsev 0e9e0796f4 [SCEV] Limit max size of AddRecExpr during evolving
When SCEV calculates product of two SCEVAddRecs from the same loop, it
tries to combine them into one big AddRecExpr. If the sizes of the initial
SCEVs were `S1` and `S2`, the size of their product is `S1 + S2 - 1`, and every
operand of the resulting SCEV is combined from operands of initial SCEV and
has much higher complexity than they have.

As result, if we try to calculate something like:
  %x1 = {a,+,b}
  %x2 = mul i32 %x1, %x1
  %x3 = mul i32 %x2, %x1
  %x4 = mul i32 %x3, %x2
  ...
The size of such SCEVs grows as `2^N`, and the arguments
become more and more complex as we go forth. This leads
to long compilation and huge memory consumption.

This patch sets a limit after which we don't try to combine two
`SCEVAddRecExpr`s into one. By default, max allowed size of the
resulting AddRecExpr is set to 16.

Differential Revision: https://reviews.llvm.org/D35664

llvm-svn: 308847
2017-07-23 15:40:19 +00:00
NAKAMURA Takumi 4c29ca4b9b RuntimeDyldELF.cpp: Prune unused "TargetRegistry.h"
llvm-svn: 308846
2017-07-23 11:47:22 +00:00
Craig Topper 07a7d56144 [X86] Add some hasSideEffects=0 flags.
llvm-svn: 308835
2017-07-23 03:59:39 +00:00
Craig Topper 6912d7faa3 [X86] Add patterns for memory forms of SARX/SHLX/SHRX with careful complexity adjustment to keep shift by immediate using the legacy instructions.
These patterns were only missing to favor using the legacy instructions when the shift was a constant. With careful adjustment of the pattern complexity we can make sure the immediate instructions still have priority over these patterns.

llvm-svn: 308834
2017-07-23 03:59:37 +00:00
Nirav Dave 4e6dcf73f9 [DAG] Fix typo preventing some stores merges to truncated stores.
Check the actual memory type stored and not the extended value size
when considering if truncated store merge is worthwhile.

Reviewers: efriedma, RKSimon, spatel, jyknight

Reviewed By: efriedma

Subscribers: llvm-commits, nhaehnle

Differential Revision: https://reviews.llvm.org/D35623

llvm-svn: 308833
2017-07-23 02:06:28 +00:00
Craig Topper abfe380f9a [X86] Add nopq instruction which is a rex encoded version of nopl for gas compatibility.
llvm-svn: 308818
2017-07-22 01:30:53 +00:00
Craig Topper e88aef4b5f [X86] Add register form of NOPL and NOPW for assembler/disassembler.
Fixes PR32805.

llvm-svn: 308817
2017-07-22 01:30:51 +00:00
Matt Arsenault 416d755675 AMDGPU: Remove leftover td file
All of the instructions were moved out of this a while ago,
so it's just a useless comment now.

llvm-svn: 308815
2017-07-22 00:40:46 +00:00
Matt Arsenault c5d1e503e1 RA: Remove another assert on empty intervals
This case is similar to the one fixed in r308808,
except when rematerializing.

Fixes bug 33884.

llvm-svn: 308813
2017-07-22 00:24:01 +00:00
Kostya Serebryany 8cb63ec20b [libFuzzer] reimplement experimental_len_control=1: bump the temporary max_len every time we failed to find new coverage during the last 1000 runs and 1 second. Also fix FileToVector to not load unfinished files
llvm-svn: 308811
2017-07-22 00:10:29 +00:00
Matt Arsenault 6a963f76ca RA: Remove assert on empty live intervals
This is possible if there is an undef use when
splitting the vreg during spilling.

Fixes bug 33620.

llvm-svn: 308808
2017-07-21 23:56:13 +00:00
Erich Keane d8f61f8f7e Remove Bitrig: LLVM Changes
Bitrig code has been merged back to OpenBSD, thus the OS has been abandoned.

Differential Revision: https://reviews.llvm.org/D35707

llvm-svn: 308799
2017-07-21 22:48:47 +00:00
David Blaikie b8cc0544d2 [ProfData] Detect if zlib is available
As discussed on [1], if the profile is compressed and llvm-profdata is not built with zlib support, the error message is not informative. Give a better error message if zlib is not available.

[1] http://lists.llvm.org/pipermail/llvm-dev/2017-July/115571.html

Reviewers: davidxl, dblaikie

Differential Revision: https://reviews.llvm.org/D35586

llvm-svn: 308789
2017-07-21 21:41:15 +00:00
Eugene Zelenko 38c02bc7f5 [Analysis] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 308787
2017-07-21 21:37:46 +00:00
Xinliang David Li 8e43698cf1 [PGOInstr] Add a debug print
llvm-svn: 308785
2017-07-21 21:36:25 +00:00
Farhana Aleen e4a89a6462 X86InterleaveAccess: A fix for bug33826
Reviewers: DavidKreitzer

Differential Revision: https://reviews.llvm.org/D35638

llvm-svn: 308784
2017-07-21 21:35:00 +00:00
Konstantin Zhuravlyov e9a5a77ee3 AMDGPU: Implement memory model
llvm-svn: 308781
2017-07-21 21:19:23 +00:00
Guozhi Wei e0094ce22e [PPC] Add Defs = [CARRY] to MIR SRADI_32
MIR SRADI uses instruction template XSForm_1rc which declares Defs = [CARRY]. But MIR SRADI_32 uses instruction template XSForm_1, and it doesn't declare such implicit definition. With patch D33720 it causes wrong code generation for perl.

This patch adds the implicit definition.

Differential Revision: https://reviews.llvm.org/D35699

llvm-svn: 308780
2017-07-21 21:06:08 +00:00
Konstantin Zhuravlyov 070d88e335 AMDGPU: Introduce maybeAtomic instruction flag
Testing is in the follow up change

llvm-svn: 308779
2017-07-21 21:05:45 +00:00
Matt Arsenault f014d7cbde AMDGPU: Preserve undef flag in eliminateFrameIndex
Fixes verifier errors in some call tests.
Not sure why we haven't run into this before.

Test split into separate patch for once
call support is committed.

llvm-svn: 308774
2017-07-21 19:31:44 +00:00
Xin Tong 495a3022da [DAGCombiner] Update comment. NFC
llvm-svn: 308772
2017-07-21 19:10:19 +00:00
Matt Arsenault 0ed39d329d AMDGPU: Partially fix improper reliance on memoperands
There are 2 more places doing this, but I'm not sure
what they are doing and don't make any sense to me

llvm-svn: 308770
2017-07-21 18:54:54 +00:00
Matt Arsenault 6ab9ea9614 AMDGPU: Don't track lgkmcnt for global_/scratch_ instructions
llvm-svn: 308766
2017-07-21 18:34:51 +00:00
Reid Kleckner c85041fe00 Fix DebugInfo/PDB build by adding missing changes
llvm-svn: 308765
2017-07-21 18:32:00 +00:00
Reid Kleckner 686f121a5d [PDB] Dump extra info about the publics stream
This includes the hash table, the address map, and the thunk table and
section offset table. The last two are only used for incremental
linking, which LLD doesn't support, so they are less interesting. The
hash table is particularly important to get right, since this is the one
of the streams that debuggers use to translate addresses to symbols.

llvm-svn: 308764
2017-07-21 18:28:55 +00:00
Matt Arsenault 37a58e03c7 AMDGPU: Fix getMemOpBaseRegImmOfs for flat with offsets
llvm-svn: 308762
2017-07-21 18:06:36 +00:00
Krzysztof Parzyszek 3ad0d01e9e [Hexagon] Add inline-asm constraint 'a' for modifier register class
For example
  asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory")

llvm-svn: 308761
2017-07-21 17:51:27 +00:00
Haojie Wang 1dec57d5b0 ThinLTO Minimized Bitcode File Size Reduction
Summary: Currently the ThinLTO minimized bitcode file only strip the debug info, but there is still a lot of information in the minimized bit code file that will be not used for thin linker. In this patch, most of the extra information is striped to reduce the minimized bitcode file. Now only ModuleVersion, ModuleInfo, ModuleGlobalValueSummary, ModuleHash, Symtab and Strtab are left. Now the minimized bitcode file size is reduced to 15%-30% of the debug info stripped bitcode file size.

Reviewers: danielcdh, tejohnson, pcc

Reviewed By: pcc

Subscribers: mehdi_amini, aprantl, inglorion, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D35334

llvm-svn: 308760
2017-07-21 17:25:20 +00:00
Simon Dardis 0310eb7a67 [mips] Support -membedded-data and fix a related bug
-membedded-data changes the location of constant data from the .sdata to
the .rodata section. Previously it was (incorrectly) always located in the
.rodata section.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D35686

llvm-svn: 308758
2017-07-21 17:19:00 +00:00
Anna Thomas 5c07a4c5de [RuntimeUnroll] NFC: Add a profitability function for mutliexit loop
Separated out the profitability from the safety analysis for multiexit
loop unrolling. Currently, this is an NFC because profitability is true
only if the unroll-runtime-multi-exit is set to true (off-by-default).

This is to ease adding the profitability heuristic up for review at
D35380.

llvm-svn: 308753
2017-07-21 16:30:38 +00:00
Dinar Temirbulatov 4403b2b668 [SLPVectorizer] Replace E->Scalars to VL0 at vectorizeTree and move comment, NFCI.
llvm-svn: 308750
2017-07-21 16:02:56 +00:00
Matt Arsenault ca7b0a1777 AMDGPU: Add instruction definitions for some scratch_* instructions
Omit atomics for now since they probably aren't useful.

llvm-svn: 308747
2017-07-21 15:36:16 +00:00
Dinar Temirbulatov b2a9a23213 [SLPVectorizer] buildTree_rec replace cast<Instruction>(VL[0]) to VL0, NFCI.
llvm-svn: 308745
2017-07-21 15:31:54 +00:00
Petar Jovanovic 9494258223 [mips] Enable IAS by default for Android MIPS64
Follow up to r306280 in Clang.
Enable IAS by default for Android MIPS64 (uses N64 ABI).

Differential Revision: https://reviews.llvm.org/D35482

llvm-svn: 308742
2017-07-21 14:25:42 +00:00
Dmitry Preobrazhensky abf2839478 [AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifier
See bug 33591: https://bugs.llvm.org//show_bug.cgi?id=33591

Reviewers: vpykhtin, artem.tamazov, SamWot, arsenm

Differential Revision: https://reviews.llvm.org/D35424

llvm-svn: 308740
2017-07-21 13:54:11 +00:00
Dinar Temirbulatov 3206409d91 [SLPVectorizer] Change canReuseExtract function parameter Opcode from unsigned to Value *, NFCI.
llvm-svn: 308739
2017-07-21 13:32:36 +00:00
Jonas Paulsson 024e319489 [SystemZ, LoopStrengthReduce]
This patch makes LSR generate better code for SystemZ in the cases of memory
intrinsics, Load->Store pairs or comparison of immediate with memory.

In order to achieve this, the following common code changes were made:

 * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if
 LSR should do instruction-based addressing evaluations by calling
 isLegalAddressingMode() with the Instruction pointers.
 * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy
 as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address,
 not just loads or stores.

SystemZ changes:

 * isLSRCostLess() implemented with Insns first, and without ImmCost.
 * New function supportedAddressingMode() that is a helper for TTI methods
 looking at Instructions passed via pointers.

Review: Ulrich Weigand, Quentin Colombet
https://reviews.llvm.org/D35262
https://reviews.llvm.org/D35049

llvm-svn: 308729
2017-07-21 11:59:37 +00:00
Simon Pilgrim 32c377a1cf [X86][SSE] Add pre-AVX2 support for (i32 bitcast(v32i1)) -> 2xMOVMSK
Currently we only support (i32 bitcast(v32i1)) using the AVX2 VPMOVMSKB ymm instruction.

This patch adds support for splitting pre-AVX2 targets into 2 x (V)PMOVMSKB xmm instructions and merging the integer results.

In future we could probably generalize this to handle more cases.

Differential Revision: https://reviews.llvm.org/D35303

llvm-svn: 308723
2017-07-21 09:58:50 +00:00
Philipp Schaad a81d23030f Commit access test
llvm-svn: 308712
2017-07-21 03:51:01 +00:00
Adrian Prantl 65e7ca995d Debug Info: Don't strip clang module skeleton CUs.
This corrects a (hopefully :-) accidental side-effect of r304020.

rdar://problem/33442618

llvm-svn: 308708
2017-07-21 01:24:05 +00:00
Spyridoula Gravani c6ef9873ac [DWARF] Generalized verification of .debug_abbrev to be applicable to both .debug_abbrev and .debug_abbrev.dwo sections.
Differential Revision: https://reviews.llvm.org/D35698

llvm-svn: 308703
2017-07-21 00:51:32 +00:00
Craig Topper 31140ade70 [AVX-512] Fix a bug that prevented some non-temporal loads from using the movntdqa instruction.
The bitconverts here had an input type of 128-bits and an output type of 256 bits. The input type should also have been 256 bits.

llvm-svn: 308702
2017-07-21 00:40:42 +00:00
Evandro Menezes 55459609c8 [AArch64] Adjust the cost model for Exynos M1 and M2
Add the cost for the EXT instructions and explicitly add the cost for a few
instructions that were implied by the coarse model.

llvm-svn: 308697
2017-07-20 23:41:50 +00:00
Kevin Enderby 3e95bd2239 Add error handling to the dyld compact export entries in libObject.
lld needs a matching change for this will be my next commit.
Expect it to fail build until that matching commit is picked up by the bots.

Like the changes in r296527 for dyld bind entires and the changes in
r298883 for lazy bind, weak bind and rebase entries the export
entries are the last of the dyld compact info to have error handling added.

This follows the model of iterators that can fail that Lang Hanes
designed when fixing the problem for bad archives r275316 (or r275361).

So that iterating through the exports now terminates if there is an error
and returns an llvm::Error with an error message in all cases for malformed
input.

This change provides the plumbing for the error handling, all the needed
testing of error conditions and test cases for all of the unique error messages.

llvm-svn: 308690
2017-07-20 23:08:41 +00:00
Tim Northover 7b6d66c0c9 Recommit: GlobalISel: select G_EXTRACT and G_INSERT instructions on AArch64.
It revealed a bug in the Localizer pass which has now been fixed.

This includes the fix for SUBREG_TO_REG committed separately last time.

llvm-svn: 308688
2017-07-20 22:58:38 +00:00
Tim Northover 071d77a51f GlobalISel: stop localizer putting constants before EH_LABELs
If the localizer pass puts one of its constants before the label that tells the
unwinder "jump here to handle your exception" then control-flow will skip it,
leaving uninitialized registers at runtime. That's bad.

llvm-svn: 308687
2017-07-20 22:58:26 +00:00
Eric Beckmann 7d50c389c4 Implement parsing and writing of a single xml manifest file.
Summary: Implement parsing and writing of a single xml manifest file.

Subscribers: mgorny, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D35425

llvm-svn: 308679
2017-07-20 21:42:04 +00:00
Artem Belevich d7a73824e4 [NVPTX] Add lowering of i128 params.
The patch adds support of i128 params lowering. The changes are quite trivial to
support i128 as a "special case" of integer type. With this patch, we lower i128
params the same way as aggregates of size 16 bytes: .param .b8 _ [16].

Currently, NVPTX can't deal with the 128 bit integers:
* in some cases because of failed assertions like
  ValVTs.size() == OutVals.size() && "Bad return value decomposition"
* in other cases emitting PTX with .i128 or .u128 types (which are not valid [1])
  [1] http://docs.nvidia.com/cuda/parallel-thread-execution/index.html#fundamental-types

Differential Revision: https://reviews.llvm.org/D34555
Patch by: Denys Zariaiev (denys.zariaiev@gmail.com)

llvm-svn: 308675
2017-07-20 21:16:03 +00:00
Matt Arsenault e5456ce5e5 AMDGPU: Rename _RTN atomic instructions
Move the _RTN to the end of the name. It reads
better if the other addressing mode components
line up with the non-RTN version. It is also
more convenient to define saddr variants of
FLAT atomics to have the RTN last, and it is
good to have a consistent naming scheme.

llvm-svn: 308674
2017-07-20 21:06:04 +00:00
Matt Arsenault db78273b6e Add an ID field to StackObjects
On AMDGPU SGPR spills are really spilled to another register.
The spiller creates the spills to new frame index objects,
which is used as a placeholder.

This will eventually be replaced with a reference to a position
in a VGPR to write to and the frame index deleted. It is
most likely not a real stack location that can be shared
with another stack object.

This is a problem when StackSlotColoring decides it should
combine a frame index used for a normal VGPR spill with
a real stack location and a frame index used for an SGPR.

Add an ID field so that StackSlotColoring has a way
of knowing the different frame index types are
incompatible.

llvm-svn: 308673
2017-07-20 21:03:45 +00:00
Artem Belevich fef0804e35 Changed EOL back to LF. NFC.
llvm-svn: 308671
2017-07-20 20:57:51 +00:00
Matt Morehouse 9e689792b2 Generate error reports when a fuzz target exits.
Summary:
Implements https://github.com/google/sanitizers/issues/835.

Flush stdout before exiting in test cases.

Since the atexit hook is used for exit reports, pending prints to
stdout can be lost if they aren't flushed before calling exit().

Expect tests to have non-zero exit code if exit() is called.

Reviewers: vitalybuka, kcc

Reviewed By: kcc

Subscribers: eraman, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D35602

llvm-svn: 308669
2017-07-20 20:43:39 +00:00
Davide Italiano 0c8d26c312 [PGO] Move the PGOInstrumentation pass to new OptRemark API.
This fixes PR33791.

llvm-svn: 308668
2017-07-20 20:43:05 +00:00
Francis Visoiu Mistrih 39aa5dbbf5 [PEI] Fix refactoring from r308664
llvm-svn: 308666
2017-07-20 20:31:44 +00:00
Mandeep Singh Grang d41ac895bb [COFF, ARM64, CodeView] Add support to emit CodeView debug info for ARM64 COFF
Reviewers: compnerd, ruiu, rnk, zturner

Reviewed By: rnk

Subscribers: majnemer, aemerson, aprantl, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D35518

llvm-svn: 308665
2017-07-20 20:20:00 +00:00
Francis Visoiu Mistrih 631f6b888c [PEI] Separate saving and restoring CSRs into different functions. NFC
Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores.

This is mostly useful for future shrink-wrapping improvements where we
want to save / restore a specific part of the CSRs in a specific block.

Differential Revision: https://reviews.llvm.org/D35644

llvm-svn: 308664
2017-07-20 20:17:17 +00:00
Kostya Serebryany d1b731d57b [libFuzzer] delete stale code
llvm-svn: 308663
2017-07-20 20:15:13 +00:00
James Y Knight bb76d48d59 [SPARC] Clean up the support for disabling fsmuld and fmuls instructions.
Summary:
Also enable no-fsmuld for sparcv7 (which doesn't have the
instruction).

The previous code which used a post-processing pass to do this was
unnecessary; disabling the instruction is entirely sufficient.

Reviewers: jacob_hansen, ekedaigle

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35576

llvm-svn: 308661
2017-07-20 20:09:11 +00:00
Krzysztof Parzyszek f3a778d757 Implement LaneBitmask::getNumLanes and LaneBitmask::getHighestLane
This should eliminate most uses of countPopulation and Log2_32 on
the lane mask values.

llvm-svn: 308658
2017-07-20 19:43:19 +00:00
Craig Topper 27c12e088e [X86] Allow masks with more than 6 bits set on the x << (y & mask) optimization for the 64-bit memory shifts.
llvm-svn: 308657
2017-07-20 19:29:58 +00:00
Krzysztof Parzyszek e9f0c1e031 Use LaneBitmask::getLane in a few more places
llvm-svn: 308655
2017-07-20 19:15:56 +00:00
Kostya Serebryany a763be3d5f [libFuzzer] make sure CheckExitOnSrcPosOrItem is called after the new input is saved to the corpus
llvm-svn: 308653
2017-07-20 18:53:25 +00:00
Nirav Dave 4aa51c3af1 [DAG] Commit missed nit cleanup from r308617. NFC.
llvm-svn: 308645
2017-07-20 18:07:57 +00:00
Peter Collingbourne 6f6788b99c LowerTypeTests: Drop function type metadata only if we're going to replace it.
Previously we were (mis)handling jump table members with a prevailing
definition in a full LTO module and a non-prevailing definition in a
ThinLTO module by dropping type metadata on those functions entirely,
which would cause type tests involving such functions to fail.

This patch causes us to drop metadata only if we are about to replace
it with metadata from cfi.functions.

We also want to replace metadata for available_externally functions,
which can arise in the opposite scenario (prevailing ThinLTO
definition, non-prevailing full LTO definition). The simplest way
to handle that is to remove the definition; there's little value in
keeping it around at this point (i.e. after most optimization passes
have already run) and later code will try to use the function's linkage
to create an alias, which would result in invalid IR if the function
is available_externally.

Fixes PR33832.

Differential Revision: https://reviews.llvm.org/D35604

llvm-svn: 308642
2017-07-20 18:02:05 +00:00
Matt Arsenault c37fe66ec5 AMDGPU: Add encoding for carryless add/sub instructions
llvm-svn: 308639
2017-07-20 17:42:47 +00:00
Matt Arsenault f65c5ac9c9 AMDGPU: Add encodings for global atomics
llvm-svn: 308638
2017-07-20 17:31:56 +00:00
Nirav Dave df86d2d008 [DAG] Handle missing transform in fold of value extension case.
Summary:
When pushing an extension of a constant bitwise operator on a load
into the load, change other uses of the load value if they exist to
prevent the old load from persisting.

Reviewers: spatel, RKSimon, efriedma

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35030

llvm-svn: 308618
2017-07-20 13:57:32 +00:00
Nirav Dave 77cc6f23b9 [DAG] Optimize away degenerate INSERT_VECTOR_ELT nodes.
Summary:
Add missing vector write of vector read reduction, i.e.:

(insert_vector_elt x (extract_vector_elt x idx) idx) to x

Reviewers: spatel, RKSimon, efriedma

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35563

llvm-svn: 308617
2017-07-20 13:48:17 +00:00
Stefan Maksimovic be0bc71e02 Reland r308585
Builder clang-x86_64-linux-abi-test apparently failed due
to a spurious error unrelated to the changes r308585
introduced.

llvm-svn: 308612
2017-07-20 13:08:18 +00:00
Javed Absar e9599e39fe [ARM] Simplify ExpandPseudoInst. NFC.
Remove headers not required and convert to range-loop

Reviewed by: @mcrosier
Differential Revision: https://reviews.llvm.org/D35626

llvm-svn: 308607
2017-07-20 12:35:37 +00:00
Simon Atanasyan fb953926b1 [mips] Support `long_call/far/near` attributes passed by front-end
This patch adds handling of the `long_call`, `far`, and `near`
attributes passed by front-end. The patch depends on D35479.

Differential revision: https://reviews.llvm.org/D35480.

llvm-svn: 308606
2017-07-20 12:19:26 +00:00
Diana Picus 7534b28291 Revert "GlobalISel: select G_EXTRACT and G_INSERT instructions on AArch64."
This reverts commit 36c6a2ea9669bc3bb695928529a85d12d1d3e3f9 because it
broke the test-suite on the GlobalISel bot.

llvm-svn: 308603
2017-07-20 11:36:03 +00:00
Simon Pilgrim 2911296f10 [DAGCombiner] Match ISD::SRL non-uniform constant vectors patterns using predicates.
Use predicate matchers introduced in D35492 to match more ISD::SRL constant folds

llvm-svn: 308602
2017-07-20 11:03:30 +00:00
Simon Pilgrim b9ff25df59 Remove trailing whitespace. NFCI.
llvm-svn: 308601
2017-07-20 10:43:52 +00:00
Simon Pilgrim 7ff0e49d8c [DAGCombiner] Match ISD::SRA non-uniform constant vectors patterns using predicates.
Use predicate matchers introduced in D35492 to match more ISD::SRA constant folds

llvm-svn: 308600
2017-07-20 10:43:05 +00:00
Simon Pilgrim 9d7863b935 [DAGCombiner] Match non-uniform constant vectors using predicates.
Most combines currently recognise scalar and splat-vector constants, but not non-uniform vector constants.

This patch introduces a matching mechanism that uses predicates to check against BUILD_VECTOR of ConstantSDNode, as well as scalar ConstantSDNode cases.

I've changed a couple of predicates to demonstrate - the combine-shl changes add currently unsupported cases, while the MatchRotate replaces an existing mechanism.

Differential Revision: https://reviews.llvm.org/D35492

llvm-svn: 308598
2017-07-20 10:13:40 +00:00
Stefan Maksimovic 3793a82b28 Revert r308585
Builder clang-x86_64-linux-abi-test seems to fail after this change

llvm-svn: 308597
2017-07-20 09:57:14 +00:00
Stefan Maksimovic 8539f77bc3 [mips] Fix fp select machine verifier errors
Introduced FSELECT node necesary when lowering ISD::SELECT
which has i32, f64, f64 as its operands.
SEL_D instruction required that its output and first operand
of a SELECT node, which it used, have matching types.
MTC1_D64 node introduced to aid FSELECT lowering.

This fixes machine verifier errors on following tests:
CodeGen/Mips/llvm-ir/select-dbl.ll
CodeGen/Mips/llvm-ir/select-flt.ll
CodeGen/Mips/select.ll

Differential Revision: https://reviews.llvm.org/D35408

llvm-svn: 308595
2017-07-20 09:21:10 +00:00
Craig Topper 33225ef314 [X86] Use SARX/SHLX/SHLX instructions for (shift x (and y, (BitWidth-1)))
Fixes PR33841.

llvm-svn: 308591
2017-07-20 06:19:55 +00:00
Matt Arsenault 04004716ff AMDGPU: Correct encoding for global instructions
The soffset field needs to be be set to 0x7f to disable it,
not 0. 0 is interpreted as an SGPR offset.

This should be enough to get basic usage of the global instructions
working. Technically it is possible to use an SGPR_32 offset,
but I'm not sure if it's correct with 64-bit pointers, but
that is not handled now. This should also be cleaned up
to be more similar to how different MUBUF modes are handled,
and to have InstrMappings between the different types.

llvm-svn: 308583
2017-07-20 05:17:54 +00:00
David Majnemer e6bb895ab5 [LICM] Make sinkRegion and hoistRegion non-recursive
Large CFGs can cause us to blow up the stack because we would have a
recursive step for each basic block in a region.

Instead, create a worklist and iterate it. This limits the stack usage
to something more manageable.

Differential Revision: https://reviews.llvm.org/D35609

llvm-svn: 308582
2017-07-20 03:27:02 +00:00
Francis Visoiu Mistrih 185b2e3d32 Revert "[PEI] Simplify handling of targets with no phys regs. NFC"
This reverts commit ce30ab6e5598f3c24f59ad016dc9526bc9a1d450.

sanitizer-ppc64le-linux seems to segfault when testing the sanitizers.

llvm-svn: 308581
2017-07-20 02:47:05 +00:00
Francis Visoiu Mistrih b3ddc1686b Revert "[PEI] Separate saving and restoring CSRs into different functions. NFC"
This reverts commit 540f6a26ae932469804a379ce9a8cbe715d59c23.

sanitizer-ppc64le-linux seems to segfault when testing the sanitizers.

llvm-svn: 308580
2017-07-20 02:47:04 +00:00
Spyridoula Gravani 364b535234 [DWARF] Added check that verifies that no abbreviation declaration has more than one attribute with the same name.
SUMMARY

This patch adds a verification check on the abbreviation declarations in the .debug_abbrev section.
The check makes sure that no abbreviation declaration has more than one attributes with the same name.

Differential Revision: https://reviews.llvm.org/D35643

llvm-svn: 308579
2017-07-20 02:06:52 +00:00
Kostya Serebryany e55828c740 [libFuzzer] prototype implementation of recursion-depth coverage features (commented out; real implementation needs to use inlined instrumentation)
llvm-svn: 308577
2017-07-20 01:35:17 +00:00
Matthias Braun c20b3383b7 Support, IR, ADT: Check nullptr after allocation with malloc/realloc or calloc
As a follow up of the bad alloc handler patch, this patch introduces nullptr checks on pointers returned from the
malloc/realloc/calloc functions.  In addition some memory size assignments  are moved behind the allocation
of the corresponding memory to fulfill exception safe memory management (RAII).

patch by Klaus Kretzschmar

Differential Revision: https://reviews.llvm.org/D35414

llvm-svn: 308576
2017-07-20 01:30:39 +00:00
Francis Visoiu Mistrih 303e5df4e2 [PEI] Separate saving and restoring CSRs into different functions. NFC
Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores.

This is mostly useful for future shrink-wrapping improvements where we
want to save / restore a specific part of the CSRs in a specific block.

Differential Revision: https://reviews.llvm.org/D35644

llvm-svn: 308573
2017-07-20 00:58:37 +00:00
Matt Arsenault d62fe83005 Replace -print-whole-regmask with a threshold.
The previous flag/default of printing everything is
not helpful when there are thousands of registers
in the mask.

llvm-svn: 308572
2017-07-20 00:37:31 +00:00
Kostya Serebryany 15cc3713d3 [libFuzzer] add DeepRecursionTest, inspired by https://guidovranken.wordpress.com/2017/07/08/libfuzzer-gv-new-techniques-for-dramatically-faster-fuzzing/ (Stack-depth-guided fuzzing). libFuzzer does not solve it yet.
llvm-svn: 308571
2017-07-20 00:37:08 +00:00
Reid Kleckner 6326639721 Try to deflake fuzzer-oom.test on Windows
llvm-svn: 308568
2017-07-20 00:11:39 +00:00
Francis Visoiu Mistrih ede08ef314 Revert "[PEI] Separate saving and restoring CSRs into different functions. NFC"
This reverts commit a84d1fa6847e70ebf63594d41a00b473c941bd72.

llvm-svn: 308562
2017-07-20 00:08:02 +00:00
Kostya Serebryany f1bafd9bf6 [libFuzzer] simplify two more tests
llvm-svn: 308560
2017-07-19 23:52:54 +00:00
Francis Visoiu Mistrih 9b97a31870 [AsmPrinter] Constify needsCFIMoves. NFC
llvm-svn: 308557
2017-07-19 23:47:33 +00:00
Francis Visoiu Mistrih 52042aa21e [PEI] Add basic opt-remarks support
Add optimization remarks support to the PrologueEpilogueInserter. For
now, emit the stack size as an analysis remark, but more additions wrt
shrink-wrapping may be added.

https://reviews.llvm.org/D35645

llvm-svn: 308556
2017-07-19 23:47:32 +00:00
Francis Visoiu Mistrih a1f21bca46 [PEI] Simplify handling of targets with no phys regs. NFC
Make doSpillCalleeSavedRegs a member function, instead of passing most
of the members of PEI as arguments.

Differential Revision: https://reviews.llvm.org/D35642

llvm-svn: 308555
2017-07-19 23:47:32 +00:00
Francis Visoiu Mistrih 3b7bbdbdd5 [PEI] Separate saving and restoring CSRs into different functions. NFC
Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores.

This is mostly useful for future shrink-wrapping improvements where we
want to save / restore a specific part of the CSRs in a specific block.

Differential Revision: https://reviews.llvm.org/D35644

llvm-svn: 308554
2017-07-19 23:47:31 +00:00
Kostya Serebryany a168af7b5f [libFuzzer] change several tests to not limit the max len: with reduce_inputs=1 they are now fast enough even w/o this
llvm-svn: 308553
2017-07-19 23:45:46 +00:00
Reid Kleckner 388f88070e Use llvm::make_unique once more to avoid ADL ambiguity with std::make_unique
llvm-svn: 308552
2017-07-19 23:42:53 +00:00
Rafael Espindola 2e942fbaef Use llvm::make_unique to try to fix the windows build.
llvm-svn: 308551
2017-07-19 23:38:54 +00:00
Rafael Espindola 3ee9e11acb Remove some leftover DWARFContextInMemory.
Not sure how I missed these on the previous commit.

llvm-svn: 308550
2017-07-19 23:34:59 +00:00
Reid Kleckner b3283b740f Fix fuzzer-flags.test on Windows
The optional external function callbacks have to be exported in order
for them to be called. The test was failing because libFuzzer wasn't
calling LLVMFuzzerInitialize.

We can reconsider if this is the best way to mark these optional
callbacks exported later.

llvm-svn: 308548
2017-07-19 23:22:06 +00:00
Rafael Espindola c398e67fed Use delegation instead of inheritance.
This changes DwarfContext to delegate to DwarfObject instead of having
pure virtual methods.

With this DwarfContextInMemory is replaced with an implementation of
DwarfObject that is local to a .cpp file.

llvm-svn: 308543
2017-07-19 22:27:28 +00:00
Tim Northover 967d4aa7a0 GlobalISel: partially revert r308540.
An unfinished and untested implementation of ISel for G_UNMERGE_VALUES crept in
by mistake.

llvm-svn: 308542
2017-07-19 22:11:08 +00:00
Kostya Serebryany 4a27b70ed5 [libFuzzer] enable reduce_inputs=1 by default (seems to be a big win usually)
llvm-svn: 308541
2017-07-19 22:10:30 +00:00
Tim Northover 0e0b3c97dd GlobalISel: fix SUBREG_TO_REG implementation.
The first argument needs to be an immediate rather than a register. Should fix
some crashes in the verifier bot.

llvm-svn: 308540
2017-07-19 22:08:08 +00:00
Derek Schuff 36454afab5 Move Runtime libcall definitions to a .def file
This will allow eliminating the duplication of the names, and allow adding
extra information such as signatures in a future commit.

Differential Revision: https://reviews.llvm.org/D35522

llvm-svn: 308531
2017-07-19 21:53:30 +00:00
Davide Italiano 4b8c8eae32 [TRE] Move to the new OptRemark API.
Fixes PR33788.

Differential Revision:  https://reviews.llvm.org/D35570

llvm-svn: 308524
2017-07-19 21:13:22 +00:00
Petr Hosek eb04da3a56 [yaml2obj][ELF] Add support for program headers
This change adds basic support for program headers.

I need to do some testing which requires generating program headers but
I can't use ld.lld or clang to produce programs that have headers. I'd
also like to test some strange things that those programs may never
produce.

Patch by Jake Ehrlich

Differential Revision: https://reviews.llvm.org/D35276

llvm-svn: 308520
2017-07-19 20:38:46 +00:00
Martin Storsjo b2e9fcfca4 [AArch64] Force relocations for all ADRP instructions
This generalizes an existing fix from ELF to MachO and COFF.

Test that an ADRP to a local symbol whose offset is known at assembly
time still produces relocations, both for MachO and COFF. Test that
an ADRP without a @page modifier on MachO fails (previously it
didn't).

Differential Revision: https://reviews.llvm.org/D35544

llvm-svn: 308518
2017-07-19 20:14:32 +00:00
Martin Storsjo 2ff5f5d681 [AArch64, COFF] Interpret .align as power of two for COFF as well
Differential Revision: https://reviews.llvm.org/D35545

llvm-svn: 308517
2017-07-19 20:14:24 +00:00
Wolfgang Pieb e018bbd835 Fixing an issue with the initialization of LexicalScopes objects when mixing debug
and non-debug units.

Patch by Andrea DiBiagio.

Differential Revision:  https://reviews.llvm.org/D35637

llvm-svn: 308513
2017-07-19 19:36:40 +00:00
Krzysztof Parzyszek ac01994db9 [Hexagon] Fix a bug in r308502: post-inc offset is always 0
llvm-svn: 308510
2017-07-19 19:17:32 +00:00
Peter Collingbourne e776dd9ca2 LTO: Export functions referenced by the CFI jump table.
If the LowerTypeTests pass decides to add a function to a jump
table for CFI, it will add its name to the set cfiFunctionDefs,
which among other things will cause the function to be renamed in
the ThinLTO backend.

One other thing that we must do with such functions is to not
internalize them, because the jump table in the full LTO object will
contain a reference to the actual function body in the ThinLTO object.

This patch handles that by ensuring that we export any functions
whose names appear in the cfiFunctionDefs set.

Fixes PR33831.

Differential Revision: https://reviews.llvm.org/D35605

llvm-svn: 308504
2017-07-19 18:18:19 +00:00
Davide Italiano 5fc5d0a406 [X86] Don't try to scale down if that exceeds the bitwidth.
Fixes the crash reported in PR33844.

llvm-svn: 308503
2017-07-19 18:09:46 +00:00
Krzysztof Parzyszek 3fce9d9c49 [Hexagon] Handle subregisters in areMemAccessesTriviallyDisjoint
llvm-svn: 308502
2017-07-19 18:03:46 +00:00
Peter Collingbourne 93fdaca5ac ThinLTOBitcodeWriter: Do not rewrite intrinsic functions when splitting modules.
Changing the type of an intrinsic may invalidate the IR.

Differential Revision: https://reviews.llvm.org/D35593

llvm-svn: 308500
2017-07-19 17:54:29 +00:00
Tim Northover d59fbec8e2 GlobalISel: select G_EXTRACT and G_INSERT instructions on AArch64.
llvm-svn: 308493
2017-07-19 16:47:07 +00:00
Krzysztof Parzyszek b449dc189a [Hexagon] Handle subregisters and non-immediates in getBaseAndOffset
llvm-svn: 308485
2017-07-19 15:39:28 +00:00
Hans Wennborg 8276556b62 Defeat a GCC -Wunused-result warning
It was warning like:

../llvm-project/llvm/lib/Support/ErrorHandling.cpp:172:51: warning:
ignoring return value of ‘ssize_t write(int, const void*, size_t)’,
         declared with attribute warn_unused_result [-Wunused-result]
            (void)::write(2, OOMMessage, strlen(OOMMessage));

Work around the warning by storing the return value in a variable and
casting that to void instead. We already did this for the other write()
call in this file.

llvm-svn: 308483
2017-07-19 15:03:38 +00:00
Simon Pilgrim c77e262260 {DAGCombine] Convert (Val & Mask) == Mask to Mask.isSubsetof(Val). NFCI.
llvm-svn: 308460
2017-07-19 13:39:58 +00:00
Javed Absar 2cb0c95031 [ARM] Unify handling of M-Class system registers
This patch cleans up and fixes issues in the M-Class system register handling:

1. It defines the system registers and the encoding (SYSm values) in one place:
   a new ARMSystemRegister.td using SearchableTable, thereby removing the
   hand-coded values which existed in multiple places.

2. Some system registers e.g. BASEPRI_MAX_NS which do not exist were being allowed!
   Ref: ARMv6/7/8M architecture reference manual.

Reviewed by: @t.p.northover, @olist01, @john.brawn
Differential Revision: https://reviews.llvm.org/D35209

llvm-svn: 308456
2017-07-19 12:57:16 +00:00
Simon Pilgrim e5c7925c5e [X86][XOP] Use default AVX2 lowering for v4i64 ashr by splat constants
XOP shifts only support 128-bit vectors, so we were ending up with less optimal codegen requiring constants

llvm-svn: 308430
2017-07-19 10:29:31 +00:00
Jonas Paulsson 4690193dec [SystemZ] Minor fixing in SystemZScheduleZ14.td
Some minor corrections for recently added instructions.

Review: Ulrich Weigand
llvm-svn: 308429
2017-07-19 10:19:21 +00:00
Dinar Temirbulatov a61f4b8957 [LoopUtils] Add an extra parameter OpValue to propagateIRFlags function,
If OpValue is non-null, we only consider operations similar to OpValue
when intersecting.

Differential Revision: https://reviews.llvm.org/D35292

llvm-svn: 308428
2017-07-19 10:02:07 +00:00
Balaram Makam b05a55787a [SimplifyCFG] Defer folding unconditional branches to LateSimplifyCFG if it can destroy canonical loop structure.
Summary:
When simplifying unconditional branches from empty blocks, we pre-test if the
BB belongs to a set of loop headers and keep the block to prevent passes from
destroying canonical loop structure. However, the current algorithm fails if
the destination of the branch is a loop header. Especially when such a loop's
latch block is folded into loop header it results in additional backedges and
LoopSimplify turns it into a nested loop which prevent later optimizations
from being applied (e.g., loop  unrolling and loop interleaving).

This patch augments the existing algorithm by further checking if the
destination of the branch belongs to a set of loop headers and defer
eliminating it if yes to LateSimplifyCFG.

Fixes PR33605: https://bugs.llvm.org/show_bug.cgi?id=33605

Reviewers: efriedma, mcrosier, pacxx, hsung, davidxl

Reviewed By: efriedma

Subscribers: ashutosh.nema, gberry, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D35411

llvm-svn: 308422
2017-07-19 08:53:34 +00:00
Ayal Zaks 8c452d76ed [LV] Test once if vector trip count is zero, instead of twice
Generate a single test to decide if there are enough iterations to jump to the
vectorized loop, or else go to the scalar remainder loop. This test compares the
Scalar Trip Count: if STC < VF * UF go to the scalar loop. If
requiresScalarEpilogue() holds, at-least one iteration must remain scalar; the
rest can be used to form vector iterations. So in this case the test checks
instead if (STC - 1) < VF * UF by comparing STC <= VF * UF, and going to the
scalar loop if so. Otherwise the vector loop is entered for at-least one vector
iteration.

This test covers the case where incrementing the backedge-taken count will
overflow leading to an incorrect trip count of zero. In this (rare) case we will
also avoid the vector loop and jump to the scalar loop.

This patch simplifies the existing tests and effectively removes the basic-block
originally named "min.iters.checked", leaving the single test in block
"vector.ph".

Original observation and initial patch by Evgeny Stupachenko.

Differential Revision: https://reviews.llvm.org/D34150

llvm-svn: 308421
2017-07-19 05:16:39 +00:00
Serguei Katkov 4ea855ebe5 [CGP] Allow cycles during Phi traversal in OptimizaMemoryInst
Allowing cycles in Phi traversal increases the scope of optimize memory instruction
in case we are in loop.

The added test shows an example of enabling optimization inside a loop.

Reviewers: loladiro, spatel, efriedma
Reviewed By: efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35294

llvm-svn: 308419
2017-07-19 04:49:17 +00:00
Chandler Carruth 06a86301a1 [PM/LCG] Follow-up fix to r308088 to handle deletion of library
functions.

In the prior commit, we provide ordering to the LCG between functions
and library function definitions that they might begin to call through
transformations. But we still would delete these library functions from
the call graph if they became dead during inlining.

While this immediately crashed, it also exposed a loss of information.
We shouldn't remove definitions of library functions that can still
usefully participate in the LCG-powered CGSCC optimization process. If
new call edges are formed, we want to have definitions to be called.

We can still remove these functions if truly dead using global-dce, etc,
but removing them during the CGSCC walk is premature.

This fixes a crash in the new PM when optimizing some unusual libraries
that end up with "internal" lib functions such as the code in the "R"
language's libraries.

llvm-svn: 308417
2017-07-19 04:12:25 +00:00
James Y Knight 0e4ce61d2a [SPARC] Add missing variable initialization after r308343.
llvm-svn: 308415
2017-07-19 04:08:42 +00:00
Craig Topper 106b5b6856 AMD znver1 Initial Scheduler model
Summary:
This patch adds the following
1. Adds a skeleton scheduler model for AMD Znver1.
2. Introduces the znver1 execution units and pipes.
3. Caters the instructions based on the generic scheduler classes.
4. Further additions to the scheduler model with instruction itineraries will be carried out incrementally based on
        a. Instructions types
        b. Registers used
5. Since itineraries are not added based on instructions, throughput information are bound to change when incremental changes are added.
6. Scheduler testcases are modified accordingly to suit the new model.

Patch by Ganesh Gopalasubramanian. With minor formatting tweaks from me.

Reviewers: craig.topper, RKSimon

Subscribers: javed.absar, shivaram, ddibyend, vprasad

Differential Revision: https://reviews.llvm.org/D35293

llvm-svn: 308411
2017-07-19 02:45:14 +00:00
Saleem Abdulrasool 08e5f6853b Object: preserve more information about DEF file
Preserve the actual library name as provided by the user.  This is
required to properly replicate link's behaviour about the module import
name handling.  This requires an associated change to lld for updating
the tests for the proper behaviour for the import library module name
handling in various cases.

Associated tests will be part of the lld change.

llvm-svn: 308406
2017-07-19 02:01:22 +00:00
Weiming Zhao 984f1dc338 Fix DebugLoc propagation for unreachable LoadInst
Summary: Currently, when GVN creates a load and when InstCombine creates a new store for unreachable Load, the DebugLoc info gets lost.

Reviewers: dberlin, davide, aprantl

Reviewed By: aprantl

Subscribers: davide, llvm-commits

Differential Revision: https://reviews.llvm.org/D34639

llvm-svn: 308404
2017-07-19 01:27:24 +00:00
Adrian Prantl d63bfd218b Debug Info: Add a file: field to DIImportedEntity.
DIImportedEntity has a line number, but not a file field. To determine
the decl_line/decl_file we combine the line number from the
DIImportedEntity with the file from the DIImportedEntity's scope. This
does not work correctly when the parent scope is a DINamespace or a
DIModule, both of which do not have a source file.

This patch adds a file field to DIImportedEntity to unambiguously
identify the source location of the using/import declaration.  Most
testcase updates are mechanical, the interesting one is the removal of
the FIXME in test/DebugInfo/Generic/namespace.ll.

This fixes PR33822. See https://bugs.llvm.org/show_bug.cgi?id=33822
for more context.

<rdar://problem/33357889>
https://bugs.llvm.org/show_bug.cgi?id=33822

Differential Revision: https://reviews.llvm.org/D35583

llvm-svn: 308398
2017-07-19 00:09:54 +00:00
Evandro Menezes e8411cba87 [AArch64] Adjust the feature set for Exynos M2
Add fusion of AES operations.

llvm-svn: 308388
2017-07-18 22:51:25 +00:00
Vitaly Buka 74443f0778 [asan] Copy arguments passed by value into explicit allocas for ASan
Summary:
  ASan determines the stack layout from alloca instructions. Since
arguments marked as "byval" do not have an explicit alloca instruction, ASan
does not produce red zones for them. This commit produces an explicit alloca
instruction and copies the byval argument into the allocated memory so that red
zones are produced.

  Submitted on behalf of @morehouse (Matt Morehouse)

  Reviewers: eugenis, vitalybuka

  Reviewed By: eugenis

  Subscribers: hiraditya, llvm-commits

  Differential Revision: https://reviews.llvm.org/D34789

llvm-svn: 308387
2017-07-18 22:28:03 +00:00
Saleem Abdulrasool 0f83a89414 Object: rename parameter from DLLName to ImportName
When I originally wrote this code, I neglected the fact that the import
library may be created for executables.  This name is not the name of
the DLL, but rather the name for the imported module.  It will be
embedded into the IAT/ILT reference.  Rename it to make it more obvious.
NFC.

llvm-svn: 308384
2017-07-18 22:11:01 +00:00
Saleem Abdulrasool e234901a84 Object: handle extensions properly in def files
When given an extension as part of the `library` directive in a def
file, the extension is preserved/honoured by link/lib.  Behave similarly
when parsing the def file.  This requires checking if a native extension
is provided as a keyword parameter.  If no extension is present, append
a standard `.dll` or `.exe` extension.

This is best tested via lld, and I will add tests there as a follow up.

llvm-svn: 308383
2017-07-18 22:11:00 +00:00
Martell Malone 1079ef8dfe llvm: add llvm-dlltool support to the archiver
A PE COFF spec compliant import library generator.
Intended to be used with mingw-w64.

Supports:
PE COFF spec (section 8, Import Library Format)
PE COFF spec (Aux Format 3: Weak Externals)

Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D29892

This reapplies rL308329, which was reverted in rL308374

llvm-svn: 308379
2017-07-18 21:26:38 +00:00
Lang Hames 2306f9c5d2 [RuntimeDyld][MachO/ARM] Don't add a redundant relocation entry.
We only need to add this entry once for it to be fixed up.

llvm-svn: 308375
2017-07-18 21:12:03 +00:00
Rui Ueyama 6db83a3af3 Revert r308329: llvm: add llvm-dlltool support to the archiver
This reverts commit r308329 because it broke buildbots.

llvm-svn: 308374
2017-07-18 21:07:13 +00:00
Martell Malone 9b6e9899f2 llvm: fix -Wcast gcc warn error from rL308329
llvm-svn: 308360
2017-07-18 20:58:21 +00:00
Mandeep Singh Grang d857b4ca98 [COFF, ARM64] Reserve X18 register by default
Reviewers: compnerd, rnk, ruiu, mstorsjo

Reviewed By: mstorsjo

Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D35531

llvm-svn: 308358
2017-07-18 20:41:33 +00:00
Nirav Dave d839749ae8 [DAG] Improve Aliasing of operations to static alloca
Re-recommiting after landing DAG extension-crash fix.

Recommiting after adding check to avoid miscomputing alias information
on addresses of the same base but different subindices.

Memory accesses offset from frame indices may alias, e.g., we
may merge write from function arguments passed on the stack when they
are contiguous. As a result, when checking aliasing, we consider the
underlying frame index's offset from the stack pointer.

Static allocs are realized as stack objects in SelectionDAG, but its
offset is not set until post-DAG causing DAGCombiner's alias check to
consider access to static allocas to frequently alias. Modify isAlias
to consider access between static allocas and access from other frame
objects to be considered aliasing.

Many test changes are included here. Most are fixes for tests which
indirectly relied on our aliasing ability and needed to be modified to
preserve their original intent.

The remaining tests have minor improvements due to relaxed
ordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.ll
which has a minor degradation dispite though the pre-legalized DAG is
improved.

Reviewers: rnk, mkuper, jonpa, hfinkel, uweigand

Reviewed By: rnk

Subscribers: sdardis, nemanjai, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33345

llvm-svn: 308350
2017-07-18 20:06:24 +00:00
Nirav Dave 041b87758a [DAG] Reverse node replacement in extension operation. NFCI.
Reorder replacements to be user first in preparation for multi-level
folding to premptively avoid inadvertantly deleting later nodes from
sharing found from replacement.

llvm-svn: 308348
2017-07-18 19:49:20 +00:00