maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
84,194 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

190 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen 8d042c0269 Fix a few places that depended on the numeric value of subreg indices. 
Add assertions in places that depend on consecutive indices.

llvm-svn: 104510
 2010-05-24 17:13:28 +00:00
Jakob Stoklund Olesen 6c47d6423c Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums 
from ARMRegisterInfo.h

llvm-svn: 104508
 2010-05-24 16:54:32 +00:00
Evan Cheng dd7f566597 Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. 
llvm-svn: 104111
 2010-05-19 06:07:03 +00:00
Evan Cheng cd04ed3533 vmov of immediates are trivially re-materializable. 
llvm-svn: 103982
 2010-05-17 21:54:50 +00:00
Anton Korobeynikov 497d831966 Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td 
llvm-svn: 103903
 2010-05-16 09:15:36 +00:00
Evan Cheng cd67c21407 Added a QQQQ register file to model 4-consecutive Q registers. 
llvm-svn: 103760
 2010-05-14 02:13:41 +00:00
Evan Cheng 9de7cfe3f4 Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ. 
llvm-svn: 103692
 2010-05-13 01:12:06 +00:00
Evan Cheng 79efd71962 Mark some pattern-less instructions as neverHasSideEffects. 
llvm-svn: 103683
 2010-05-13 00:16:46 +00:00
Evan Cheng 86eb22976f Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. 
llvm-svn: 103235
 2010-05-07 02:04:02 +00:00
Evan Cheng ddc93c7e04 Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers. 
llvm-svn: 103218
 2010-05-07 00:24:52 +00:00
Evan Cheng 31cdcd46d6 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170. 
llvm-svn: 103172
 2010-05-06 06:36:08 +00:00
Eric Christopher 9feb1bb117 Revert r103156 since it was breaking the build bots. 
Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td

llvm-svn: 103159
 2010-05-06 02:29:06 +00:00
Evan Cheng 8f99a1c6b4 Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. 
llvm-svn: 103156
 2010-05-06 01:52:03 +00:00
Anton Korobeynikov 4d36f8890f More fixes for itins 
llvm-svn: 100662
 2010-04-07 18:21:10 +00:00
Anton Korobeynikov ceb54d5ab0 Fix invalid itins for 32-bit varians of VMLAL and friends 
llvm-svn: 100661
 2010-04-07 18:21:04 +00:00
Anton Korobeynikov a248becd6c Fix itins for VABA 
llvm-svn: 100657
 2010-04-07 18:20:42 +00:00
Anton Korobeynikov a3e4989ad8 Correct VMVN itinerary: operand is read in the second cycle, not in the first. 
llvm-svn: 100656
 2010-04-07 18:20:36 +00:00
Anton Korobeynikov 140a65ce0b More A9 itineraries 
llvm-svn: 100655
 2010-04-07 18:20:29 +00:00
Anton Korobeynikov 1a1af5a830 Correct itinerary class for VPADD 
llvm-svn: 100654
 2010-04-07 18:20:24 +00:00
Anton Korobeynikov 4650fd5fc6 VP{MAX, MIN} are of IIC_VSUBi4D itin class as well. 
llvm-svn: 100653
 2010-04-07 18:20:18 +00:00
Anton Korobeynikov 7d4fad5942 VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. 
llvm-svn: 100652
 2010-04-07 18:20:13 +00:00
Johnny Chen c86256fa5d Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions. 
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd).  The table is specified via
a list of vectors, which can be:

{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}

llvm-svn: 99789
 2010-03-29 01:14:22 +00:00
Chris Lattner 3dad5fbeb9 fix integer negates to use the proper type for the zero vectors, 
this also depends on the new "bitconvert dropping" behavior just
added to tblgen.

llvm-svn: 99757
 2010-03-28 08:39:10 +00:00
Chris Lattner 6c223ee0e9 fix vnot matching to explicitly specify the type of the 
input to be v8i8 or v16i8, which buildvectors get canonicalized to.

This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.

llvm-svn: 99754
 2010-03-28 08:08:07 +00:00
Bob Wilson 0f8a02830a Fix indentation. 
llvm-svn: 99705
 2010-03-27 04:01:23 +00:00
Bob Wilson cf603fb1c5 Add a format argument to the N3V and N3VX classes, removing the N3Vf class. 
llvm-svn: 99704
 2010-03-27 03:56:52 +00:00
Johnny Chen 6094cdab9f Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set 
it as the format for the appropriate N3V*SL*<> classes.  These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.

Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):

	vmlal.s32	q3, d2, d10[0]

llvm-svn: 99690
 2010-03-27 01:03:13 +00:00
Johnny Chen 93acfbf441 Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified 
to now take a format argument.  N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.

llvm-svn: 99676
 2010-03-26 23:49:07 +00:00
Johnny Chen 0b57de3c4c Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8} 
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.

Modify VEXTd and VEXTq classes to use the format.

llvm-svn: 99659
 2010-03-26 22:28:56 +00:00
Johnny Chen 2cf04957c2 Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not 
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).

Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from.  N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.

Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.

llvm-svn: 99655
 2010-03-26 21:26:28 +00:00
Johnny Chen 5d4e917d9f Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily 
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field.  The Vd, Vm fields are interpreted
the same between the two, though.

See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.

llvm-svn: 99590
 2010-03-26 01:07:59 +00:00
Johnny Chen d82f9002e4 Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to 
expect a Format arg.  N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.

llvm-svn: 99548
 2010-03-25 20:39:04 +00:00
Johnny Chen 45ab3f3ccf Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ, 
instead of the current N2V.  Format of NVDupLane instances are set to NEONFrm
currently.

llvm-svn: 99518
 2010-03-25 17:01:27 +00:00
Johnny Chen bff23ca690 Trivial formating change. 
llvm-svn: 99428
 2010-03-24 21:25:07 +00:00
Johnny Chen e99953ce9c Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm. 
NVCVTFrm will later be used to describe "vcvt with fractional bits".

llvm-svn: 99415
 2010-03-24 19:47:14 +00:00
Johnny Chen da44d5977f Reverted r99376. The disassembler will deal with the 2-reg format of these two 
N3VX instructions using special case code.

llvm-svn: 99409
 2010-03-24 18:46:34 +00:00
Johnny Chen aa9b1c81a7 Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler. 
llvm-svn: 99376
 2010-03-24 01:29:25 +00:00
Johnny Chen 9b1f60adec Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm, 
respectively, and add some more comment.

llvm-svn: 99373
 2010-03-24 00:57:50 +00:00
Johnny Chen 5be6d5a6a9 Add comment. 
llvm-svn: 99327
 2010-03-23 21:30:12 +00:00
Johnny Chen 5dbf39285d Add New NEON Format NVdVmVCVTFrm. 
Converted some of the NEON vcvt instructions to this format.

llvm-svn: 99326
 2010-03-23 21:25:38 +00:00
Bob Wilson 59f75bba24 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes. 
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

llvm-svn: 99309
 2010-03-23 18:54:46 +00:00
Bob Wilson 9b680e21c0 Rename some instructions to match the corresponding NEON opcode. 
llvm-svn: 99266
 2010-03-23 06:26:18 +00:00
Bob Wilson cc0a2a75a0 Change VST1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265
 2010-03-23 06:20:33 +00:00
Bob Wilson 340861d29e Change VLD1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261
 2010-03-23 05:25:43 +00:00
Bob Wilson e60e3ab624 Rename one more NEON instruction that I missed earlier. 
llvm-svn: 99201
 2010-03-22 20:31:39 +00:00
Bob Wilson c286c88db0 Regroup some instructions. No functional change. 
llvm-svn: 99192
 2010-03-22 18:22:06 +00:00
Bob Wilson c53a1125ff Rename some VLD1/VST1 instructions to match the implementation, i.e., the 
corresponding NEON instructions, instead of operation they are currently
used for.

llvm-svn: 99189
 2010-03-22 18:13:18 +00:00
Bob Wilson 98bf5189d7 Remove some redundant instruction classes. 
llvm-svn: 99187
 2010-03-22 18:02:38 +00:00
Bob Wilson debe0bdb13 Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to 
specify encoding bits in arguments instead of "let" expressions.

llvm-svn: 99185
 2010-03-22 16:43:10 +00:00
Bob Wilson ae08a736d6 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") 
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095
 2010-03-20 22:13:40 +00:00