Commit Graph

240285 Commits

Author SHA1 Message Date
Artur Pilipenko bc76ecada0 Revert -r278267 [ValueTracking] An improvement to IR ValueTracking on Non-negative Integers
This change cause performance regression on MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt from LNT and some other bechmarks.

See https://reviews.llvm.org/D18777 for details.

llvm-svn: 279433
2016-08-22 13:14:07 +00:00
Artur Pilipenko b78ad9d41f Revert -r278269 [IndVarSimplify] Eliminate zext of a signed IV when the IV is known to be non-negative
This change needs to be reverted in order to revert -r278267 which cause performance regression on MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt from LNT and some other bechmarks.

See comments on https://reviews.llvm.org/D18777 for details.

llvm-svn: 279432
2016-08-22 13:12:07 +00:00
Balaram Makam a927aa4ad0 [PM] Port LoopDataPrefetch AArch64 tests to new pass manager
Reviewers: mcrosier, tejohnson

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D23724

llvm-svn: 279431
2016-08-22 12:59:58 +00:00
Simon Pilgrim 2279e59573 [X86][SSE] Avoid specifying unused arguments in SHUFPD lowering
As discussed on PR26491, we are missing the opportunity to make use of the smaller MOVHLPS instruction because we set both arguments of a SHUFPD when using it to lower a single input shuffle.

This patch sets the lowered argument to UNDEF if that shuffle element is undefined. This in turn makes it easier for target shuffle combining to decode UNDEF shuffle elements, allowing combines to MOVHLPS to occur.

A fix to match against MOVHPD stores was necessary as well.

This builds on the improved MOVLHPS/MOVHLPS lowering and memory folding support added in D16956

Adding similar support for SHUFPS will have to wait until have better support for target combining of binary shuffles.

Differential Revision: https://reviews.llvm.org/D23027

llvm-svn: 279430
2016-08-22 12:56:54 +00:00
Hrvoje Varga f0ed16eae5 [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations
Differential Revision: https://reviews.llvm.org/D22667

llvm-svn: 279429
2016-08-22 12:17:59 +00:00
Davide Italiano 80d379f228 [MC] Remove guard(s). NFCI.
All the methods are already marked with
LLVM_DUMP_METHOD.

llvm-svn: 279428
2016-08-22 11:55:22 +00:00
Gabor Horvath b59b27040e Reapply "[analyzer] Added valist related checkers."
Differential Revision: https://reviews.llvm.org/D15227

llvm-svn: 279427
2016-08-22 11:21:30 +00:00
Simon Pilgrim 8738786bc1 [ThinLTO][X86] Fix windows build
Windows 'rm' complains about non-existent files if a wildcard is used. Be more explicit about the files deleted to avoid this.

llvm-svn: 279426
2016-08-22 10:49:37 +00:00
Gabor Horvath 855ad82e05 [analyzer] Correctly add assumptions based on array bounds.
Also simplify the constraints generated by the checker. 

Differential Revision: https://reviews.llvm.org/D23112

llvm-svn: 279425
2016-08-22 10:07:32 +00:00
Craig Topper 5f8419da34 [X86] Create a new instruction format to handle 4VOp3 encoding. This saves one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling.
llvm-svn: 279424
2016-08-22 07:38:50 +00:00
Craig Topper 9b20fece81 [X86] Create a new instruction format to handle MemOp4 encoding. This saves one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling.
llvm-svn: 279423
2016-08-22 07:38:45 +00:00
Craig Topper 61b62e56b7 [X86] Space out the encodings of X86 instruction formats. I plan to add some new encodings in future commits and this will reduce the size of those commits. NFC
This tries to keep all the ModRM memory and register forms in their own regions of the encodings. Hoping to make it simple on some of the switch statements that operate on these encodings.

llvm-svn: 279422
2016-08-22 07:38:41 +00:00
Craig Topper 1867c6acc7 [X86] Merge small helper function into the switch that calls it since they both operate on the same variable. NFC
llvm-svn: 279421
2016-08-22 07:38:36 +00:00
Craig Topper 313226fdbc [X86] Explicitly list all X86 instruction forms in switch statement so its easier to detect when one is missing. NFC
llvm-svn: 279420
2016-08-22 07:38:30 +00:00
Elad Cohen 13fc34b5b5 Test commit (Removing trailing whitespace).
llvm-svn: 279419
2016-08-22 07:34:21 +00:00
Mehdi Amini 35edfc5f13 Add REQUIRES:X86 to test/tools/llvm-lto2/common.ll
llvm-svn: 279418
2016-08-22 06:37:41 +00:00
Mehdi Amini dc4c8cf9ac [LTO] Handles commons in monolithic LTO
The gold-plugin was doing this internally, now the API is handling
commons correctly based on the given resolution.

Differential Revision: https://reviews.llvm.org/D23739

llvm-svn: 279417
2016-08-22 06:25:46 +00:00
Mehdi Amini d310b47c23 [LTO] Add a "CodeGenOnly" option. Allows the client to skip the optimizer.
Summary: Slowly getting on par with libLTO

Reviewers: tejohnson

Subscribers: llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D23615

llvm-svn: 279416
2016-08-22 06:25:41 +00:00
Rui Ueyama 189b871a62 Format.
llvm-svn: 279415
2016-08-22 04:55:41 +00:00
Rui Ueyama 464daadc3d Do not add .interp, .dynamic nor .eh_frame_hdr to segments just by type.
Summary:
We previously added these output sections to segments just by type.
Therefore, if there's a PHDRS command like this

  PHDRS {
    headers PT_PHDR PHDRS;
    interp PT_INTERP;
  }

  SECTIONS {
    . = SIZEOF_HEADERS;
    .interp : { *(.interp) } :text
  }

then .interp was added to "interp" segment even though the linker
is not instructed to do so by SECTIONS command. This patch removes
the default behavior to simplify.

Differential Revision: https://reviews.llvm.org/D23702

llvm-svn: 279414
2016-08-22 04:55:20 +00:00
Vitaly Buka 0672a27bb5 [asan] Use 1 byte aligned stores to poison shadow memory
Summary: r279379 introduced crash on arm 32bit bot. I suspect this is alignment issue.

Reviewers: eugenis

Subscribers: llvm-commits, aemerson

Differential Revision: https://reviews.llvm.org/D23762

llvm-svn: 279413
2016-08-22 04:16:14 +00:00
Craig Topper ca0eda3e6a [X86] Merge hasVEX_i8ImmReg into the ImmFormat type which had extra unused encodings. This saves one bit in TSFlags. NFC
llvm-svn: 279412
2016-08-22 01:37:19 +00:00
Craig Topper 522541231a [X86] Remove ignoreVEX_L from TSFlags. Only the disassembler needs it and the disassembler doesn't use TSFlags. NFC
llvm-svn: 279411
2016-08-22 01:37:16 +00:00
NAKAMURA Takumi 9d0b53129c Reformat.
llvm-svn: 279409
2016-08-22 00:58:47 +00:00
NAKAMURA Takumi 59a20649c6 Untabify.
llvm-svn: 279408
2016-08-22 00:58:04 +00:00
Saleem Abdulrasool 9f8bc029bd COFF: hoist a local variable
Create a local variable for the rdata section.  NFC.

llvm-svn: 279407
2016-08-21 23:05:43 +00:00
Simon Pilgrim 89e375a95e [CostModel][X86] Removed shift tests
There are more thorough tests found in vshift-*-cost.ll 

llvm-svn: 279406
2016-08-21 19:56:02 +00:00
Simon Pilgrim 6ad12ec629 [CostModel][X86] Added costs for vXi16 and vXi8 vectors for add/sub/mul/and/or/xor tests
llvm-svn: 279405
2016-08-21 19:44:44 +00:00
Simon Pilgrim b0a0576ffc [CostModel][X86] Replaced SSSE3 with SSE2 costs to create a better baseline
llvm-svn: 279404
2016-08-21 19:14:48 +00:00
Simon Pilgrim 07d7a21ea1 [CostModel][X86] Added fsqrt and fma costs
llvm-svn: 279403
2016-08-21 19:06:25 +00:00
Simon Pilgrim 3cd61a084f [CostModel][X86] Split off float arithmetic cost tests
llvm-svn: 279402
2016-08-21 18:34:47 +00:00
Sanjay Patel 643d21a62c [InstCombine] use m_APInt to allow icmp (shl X, Y), C folds for splat constant vectors, part 4
This concludes the fixes for icmp+shl in this series:
https://reviews.llvm.org/rL279339
https://reviews.llvm.org/rL279398
https://reviews.llvm.org/rL279399

llvm-svn: 279401
2016-08-21 17:10:07 +00:00
Sanjay Patel 163a5ab799 remove FIXME comment; fixed by previous commit
llvm-svn: 279400
2016-08-21 16:40:42 +00:00
Sanjay Patel 7ffcde7422 [InstCombine] use m_APInt to allow icmp (shl X, Y), C folds for splat constant vectors, part 3
This is a partial enablement (move the ConstantInt guard down).

llvm-svn: 279399
2016-08-21 16:35:34 +00:00
Sanjay Patel 7e09f13fed [InstCombine] use m_APInt to allow icmp (shl X, Y), C folds for splat constant vectors, part 2
This is a partial enablement (move the ConstantInt guard down).

llvm-svn: 279398
2016-08-21 16:28:22 +00:00
Simon Pilgrim 67e7e22462 [X86][AVX] Dropped combineShuffle256 - this can now be performed by EltsFromConsecutiveLoads
llvm-svn: 279397
2016-08-21 15:39:45 +00:00
Sanjay Patel 792636603f [InstCombine] use APInt instead of ConstantInt in isSignBitCheck(); NFCI
The callers still have ConstantInt guards, so there is no functional change
intended from this change. But relaxing the callers will allow more folds
for vector types.

llvm-svn: 279396
2016-08-21 15:07:45 +00:00
Roman Gareev 5f99f8656e Add a flag to dump SCoP optimized with the IslScheduleOptimizer pass
Dump polyhedral descriptions of Scops optimized with the isl scheduling
optimizer and the set of post-scheduling transformations applied
on the schedule tree to be able to check the work of the IslScheduleOptimizer
pass at the polyhedral level.

Reviewed-by: Tobias Grosser <tobias@grosser.es>

Differential Revision: https://reviews.llvm.org/D23740

llvm-svn: 279395
2016-08-21 11:20:39 +00:00
Roman Gareev e2ee79afde Simplify AccFuncMap to vector<> AccessFunctions
getAccessFunctions() is dead code and the 'BB' argument
of getOrCreateAccessFunctions() is not used. This patch deletes
getAccessFunctions and transforms AccFuncMap into
a std::vector<std::unique_ptr<MemoryAccess>> AccessFunctions.

Reviewed-by: Tobias Grosser <tobias@grosser.es>

Differential Revision: https://reviews.llvm.org/D23759

llvm-svn: 279394
2016-08-21 11:09:19 +00:00
Guy Blank 9ae797a798 [AVX512][FastISel] Do not use K registers in TEST instructions
In some cases, FastIsel was emitting TEST instruction with K reg input, which is illegal.
Changed to using KORTEST when dealing with K regs.

Differential Revision: https://reviews.llvm.org/D23163

llvm-svn: 279393
2016-08-21 08:02:27 +00:00
Asaf Badouh 356bb76809 [X86][AVX512F] minor fix of the parameter names
add "__" prefix

Bug 28842 https://llvm.org/bugs/show_bug.cgi?id=29040

Differential Revision: https://reviews.llvm.org/D23753


 

llvm-svn: 279392
2016-08-21 07:56:47 +00:00
Duncan P. N. Exon Smith 8f44c98d04 ARM: Avoid dereferencing end() in ARMFrameLowering::emitEpilogue
This fixes the crash from PR29072, where the MachineBasicBlock::iterator
wasn't being properly checked against MachineBasicBlock::end() before
iterating.  This was another bug exposed by the new
ilist::iterator::operator*() assertion from r279314.

This testcase is poor quality.  bugpoint couldn't reduce any further,
and I haven't had time to dig into what's going on so I can't invent a
better one.  I didn't even get good CHECK lines in: this is just a
crasher.

I'm committing anyway since this is a real crash with an obvious fix,
but I'll leave PR29072 open and ask an ARM maintainer to help improve
the testcase.

llvm-svn: 279391
2016-08-21 00:08:10 +00:00
Todd Fiala 3b40aa57f6 Fix broken macOS LLDB Xcode build from r279314
llvm-svn: 279390
2016-08-20 23:24:02 +00:00
Simon Pilgrim 636422a898 [X86][SSE] Regenerate 32-bit buildvector test
llvm-svn: 279389
2016-08-20 23:09:57 +00:00
Simon Pilgrim ead5076753 [X86][SSE] Regenerate subvector extraction widening test
llvm-svn: 279388
2016-08-20 22:00:53 +00:00
Simon Pilgrim b65d476549 [X86] Regenerate fp truncate tests
llvm-svn: 279387
2016-08-20 21:56:33 +00:00
Simon Pilgrim 8275583be6 Regenerate test
llvm-svn: 279386
2016-08-20 21:37:30 +00:00
Simon Pilgrim a1142579f1 Regenerate test
llvm-svn: 279385
2016-08-20 21:35:45 +00:00
Simon Pilgrim ae9b81e684 [X86][XOP] Tweak vpermil2pd test to stop it being combined away
llvm-svn: 279384
2016-08-20 21:07:41 +00:00
Vitaly Buka 1f9e135023 [asan] Minimize code size by using __asan_set_shadow_* for large blocks
Summary:
We can insert function call instead of multiple store operation.
Current default is blocks larger than 64 bytes.
Changes are hidden behind -asan-experimental-poisoning flag.

PR27453

Differential Revision: https://reviews.llvm.org/D23711

llvm-svn: 279383
2016-08-20 20:23:50 +00:00