f54c9395e7
remove RET hack, add proper support for rets (watching out for ret voids)
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llvm-svn: 25486
2006-01-20 20:24:31 +00:00
9a8fb20689
fix storing bools! eek!
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llvm-svn: 25476
2006-01-20 03:40:25 +00:00
550d8ec1ad
fix boolean XOR (which fixes up comparisons..)
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llvm-svn: 25462
2006-01-19 15:18:56 +00:00
266ff6056a
use proper (82-bit) spills/fills when spilling FP regs, so that
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divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)
llvm-svn: 25385
2006-01-17 02:04:52 +00:00
ba187774fe
fix division! again!! pattern isel, prepare to die.
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llvm-svn: 25353
2006-01-16 06:33:38 +00:00
c712fd6b4e
this just might work
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llvm-svn: 25195
2006-01-11 01:38:07 +00:00
0d5d08b26e
add support for selecting bools
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FIXME: this is commented out because it makes tblgen go a bit fruity
llvm-svn: 25193
2006-01-11 01:21:12 +00:00
14c53b45f5
Added field noResults to Instruction.
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Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
06dcc199f0
we don't feed our call instructions extra operands
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llvm-svn: 25009
2005-12-25 14:07:01 +00:00
3608ab87c0
oops, back this out
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llvm-svn: 24950
2005-12-22 07:13:51 +00:00
a8de8a5db4
we need to emit the getf.d instruction in lowering, so add it
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to IA64ISD
llvm-svn: 24946
2005-12-22 06:38:38 +00:00
a743e00e7a
update tablegen files - nothing to see here
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llvm-svn: 24939
2005-12-22 03:56:03 +00:00
c54cddd25b
Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.
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llvm-svn: 24595
2005-12-05 02:34:29 +00:00
76034f95f6
add FP select. next up - divide!
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llvm-svn: 24346
2005-11-14 01:17:30 +00:00
7ac646ef95
fun with predicates! (add TRUNC i64->i1, AND i1 i1, fix XOR i1 i1)
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llvm-svn: 24175
2005-11-04 00:57:56 +00:00
f0f22a55b0
add pattern to load constant 0 into a predicate reg
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llvm-svn: 24164
2005-11-03 10:09:32 +00:00
674660ff03
Fix a bug that prevented this pattern from matching
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llvm-svn: 24161
2005-11-03 05:45:34 +00:00
b5310bdbe9
This works now
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llvm-svn: 24150
2005-11-02 06:49:37 +00:00
17decbb253
add support for SELECT to TargetSelectionDAG.td, add support for
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selecting ints to IA64, and a few other ia64 bits and pieces
llvm-svn: 24147
2005-11-02 02:37:18 +00:00
b81b61330e
so tablegen was thinking I might want to convert FPs to predicates.
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clever little tablegen!
llvm-svn: 24133
2005-11-01 03:32:15 +00:00
6c912bffd6
add support for int->FP and FP->int ops, and add ia64 patterns for these
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llvm-svn: 24132
2005-11-01 03:07:25 +00:00
a284b6636f
add zeroextend predicate->integer
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llvm-svn: 24131
2005-11-01 01:29:55 +00:00
88fc69f627
add FP compares and implicit register defs to the dag isel
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llvm-svn: 24118
2005-10-31 01:42:11 +00:00
57b7ee9da8
fix some broken comparisons, this affected the Pattern isel too.
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llvm-svn: 24109
2005-10-30 10:14:19 +00:00
7abaf906e2
add some FP stuff, some mix.* stuff, and constant pool support to the
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DAG instruction selector, which should be destroyed one day (in the pattern
isel also) since ia64 can pack any constant in the instruction stream
llvm-svn: 24094
2005-10-29 16:08:30 +00:00
c252f33fdb
add shladd
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llvm-svn: 24080
2005-10-29 04:13:40 +00:00
f221c261f3
DAG->DAG instruction selection for ia64! "hello world" works, not much else.
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use -enable-ia64-dag-isel to turn this on
TODO: delete lowering stuff from the pattern isel
: get operations on predicate bits working
: get other bits of pseudocode going
: use sampo's mulh/mull-using divide-by-constant magic
: *so* many patterns ("extr", "tbit" and "dep" will be fun :)
: add FP
: add a JIT!
: get it working 100%
in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.
OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.
llvm-svn: 24058
2005-10-28 17:46:35 +00:00
9e4a4ee3dc
Give all operands names
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llvm-svn: 23357
2005-09-14 21:11:13 +00:00
3e0335c9d1
Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR.
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I'm not convinced this is all of them, but I can't do much testing, because
IA64 LLC crashes on big programs :(
llvm-svn: 22892
2005-08-19 00:47:42 +00:00
25163d8d60
add the popcount instruction and support this in the isel
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the primary user of this will probably end up being find-first-set-bit/find-
last-set-bit, which i'll get around to...
llvm-svn: 21860
2005-05-11 05:16:09 +00:00
0a7c2b9078
print negative 64 bit immediates as negative numbers, makes things a little
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easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything
llvm-svn: 21300
2005-04-14 10:08:01 +00:00
2f2312575b
* add the shladd instruction
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* fold left shifts of 1, 2, 3 or 4 bits into adds
This doesn't save much now, but should get a serious workout once
multiplies by constants get converted to shift/add/sub sequences.
Hold on! :)
llvm-svn: 21282
2005-04-13 06:12:04 +00:00
6b91767b77
Make sure to realize that calls use their argument regs
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llvm-svn: 21248
2005-04-12 15:12:19 +00:00
fb43ef78c5
assorted fixes:
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* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
* fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
* fix nasty thinko - didn't use two-address form of conditional add
for extending bools to integers, so occasionally there would be
garbage in the result. it's amazing how often zeros are just
sitting around in registers ;) - this should fix a bunch of tests.
llvm-svn: 21221
2005-04-11 05:55:56 +00:00
41ff502549
fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn)
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fix hack in division (clean up frcpa instruction)
llvm-svn: 21153
2005-04-08 10:01:48 +00:00
b484f7c55e
add immediate forms of add, sub, shift
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llvm-svn: 21129
2005-04-07 12:32:24 +00:00
03c530786c
add fms instruction
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llvm-svn: 21112
2005-04-06 09:54:09 +00:00
dbc810022b
add implicit use op
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llvm-svn: 21074
2005-04-04 04:50:57 +00:00
0ccac38ed3
add fnegabs op
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llvm-svn: 21022
2005-04-02 10:06:27 +00:00
0720dc14ed
add support FNEG and FABS
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llvm-svn: 21012
2005-04-02 05:18:38 +00:00
73c2777a0e
add what we need to fudge a 'floating point conditional move', this is
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used to get FP div-by-zero working properly (shunt the right answer
depending on how frcpa sets its predicate output)
llvm-svn: 20954
2005-03-31 07:32:32 +00:00
91ed0a11cf
and so it begins...
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PHASE 1: write instruction selector
PHASE 2: ???
PHASE 3: profit!
llvm-svn: 20652
2005-03-17 18:17:03 +00:00
Duraid Madina